18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __SOC_ARC_TIMERS_H 78c2ecf20Sopenharmony_ci#define __SOC_ARC_TIMERS_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <soc/arc/aux.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* Timer related Aux registers */ 128c2ecf20Sopenharmony_ci#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 138c2ecf20Sopenharmony_ci#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 148c2ecf20Sopenharmony_ci#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 158c2ecf20Sopenharmony_ci#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 168c2ecf20Sopenharmony_ci#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 178c2ecf20Sopenharmony_ci#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci/* CTRL reg bits */ 208c2ecf20Sopenharmony_ci#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 218c2ecf20Sopenharmony_ci#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define ARC_TIMERN_MAX 0xFFFFFFFF 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define ARC_REG_TIMERS_BCR 0x75 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_cistruct bcr_timer { 288c2ecf20Sopenharmony_ci#ifdef CONFIG_CPU_BIG_ENDIAN 298c2ecf20Sopenharmony_ci unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 308c2ecf20Sopenharmony_ci#else 318c2ecf20Sopenharmony_ci unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 328c2ecf20Sopenharmony_ci#endif 338c2ecf20Sopenharmony_ci}; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#endif 36