18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Header file for the Atmel AHB DMA Controller driver
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Copyright (C) 2008 Atmel Corporation
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci#ifndef AT_HDMAC_H
88c2ecf20Sopenharmony_ci#define AT_HDMAC_H
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci#include <linux/dmaengine.h>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci/**
138c2ecf20Sopenharmony_ci * struct at_dma_platform_data - Controller configuration parameters
148c2ecf20Sopenharmony_ci * @nr_channels: Number of channels supported by hardware (max 8)
158c2ecf20Sopenharmony_ci * @cap_mask: dma_capability flags supported by the platform
168c2ecf20Sopenharmony_ci */
178c2ecf20Sopenharmony_cistruct at_dma_platform_data {
188c2ecf20Sopenharmony_ci	unsigned int	nr_channels;
198c2ecf20Sopenharmony_ci	dma_cap_mask_t  cap_mask;
208c2ecf20Sopenharmony_ci};
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci/**
238c2ecf20Sopenharmony_ci * struct at_dma_slave - Controller-specific information about a slave
248c2ecf20Sopenharmony_ci * @dma_dev: required DMA master device
258c2ecf20Sopenharmony_ci * @cfg: Platform-specific initializer for the CFG register
268c2ecf20Sopenharmony_ci */
278c2ecf20Sopenharmony_cistruct at_dma_slave {
288c2ecf20Sopenharmony_ci	struct device		*dma_dev;
298c2ecf20Sopenharmony_ci	u32			cfg;
308c2ecf20Sopenharmony_ci};
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci/* Platform-configurable bits in CFG */
348c2ecf20Sopenharmony_ci#define ATC_PER_MSB(h)	((0x30U & (h)) >> 4)	/* Extract most significant bits of a handshaking identifier */
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci#define	ATC_SRC_PER(h)		(0xFU & (h))	/* Channel src rq associated with periph handshaking ifc h */
378c2ecf20Sopenharmony_ci#define	ATC_DST_PER(h)		((0xFU & (h)) <<  4)	/* Channel dst rq associated with periph handshaking ifc h */
388c2ecf20Sopenharmony_ci#define	ATC_SRC_REP		(0x1 <<  8)	/* Source Replay Mod */
398c2ecf20Sopenharmony_ci#define	ATC_SRC_H2SEL		(0x1 <<  9)	/* Source Handshaking Mod */
408c2ecf20Sopenharmony_ci#define		ATC_SRC_H2SEL_SW	(0x0 <<  9)
418c2ecf20Sopenharmony_ci#define		ATC_SRC_H2SEL_HW	(0x1 <<  9)
428c2ecf20Sopenharmony_ci#define	ATC_SRC_PER_MSB(h)	(ATC_PER_MSB(h) << 10)	/* Channel src rq (most significant bits) */
438c2ecf20Sopenharmony_ci#define	ATC_DST_REP		(0x1 << 12)	/* Destination Replay Mod */
448c2ecf20Sopenharmony_ci#define	ATC_DST_H2SEL		(0x1 << 13)	/* Destination Handshaking Mod */
458c2ecf20Sopenharmony_ci#define		ATC_DST_H2SEL_SW	(0x0 << 13)
468c2ecf20Sopenharmony_ci#define		ATC_DST_H2SEL_HW	(0x1 << 13)
478c2ecf20Sopenharmony_ci#define	ATC_DST_PER_MSB(h)	(ATC_PER_MSB(h) << 14)	/* Channel dst rq (most significant bits) */
488c2ecf20Sopenharmony_ci#define	ATC_SOD			(0x1 << 16)	/* Stop On Done */
498c2ecf20Sopenharmony_ci#define	ATC_LOCK_IF		(0x1 << 20)	/* Interface Lock */
508c2ecf20Sopenharmony_ci#define	ATC_LOCK_B		(0x1 << 21)	/* AHB Bus Lock */
518c2ecf20Sopenharmony_ci#define	ATC_LOCK_IF_L		(0x1 << 22)	/* Master Interface Arbiter Lock */
528c2ecf20Sopenharmony_ci#define		ATC_LOCK_IF_L_CHUNK	(0x0 << 22)
538c2ecf20Sopenharmony_ci#define		ATC_LOCK_IF_L_BUFFER	(0x1 << 22)
548c2ecf20Sopenharmony_ci#define	ATC_AHB_PROT_MASK	(0x7 << 24)	/* AHB Protection */
558c2ecf20Sopenharmony_ci#define	ATC_FIFOCFG_MASK	(0x3 << 28)	/* FIFO Request Configuration */
568c2ecf20Sopenharmony_ci#define		ATC_FIFOCFG_LARGESTBURST	(0x0 << 28)
578c2ecf20Sopenharmony_ci#define		ATC_FIFOCFG_HALFFIFO		(0x1 << 28)
588c2ecf20Sopenharmony_ci#define		ATC_FIFOCFG_ENOUGHSPACE		(0x2 << 28)
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ci#endif /* AT_HDMAC_H */
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