18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * ARM PL353 SMC Driver Header 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2012 - 2018 Xilinx, Inc 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef __LINUX_PL353_SMC_H 98c2ecf20Sopenharmony_ci#define __LINUX_PL353_SMC_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_cienum pl353_smc_ecc_mode { 128c2ecf20Sopenharmony_ci PL353_SMC_ECCMODE_BYPASS = 0, 138c2ecf20Sopenharmony_ci PL353_SMC_ECCMODE_APB = 1, 148c2ecf20Sopenharmony_ci PL353_SMC_ECCMODE_MEM = 2 158c2ecf20Sopenharmony_ci}; 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cienum pl353_smc_mem_width { 188c2ecf20Sopenharmony_ci PL353_SMC_MEM_WIDTH_8 = 0, 198c2ecf20Sopenharmony_ci PL353_SMC_MEM_WIDTH_16 = 1 208c2ecf20Sopenharmony_ci}; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciu32 pl353_smc_get_ecc_val(int ecc_reg); 238c2ecf20Sopenharmony_cibool pl353_smc_ecc_is_busy(void); 248c2ecf20Sopenharmony_ciint pl353_smc_get_nand_int_status_raw(void); 258c2ecf20Sopenharmony_civoid pl353_smc_clr_nand_int(void); 268c2ecf20Sopenharmony_ciint pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode); 278c2ecf20Sopenharmony_ciint pl353_smc_set_ecc_pg_size(unsigned int pg_sz); 288c2ecf20Sopenharmony_ciint pl353_smc_set_buswidth(unsigned int bw); 298c2ecf20Sopenharmony_civoid pl353_smc_set_cycles(u32 timings[]); 308c2ecf20Sopenharmony_ci#endif 31