1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * twl4030.h - header for TWL4030 PM and audio CODEC device 4 * 5 * Copyright (C) 2005-2006 Texas Instruments, Inc. 6 * 7 * Based on tlv320aic23.c: 8 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 9 */ 10 11#ifndef __TWL_H_ 12#define __TWL_H_ 13 14#include <linux/types.h> 15#include <linux/input/matrix_keypad.h> 16 17/* 18 * Using the twl4030 core we address registers using a pair 19 * { module id, relative register offset } 20 * which that core then maps to the relevant 21 * { i2c slave, absolute register address } 22 * 23 * The module IDs are meaningful only to the twl4030 core code, 24 * which uses them as array indices to look up the first register 25 * address each module uses within a given i2c slave. 26 */ 27 28/* Module IDs for similar functionalities found in twl4030/twl6030 */ 29enum twl_module_ids { 30 TWL_MODULE_USB, 31 TWL_MODULE_PIH, 32 TWL_MODULE_MAIN_CHARGE, 33 TWL_MODULE_PM_MASTER, 34 TWL_MODULE_PM_RECEIVER, 35 36 TWL_MODULE_RTC, 37 TWL_MODULE_PWM, 38 TWL_MODULE_LED, 39 TWL_MODULE_SECURED_REG, 40 41 TWL_MODULE_LAST, 42}; 43 44/* Modules only available in twl4030 series */ 45enum twl4030_module_ids { 46 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST, 47 TWL4030_MODULE_GPIO, 48 TWL4030_MODULE_INTBR, 49 TWL4030_MODULE_TEST, 50 TWL4030_MODULE_KEYPAD, 51 52 TWL4030_MODULE_MADC, 53 TWL4030_MODULE_INTERRUPTS, 54 TWL4030_MODULE_PRECHARGE, 55 TWL4030_MODULE_BACKUP, 56 TWL4030_MODULE_INT, 57 58 TWL5031_MODULE_ACCESSORY, 59 TWL5031_MODULE_INTERRUPTS, 60 61 TWL4030_MODULE_LAST, 62}; 63 64/* Modules only available in twl6030 series */ 65enum twl6030_module_ids { 66 TWL6030_MODULE_ID0 = TWL_MODULE_LAST, 67 TWL6030_MODULE_ID1, 68 TWL6030_MODULE_ID2, 69 TWL6030_MODULE_GPADC, 70 TWL6030_MODULE_GASGAUGE, 71 72 TWL6030_MODULE_LAST, 73}; 74 75/* Until the clients has been converted to use TWL_MODULE_LED */ 76#define TWL4030_MODULE_LED TWL_MODULE_LED 77 78#define GPIO_INTR_OFFSET 0 79#define KEYPAD_INTR_OFFSET 1 80#define BCI_INTR_OFFSET 2 81#define MADC_INTR_OFFSET 3 82#define USB_INTR_OFFSET 4 83#define CHARGERFAULT_INTR_OFFSET 5 84#define BCI_PRES_INTR_OFFSET 9 85#define USB_PRES_INTR_OFFSET 10 86#define RTC_INTR_OFFSET 11 87 88/* 89 * Offset from TWL6030_IRQ_BASE / pdata->irq_base 90 */ 91#define PWR_INTR_OFFSET 0 92#define HOTDIE_INTR_OFFSET 12 93#define SMPSLDO_INTR_OFFSET 13 94#define BATDETECT_INTR_OFFSET 14 95#define SIMDETECT_INTR_OFFSET 15 96#define MMCDETECT_INTR_OFFSET 16 97#define GASGAUGE_INTR_OFFSET 17 98#define USBOTG_INTR_OFFSET 4 99#define CHARGER_INTR_OFFSET 2 100#define RSV_INTR_OFFSET 0 101 102/* INT register offsets */ 103#define REG_INT_STS_A 0x00 104#define REG_INT_STS_B 0x01 105#define REG_INT_STS_C 0x02 106 107#define REG_INT_MSK_LINE_A 0x03 108#define REG_INT_MSK_LINE_B 0x04 109#define REG_INT_MSK_LINE_C 0x05 110 111#define REG_INT_MSK_STS_A 0x06 112#define REG_INT_MSK_STS_B 0x07 113#define REG_INT_MSK_STS_C 0x08 114 115/* MASK INT REG GROUP A */ 116#define TWL6030_PWR_INT_MASK 0x07 117#define TWL6030_RTC_INT_MASK 0x18 118#define TWL6030_HOTDIE_INT_MASK 0x20 119#define TWL6030_SMPSLDOA_INT_MASK 0xC0 120 121/* MASK INT REG GROUP B */ 122#define TWL6030_SMPSLDOB_INT_MASK 0x01 123#define TWL6030_BATDETECT_INT_MASK 0x02 124#define TWL6030_SIMDETECT_INT_MASK 0x04 125#define TWL6030_MMCDETECT_INT_MASK 0x08 126#define TWL6030_GPADC_INT_MASK 0x60 127#define TWL6030_GASGAUGE_INT_MASK 0x80 128 129/* MASK INT REG GROUP C */ 130#define TWL6030_USBOTG_INT_MASK 0x0F 131#define TWL6030_CHARGER_CTRL_INT_MASK 0x10 132#define TWL6030_CHARGER_FAULT_INT_MASK 0x60 133 134#define TWL6030_MMCCTRL 0xEE 135#define VMMC_AUTO_OFF (0x1 << 3) 136#define SW_FC (0x1 << 2) 137#define STS_MMC 0x1 138 139#define TWL6030_CFG_INPUT_PUPD3 0xF2 140#define MMC_PU (0x1 << 3) 141#define MMC_PD (0x1 << 2) 142 143#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) 144#define TWL_SIL_REV(rev) ((rev) >> 24) 145#define TWL_SIL_5030 0x09002F 146#define TWL5030_REV_1_0 0x00 147#define TWL5030_REV_1_1 0x10 148#define TWL5030_REV_1_2 0x30 149 150#define TWL4030_CLASS_ID 0x4030 151#define TWL6030_CLASS_ID 0x6030 152unsigned int twl_rev(void); 153#define GET_TWL_REV (twl_rev()) 154#define TWL_CLASS_IS(class, id) \ 155static inline int twl_class_is_ ##class(void) \ 156{ \ 157 return ((id) == (GET_TWL_REV)) ? 1 : 0; \ 158} 159 160TWL_CLASS_IS(4030, TWL4030_CLASS_ID) 161TWL_CLASS_IS(6030, TWL6030_CLASS_ID) 162 163/* Set the regcache bypass for the regmap associated with the nodule */ 164int twl_set_regcache_bypass(u8 mod_no, bool enable); 165 166/* 167 * Read and write several 8-bit registers at once. 168 */ 169int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 170int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 171 172/* 173 * Read and write single 8-bit registers 174 */ 175static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { 176 return twl_i2c_write(mod_no, &val, reg, 1); 177} 178 179static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { 180 return twl_i2c_read(mod_no, val, reg, 1); 181} 182 183static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { 184 __le16 value; 185 186 value = cpu_to_le16(val); 187 return twl_i2c_write(mod_no, (u8 *) &value, reg, 2); 188} 189 190static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { 191 int ret; 192 __le16 value; 193 194 ret = twl_i2c_read(mod_no, (u8 *) &value, reg, 2); 195 *val = le16_to_cpu(value); 196 return ret; 197} 198 199int twl_get_type(void); 200int twl_get_version(void); 201int twl_get_hfclk_rate(void); 202 203int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); 204int twl6030_interrupt_mask(u8 bit_mask, u8 offset); 205 206/* Card detect Configuration for MMC1 Controller on OMAP4 */ 207#ifdef CONFIG_TWL4030_CORE 208int twl6030_mmc_card_detect_config(void); 209#else 210static inline int twl6030_mmc_card_detect_config(void) 211{ 212 pr_debug("twl6030_mmc_card_detect_config not supported\n"); 213 return 0; 214} 215#endif 216 217/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ 218#ifdef CONFIG_TWL4030_CORE 219int twl6030_mmc_card_detect(struct device *dev, int slot); 220#else 221static inline int twl6030_mmc_card_detect(struct device *dev, int slot) 222{ 223 pr_debug("Call back twl6030_mmc_card_detect not supported\n"); 224 return -EIO; 225} 226#endif 227/*----------------------------------------------------------------------*/ 228 229/* 230 * NOTE: at up to 1024 registers, this is a big chip. 231 * 232 * Avoid putting register declarations in this file, instead of into 233 * a driver-private file, unless some of the registers in a block 234 * need to be shared with other drivers. One example is blocks that 235 * have Secondary IRQ Handler (SIH) registers. 236 */ 237 238#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) 239#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) 240#define TWL4030_SIH_CTRL_COR_MASK BIT(2) 241 242/*----------------------------------------------------------------------*/ 243 244/* 245 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) 246 */ 247 248#define REG_GPIODATAIN1 0x0 249#define REG_GPIODATAIN2 0x1 250#define REG_GPIODATAIN3 0x2 251#define REG_GPIODATADIR1 0x3 252#define REG_GPIODATADIR2 0x4 253#define REG_GPIODATADIR3 0x5 254#define REG_GPIODATAOUT1 0x6 255#define REG_GPIODATAOUT2 0x7 256#define REG_GPIODATAOUT3 0x8 257#define REG_CLEARGPIODATAOUT1 0x9 258#define REG_CLEARGPIODATAOUT2 0xA 259#define REG_CLEARGPIODATAOUT3 0xB 260#define REG_SETGPIODATAOUT1 0xC 261#define REG_SETGPIODATAOUT2 0xD 262#define REG_SETGPIODATAOUT3 0xE 263#define REG_GPIO_DEBEN1 0xF 264#define REG_GPIO_DEBEN2 0x10 265#define REG_GPIO_DEBEN3 0x11 266#define REG_GPIO_CTRL 0x12 267#define REG_GPIOPUPDCTR1 0x13 268#define REG_GPIOPUPDCTR2 0x14 269#define REG_GPIOPUPDCTR3 0x15 270#define REG_GPIOPUPDCTR4 0x16 271#define REG_GPIOPUPDCTR5 0x17 272#define REG_GPIO_ISR1A 0x19 273#define REG_GPIO_ISR2A 0x1A 274#define REG_GPIO_ISR3A 0x1B 275#define REG_GPIO_IMR1A 0x1C 276#define REG_GPIO_IMR2A 0x1D 277#define REG_GPIO_IMR3A 0x1E 278#define REG_GPIO_ISR1B 0x1F 279#define REG_GPIO_ISR2B 0x20 280#define REG_GPIO_ISR3B 0x21 281#define REG_GPIO_IMR1B 0x22 282#define REG_GPIO_IMR2B 0x23 283#define REG_GPIO_IMR3B 0x24 284#define REG_GPIO_EDR1 0x28 285#define REG_GPIO_EDR2 0x29 286#define REG_GPIO_EDR3 0x2A 287#define REG_GPIO_EDR4 0x2B 288#define REG_GPIO_EDR5 0x2C 289#define REG_GPIO_SIH_CTRL 0x2D 290 291/* Up to 18 signals are available as GPIOs, when their 292 * pins are not assigned to another use (such as ULPI/USB). 293 */ 294#define TWL4030_GPIO_MAX 18 295 296/*----------------------------------------------------------------------*/ 297 298/*Interface Bit Register (INTBR) offsets 299 *(Use TWL_4030_MODULE_INTBR) 300 */ 301 302#define REG_IDCODE_7_0 0x00 303#define REG_IDCODE_15_8 0x01 304#define REG_IDCODE_16_23 0x02 305#define REG_IDCODE_31_24 0x03 306#define REG_GPPUPDCTR1 0x0F 307#define REG_UNLOCK_TEST_REG 0x12 308 309/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ 310 311#define I2C_SCL_CTRL_PU BIT(0) 312#define I2C_SDA_CTRL_PU BIT(2) 313#define SR_I2C_SCL_CTRL_PU BIT(4) 314#define SR_I2C_SDA_CTRL_PU BIT(6) 315 316#define TWL_EEPROM_R_UNLOCK 0x49 317 318/*----------------------------------------------------------------------*/ 319 320/* 321 * Keypad register offsets (use TWL4030_MODULE_KEYPAD) 322 * ... SIH/interrupt only 323 */ 324 325#define TWL4030_KEYPAD_KEYP_ISR1 0x11 326#define TWL4030_KEYPAD_KEYP_IMR1 0x12 327#define TWL4030_KEYPAD_KEYP_ISR2 0x13 328#define TWL4030_KEYPAD_KEYP_IMR2 0x14 329#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ 330#define TWL4030_KEYPAD_KEYP_EDR 0x16 331#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 332 333/*----------------------------------------------------------------------*/ 334 335/* 336 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) 337 * ... SIH/interrupt only 338 */ 339 340#define TWL4030_MADC_ISR1 0x61 341#define TWL4030_MADC_IMR1 0x62 342#define TWL4030_MADC_ISR2 0x63 343#define TWL4030_MADC_IMR2 0x64 344#define TWL4030_MADC_SIR 0x65 /* test register */ 345#define TWL4030_MADC_EDR 0x66 346#define TWL4030_MADC_SIH_CTRL 0x67 347 348/*----------------------------------------------------------------------*/ 349 350/* 351 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) 352 */ 353 354#define TWL4030_INTERRUPTS_BCIISR1A 0x0 355#define TWL4030_INTERRUPTS_BCIISR2A 0x1 356#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 357#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 358#define TWL4030_INTERRUPTS_BCIISR1B 0x4 359#define TWL4030_INTERRUPTS_BCIISR2B 0x5 360#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 361#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 362#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ 363#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ 364#define TWL4030_INTERRUPTS_BCIEDR1 0xa 365#define TWL4030_INTERRUPTS_BCIEDR2 0xb 366#define TWL4030_INTERRUPTS_BCIEDR3 0xc 367#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd 368 369/*----------------------------------------------------------------------*/ 370 371/* 372 * Power Interrupt block register offsets (use TWL4030_MODULE_INT) 373 */ 374 375#define TWL4030_INT_PWR_ISR1 0x0 376#define TWL4030_INT_PWR_IMR1 0x1 377#define TWL4030_INT_PWR_ISR2 0x2 378#define TWL4030_INT_PWR_IMR2 0x3 379#define TWL4030_INT_PWR_SIR 0x4 /* test register */ 380#define TWL4030_INT_PWR_EDR1 0x5 381#define TWL4030_INT_PWR_EDR2 0x6 382#define TWL4030_INT_PWR_SIH_CTRL 0x7 383 384/*----------------------------------------------------------------------*/ 385 386/* 387 * Accessory Interrupts 388 */ 389#define TWL5031_ACIIMR_LSB 0x05 390#define TWL5031_ACIIMR_MSB 0x06 391#define TWL5031_ACIIDR_LSB 0x07 392#define TWL5031_ACIIDR_MSB 0x08 393#define TWL5031_ACCISR1 0x0F 394#define TWL5031_ACCIMR1 0x10 395#define TWL5031_ACCISR2 0x11 396#define TWL5031_ACCIMR2 0x12 397#define TWL5031_ACCSIR 0x13 398#define TWL5031_ACCEDR1 0x14 399#define TWL5031_ACCSIHCTRL 0x15 400 401/*----------------------------------------------------------------------*/ 402 403/* 404 * Battery Charger Controller 405 */ 406 407#define TWL5031_INTERRUPTS_BCIISR1 0x0 408#define TWL5031_INTERRUPTS_BCIIMR1 0x1 409#define TWL5031_INTERRUPTS_BCIISR2 0x2 410#define TWL5031_INTERRUPTS_BCIIMR2 0x3 411#define TWL5031_INTERRUPTS_BCISIR 0x4 412#define TWL5031_INTERRUPTS_BCIEDR1 0x5 413#define TWL5031_INTERRUPTS_BCIEDR2 0x6 414#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 415 416/*----------------------------------------------------------------------*/ 417 418/* 419 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) 420 */ 421 422#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 423#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 424#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 425#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 426#define TWL4030_PM_MASTER_STS_BOOT 0x04 427#define TWL4030_PM_MASTER_CFG_BOOT 0x05 428#define TWL4030_PM_MASTER_SHUNDAN 0x06 429#define TWL4030_PM_MASTER_BOOT_BCI 0x07 430#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 431#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 432#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b 433#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c 434#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d 435#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e 436#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f 437#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 438#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 439#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 440#define TWL4030_PM_MASTER_STS_P123_STATE 0x13 441#define TWL4030_PM_MASTER_PB_CFG 0x14 442#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 443#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 444#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c 445#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d 446#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e 447#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f 448#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 449#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 450#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 451#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 452#define TWL4030_PM_MASTER_MEMORY_DATA 0x24 453 454#define TWL4030_PM_MASTER_KEY_CFG1 0xc0 455#define TWL4030_PM_MASTER_KEY_CFG2 0x0c 456 457#define TWL4030_PM_MASTER_KEY_TST1 0xe0 458#define TWL4030_PM_MASTER_KEY_TST2 0x0e 459 460#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 461 462/*----------------------------------------------------------------------*/ 463 464/* Power bus message definitions */ 465 466/* The TWL4030/5030 splits its power-management resources (the various 467 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and 468 * P3. These groups can then be configured to transition between sleep, wait-on 469 * and active states by sending messages to the power bus. See Section 5.4.2 470 * Power Resources of TWL4030 TRM 471 */ 472 473/* Processor groups */ 474#define DEV_GRP_NULL 0x0 475#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ 476#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ 477#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ 478 479/* Resource groups */ 480#define RES_GRP_RES 0x0 /* Reserved */ 481#define RES_GRP_PP 0x1 /* Power providers */ 482#define RES_GRP_RC 0x2 /* Reset and control */ 483#define RES_GRP_PP_RC 0x3 484#define RES_GRP_PR 0x4 /* Power references */ 485#define RES_GRP_PP_PR 0x5 486#define RES_GRP_RC_PR 0x6 487#define RES_GRP_ALL 0x7 /* All resource groups */ 488 489#define RES_TYPE2_R0 0x0 490#define RES_TYPE2_R1 0x1 491#define RES_TYPE2_R2 0x2 492 493#define RES_TYPE_R0 0x0 494#define RES_TYPE_ALL 0x7 495 496/* Resource states */ 497#define RES_STATE_WRST 0xF 498#define RES_STATE_ACTIVE 0xE 499#define RES_STATE_SLEEP 0x8 500#define RES_STATE_OFF 0x0 501 502/* Power resources */ 503 504/* Power providers */ 505#define RES_VAUX1 1 506#define RES_VAUX2 2 507#define RES_VAUX3 3 508#define RES_VAUX4 4 509#define RES_VMMC1 5 510#define RES_VMMC2 6 511#define RES_VPLL1 7 512#define RES_VPLL2 8 513#define RES_VSIM 9 514#define RES_VDAC 10 515#define RES_VINTANA1 11 516#define RES_VINTANA2 12 517#define RES_VINTDIG 13 518#define RES_VIO 14 519#define RES_VDD1 15 520#define RES_VDD2 16 521#define RES_VUSB_1V5 17 522#define RES_VUSB_1V8 18 523#define RES_VUSB_3V1 19 524#define RES_VUSBCP 20 525#define RES_REGEN 21 526/* Reset and control */ 527#define RES_NRES_PWRON 22 528#define RES_CLKEN 23 529#define RES_SYSEN 24 530#define RES_HFCLKOUT 25 531#define RES_32KCLKOUT 26 532#define RES_RESET 27 533/* Power Reference */ 534#define RES_MAIN_REF 28 535 536#define TOTAL_RESOURCES 28 537/* 538 * Power Bus Message Format ... these can be sent individually by Linux, 539 * but are usually part of downloaded scripts that are run when various 540 * power events are triggered. 541 * 542 * Broadcast Message (16 Bits): 543 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] 544 * RES_STATE[3:0] 545 * 546 * Singular Message (16 Bits): 547 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] 548 */ 549 550#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ 551 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ 552 | (type) << 4 | (state)) 553 554#define MSG_SINGULAR(devgrp, id, state) \ 555 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 556 557#define MSG_BROADCAST_ALL(devgrp, state) \ 558 ((devgrp) << 5 | (state)) 559 560#define MSG_BROADCAST_REF MSG_BROADCAST_ALL 561#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL 562#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL 563/*----------------------------------------------------------------------*/ 564 565struct twl4030_clock_init_data { 566 bool ck32k_lowpwr_enable; 567}; 568 569struct twl4030_bci_platform_data { 570 int *battery_tmp_tbl; 571 unsigned int tblsize; 572 int bb_uvolt; /* voltage to charge backup battery */ 573 int bb_uamp; /* current for backup battery charging */ 574}; 575 576/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ 577struct twl4030_gpio_platform_data { 578 /* package the two LED signals as output-only GPIOs? */ 579 bool use_leds; 580 581 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ 582 u8 mmc_cd; 583 584 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ 585 u32 debounce; 586 587 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup 588 * should be enabled. Else, if that bit is set in "pulldowns", 589 * that pulldown is enabled. Don't waste power by letting any 590 * digital inputs float... 591 */ 592 u32 pullups; 593 u32 pulldowns; 594 595 int (*setup)(struct device *dev, 596 unsigned gpio, unsigned ngpio); 597 int (*teardown)(struct device *dev, 598 unsigned gpio, unsigned ngpio); 599}; 600 601struct twl4030_madc_platform_data { 602 int irq_line; 603}; 604 605/* Boards have unique mappings of {row, col} --> keycode. 606 * Column and row are 8 bits each, but range only from 0..7. 607 * a PERSISTENT_KEY is "always on" and never reported. 608 */ 609#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) 610 611struct twl4030_keypad_data { 612 const struct matrix_keymap_data *keymap_data; 613 unsigned rows; 614 unsigned cols; 615 bool rep; 616}; 617 618enum twl4030_usb_mode { 619 T2_USB_MODE_ULPI = 1, 620 T2_USB_MODE_CEA2011_3PIN = 2, 621}; 622 623struct twl4030_usb_data { 624 enum twl4030_usb_mode usb_mode; 625 unsigned long features; 626 627 int (*phy_init)(struct device *dev); 628 int (*phy_exit)(struct device *dev); 629 /* Power on/off the PHY */ 630 int (*phy_power)(struct device *dev, int iD, int on); 631 /* enable/disable phy clocks */ 632 int (*phy_set_clock)(struct device *dev, int on); 633 /* suspend/resume of phy */ 634 int (*phy_suspend)(struct device *dev, int suspend); 635}; 636 637struct twl4030_ins { 638 u16 pmb_message; 639 u8 delay; 640}; 641 642struct twl4030_script { 643 struct twl4030_ins *script; 644 unsigned size; 645 u8 flags; 646#define TWL4030_WRST_SCRIPT (1<<0) 647#define TWL4030_WAKEUP12_SCRIPT (1<<1) 648#define TWL4030_WAKEUP3_SCRIPT (1<<2) 649#define TWL4030_SLEEP_SCRIPT (1<<3) 650}; 651 652struct twl4030_resconfig { 653 u8 resource; 654 u8 devgroup; /* Processor group that Power resource belongs to */ 655 u8 type; /* Power resource addressed, 6 / broadcast message */ 656 u8 type2; /* Power resource addressed, 3 / broadcast message */ 657 u8 remap_off; /* off state remapping */ 658 u8 remap_sleep; /* sleep state remapping */ 659}; 660 661struct twl4030_power_data { 662 struct twl4030_script **scripts; 663 unsigned num; 664 struct twl4030_resconfig *resource_config; 665 struct twl4030_resconfig *board_config; 666#define TWL4030_RESCONFIG_UNDEF ((u8)-1) 667 bool use_poweroff; /* Board is wired for TWL poweroff */ 668 bool ac_charger_quirk; /* Disable AC charger on board */ 669}; 670 671extern int twl4030_remove_script(u8 flags); 672extern void twl4030_power_off(void); 673 674struct twl4030_codec_data { 675 unsigned int digimic_delay; /* in ms */ 676 unsigned int ramp_delay_value; 677 unsigned int offset_cncl_path; 678 unsigned int hs_extmute:1; 679 int hs_extmute_gpio; 680}; 681 682struct twl4030_vibra_data { 683 unsigned int coexist; 684}; 685 686struct twl4030_audio_data { 687 unsigned int audio_mclk; 688 struct twl4030_codec_data *codec; 689 struct twl4030_vibra_data *vibra; 690 691 /* twl6040 */ 692 int audpwron_gpio; /* audio power-on gpio */ 693 int naudint_irq; /* audio interrupt */ 694 unsigned int irq_base; 695}; 696 697struct twl4030_platform_data { 698 struct twl4030_clock_init_data *clock; 699 struct twl4030_bci_platform_data *bci; 700 struct twl4030_gpio_platform_data *gpio; 701 struct twl4030_madc_platform_data *madc; 702 struct twl4030_keypad_data *keypad; 703 struct twl4030_usb_data *usb; 704 struct twl4030_power_data *power; 705 struct twl4030_audio_data *audio; 706 707 /* Common LDO regulators for TWL4030/TWL6030 */ 708 struct regulator_init_data *vdac; 709 struct regulator_init_data *vaux1; 710 struct regulator_init_data *vaux2; 711 struct regulator_init_data *vaux3; 712 struct regulator_init_data *vdd1; 713 struct regulator_init_data *vdd2; 714 struct regulator_init_data *vdd3; 715 /* TWL4030 LDO regulators */ 716 struct regulator_init_data *vpll1; 717 struct regulator_init_data *vpll2; 718 struct regulator_init_data *vmmc1; 719 struct regulator_init_data *vmmc2; 720 struct regulator_init_data *vsim; 721 struct regulator_init_data *vaux4; 722 struct regulator_init_data *vio; 723 struct regulator_init_data *vintana1; 724 struct regulator_init_data *vintana2; 725 struct regulator_init_data *vintdig; 726 /* TWL6030 LDO regulators */ 727 struct regulator_init_data *vmmc; 728 struct regulator_init_data *vpp; 729 struct regulator_init_data *vusim; 730 struct regulator_init_data *vana; 731 struct regulator_init_data *vcxio; 732 struct regulator_init_data *vusb; 733 struct regulator_init_data *clk32kg; 734 struct regulator_init_data *v1v8; 735 struct regulator_init_data *v2v1; 736 /* TWL6032 LDO regulators */ 737 struct regulator_init_data *ldo1; 738 struct regulator_init_data *ldo2; 739 struct regulator_init_data *ldo3; 740 struct regulator_init_data *ldo4; 741 struct regulator_init_data *ldo5; 742 struct regulator_init_data *ldo6; 743 struct regulator_init_data *ldo7; 744 struct regulator_init_data *ldoln; 745 struct regulator_init_data *ldousb; 746 /* TWL6032 DCDC regulators */ 747 struct regulator_init_data *smps3; 748 struct regulator_init_data *smps4; 749 struct regulator_init_data *vio6025; 750}; 751 752struct twl_regulator_driver_data { 753 int (*set_voltage)(void *data, int target_uV); 754 int (*get_voltage)(void *data); 755 void *data; 756 unsigned long features; 757}; 758/* chip-specific feature flags, for twl_regulator_driver_data.features */ 759#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */ 760#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */ 761#define TWL5031 BIT(2) /* twl5031 has different registers */ 762#define TWL6030_CLASS BIT(3) /* TWL6030 class */ 763#define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */ 764#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible 765 * but not officially supported. 766 * This flag is necessary to 767 * enable them. 768 */ 769 770/*----------------------------------------------------------------------*/ 771 772int twl4030_sih_setup(struct device *dev, int module, int irq_base); 773 774/* Offsets to Power Registers */ 775#define TWL4030_VDAC_DEV_GRP 0x3B 776#define TWL4030_VDAC_DEDICATED 0x3E 777#define TWL4030_VAUX1_DEV_GRP 0x17 778#define TWL4030_VAUX1_DEDICATED 0x1A 779#define TWL4030_VAUX2_DEV_GRP 0x1B 780#define TWL4030_VAUX2_DEDICATED 0x1E 781#define TWL4030_VAUX3_DEV_GRP 0x1F 782#define TWL4030_VAUX3_DEDICATED 0x22 783 784static inline int twl4030charger_usb_en(int enable) { return 0; } 785 786/*----------------------------------------------------------------------*/ 787 788/* Linux-specific regulator identifiers ... for now, we only support 789 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 790 * need to tie into hardware based voltage scaling (cpufreq etc), while 791 * VIO is generally fixed. 792 */ 793 794/* TWL4030 SMPS/LDO's */ 795/* EXTERNAL dc-to-dc buck converters */ 796#define TWL4030_REG_VDD1 0 797#define TWL4030_REG_VDD2 1 798#define TWL4030_REG_VIO 2 799 800/* EXTERNAL LDOs */ 801#define TWL4030_REG_VDAC 3 802#define TWL4030_REG_VPLL1 4 803#define TWL4030_REG_VPLL2 5 /* not on all chips */ 804#define TWL4030_REG_VMMC1 6 805#define TWL4030_REG_VMMC2 7 /* not on all chips */ 806#define TWL4030_REG_VSIM 8 /* not on all chips */ 807#define TWL4030_REG_VAUX1 9 /* not on all chips */ 808#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ 809#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ 810#define TWL4030_REG_VAUX3 12 /* not on all chips */ 811#define TWL4030_REG_VAUX4 13 /* not on all chips */ 812 813/* INTERNAL LDOs */ 814#define TWL4030_REG_VINTANA1 14 815#define TWL4030_REG_VINTANA2 15 816#define TWL4030_REG_VINTDIG 16 817#define TWL4030_REG_VUSB1V5 17 818#define TWL4030_REG_VUSB1V8 18 819#define TWL4030_REG_VUSB3V1 19 820 821/* TWL6030 SMPS/LDO's */ 822/* EXTERNAL dc-to-dc buck convertor controllable via SR */ 823#define TWL6030_REG_VDD1 30 824#define TWL6030_REG_VDD2 31 825#define TWL6030_REG_VDD3 32 826 827/* Non SR compliant dc-to-dc buck convertors */ 828#define TWL6030_REG_VMEM 33 829#define TWL6030_REG_V2V1 34 830#define TWL6030_REG_V1V29 35 831#define TWL6030_REG_V1V8 36 832 833/* EXTERNAL LDOs */ 834#define TWL6030_REG_VAUX1_6030 37 835#define TWL6030_REG_VAUX2_6030 38 836#define TWL6030_REG_VAUX3_6030 39 837#define TWL6030_REG_VMMC 40 838#define TWL6030_REG_VPP 41 839#define TWL6030_REG_VUSIM 42 840#define TWL6030_REG_VANA 43 841#define TWL6030_REG_VCXIO 44 842#define TWL6030_REG_VDAC 45 843#define TWL6030_REG_VUSB 46 844 845/* INTERNAL LDOs */ 846#define TWL6030_REG_VRTC 47 847#define TWL6030_REG_CLK32KG 48 848 849/* LDOs on 6025 have different names */ 850#define TWL6032_REG_LDO2 49 851#define TWL6032_REG_LDO4 50 852#define TWL6032_REG_LDO3 51 853#define TWL6032_REG_LDO5 52 854#define TWL6032_REG_LDO1 53 855#define TWL6032_REG_LDO7 54 856#define TWL6032_REG_LDO6 55 857#define TWL6032_REG_LDOLN 56 858#define TWL6032_REG_LDOUSB 57 859 860/* 6025 DCDC supplies */ 861#define TWL6032_REG_SMPS3 58 862#define TWL6032_REG_SMPS4 59 863#define TWL6032_REG_VIO 60 864 865 866#endif /* End of __TWL4030_H */ 867