18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * This header provides constants for binding nvidia,tegra194-gpio*. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 88c2ecf20Sopenharmony_ci * provide names for this. 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * The second cell contains standard flag values specified in gpio.h. 118c2ecf20Sopenharmony_ci */ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 148c2ecf20Sopenharmony_ci#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#include <dt-bindings/gpio/gpio.h> 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* GPIOs implemented by main GPIO controller */ 198c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_A 0 208c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_B 1 218c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_C 2 228c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_D 3 238c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_E 4 248c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_F 5 258c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_G 6 268c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_H 7 278c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_I 8 288c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_J 9 298c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_K 10 308c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_L 11 318c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_M 12 328c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_N 13 338c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_O 14 348c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_P 15 358c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_Q 16 368c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_R 17 378c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_S 18 388c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_T 19 398c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_U 20 408c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_V 21 418c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_W 22 428c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_X 23 438c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_Y 24 448c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_Z 25 458c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_FF 26 468c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO_PORT_GG 27 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define TEGRA194_MAIN_GPIO(port, offset) \ 498c2ecf20Sopenharmony_ci ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci/* GPIOs implemented by AON GPIO controller */ 528c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO_PORT_AA 0 538c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO_PORT_BB 1 548c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO_PORT_CC 2 558c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO_PORT_DD 3 568c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO_PORT_EE 4 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci#define TEGRA194_AON_GPIO(port, offset) \ 598c2ecf20Sopenharmony_ci ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#endif 62