18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
98c2ecf20Sopenharmony_ci#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci/*
128c2ecf20Sopenharmony_ci * Let each exported clock get a unique index, which is used on DT-enabled
138c2ecf20Sopenharmony_ci * platforms to lookup the clock from a clock specifier. These indices are
148c2ecf20Sopenharmony_ci * therefore considered an ABI and so must not be changed. This implies
158c2ecf20Sopenharmony_ci * that new clocks should be added either in free spaces between clock groups
168c2ecf20Sopenharmony_ci * or at the end.
178c2ecf20Sopenharmony_ci */
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci/* Core clocks. */
208c2ecf20Sopenharmony_ci#define MSYSCLK			1
218c2ecf20Sopenharmony_ci#define ESYSCLK			2
228c2ecf20Sopenharmony_ci#define ARMDIV			3
238c2ecf20Sopenharmony_ci#define ARMCLK			4
248c2ecf20Sopenharmony_ci#define HCLK			5
258c2ecf20Sopenharmony_ci#define PCLK			6
268c2ecf20Sopenharmony_ci#define MPLL			7
278c2ecf20Sopenharmony_ci#define EPLL			8
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci/* Special clocks */
308c2ecf20Sopenharmony_ci#define SCLK_HSSPI0		16
318c2ecf20Sopenharmony_ci#define SCLK_FIMD		17
328c2ecf20Sopenharmony_ci#define SCLK_I2S0		18
338c2ecf20Sopenharmony_ci#define SCLK_I2S1		19
348c2ecf20Sopenharmony_ci#define SCLK_HSMMC1		20
358c2ecf20Sopenharmony_ci#define SCLK_HSMMC_EXT		21
368c2ecf20Sopenharmony_ci#define SCLK_CAM		22
378c2ecf20Sopenharmony_ci#define SCLK_UART		23
388c2ecf20Sopenharmony_ci#define SCLK_USBH		24
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci/* Muxes */
418c2ecf20Sopenharmony_ci#define MUX_HSSPI0		32
428c2ecf20Sopenharmony_ci#define MUX_HSSPI1		33
438c2ecf20Sopenharmony_ci#define MUX_HSMMC0		34
448c2ecf20Sopenharmony_ci#define MUX_HSMMC1		35
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci/* hclk-gates */
478c2ecf20Sopenharmony_ci#define HCLK_DMA0		48
488c2ecf20Sopenharmony_ci#define HCLK_DMA1		49
498c2ecf20Sopenharmony_ci#define HCLK_DMA2		50
508c2ecf20Sopenharmony_ci#define HCLK_DMA3		51
518c2ecf20Sopenharmony_ci#define HCLK_DMA4		52
528c2ecf20Sopenharmony_ci#define HCLK_DMA5		53
538c2ecf20Sopenharmony_ci#define HCLK_DMA6		54
548c2ecf20Sopenharmony_ci#define HCLK_DMA7		55
558c2ecf20Sopenharmony_ci#define HCLK_CAM		56
568c2ecf20Sopenharmony_ci#define HCLK_LCD		57
578c2ecf20Sopenharmony_ci#define HCLK_USBH		58
588c2ecf20Sopenharmony_ci#define HCLK_USBD		59
598c2ecf20Sopenharmony_ci#define HCLK_IROM		60
608c2ecf20Sopenharmony_ci#define HCLK_HSMMC0		61
618c2ecf20Sopenharmony_ci#define HCLK_HSMMC1		62
628c2ecf20Sopenharmony_ci#define HCLK_CFC		63
638c2ecf20Sopenharmony_ci#define HCLK_SSMC		64
648c2ecf20Sopenharmony_ci#define HCLK_DRAM		65
658c2ecf20Sopenharmony_ci#define HCLK_2D			66
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_ci/* pclk-gates */
688c2ecf20Sopenharmony_ci#define PCLK_UART0		72
698c2ecf20Sopenharmony_ci#define PCLK_UART1		73
708c2ecf20Sopenharmony_ci#define PCLK_UART2		74
718c2ecf20Sopenharmony_ci#define PCLK_UART3		75
728c2ecf20Sopenharmony_ci#define PCLK_I2C0		76
738c2ecf20Sopenharmony_ci#define PCLK_SDI		77
748c2ecf20Sopenharmony_ci#define PCLK_SPI0		78
758c2ecf20Sopenharmony_ci#define PCLK_ADC		79
768c2ecf20Sopenharmony_ci#define PCLK_AC97		80
778c2ecf20Sopenharmony_ci#define PCLK_I2S0		81
788c2ecf20Sopenharmony_ci#define PCLK_PWM		82
798c2ecf20Sopenharmony_ci#define PCLK_WDT		83
808c2ecf20Sopenharmony_ci#define PCLK_RTC		84
818c2ecf20Sopenharmony_ci#define PCLK_GPIO		85
828c2ecf20Sopenharmony_ci#define PCLK_SPI1		86
838c2ecf20Sopenharmony_ci#define PCLK_CHIPID		87
848c2ecf20Sopenharmony_ci#define PCLK_I2C1		88
858c2ecf20Sopenharmony_ci#define PCLK_I2S1		89
868c2ecf20Sopenharmony_ci#define PCLK_PCM		90
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci/* Total number of clocks. */
898c2ecf20Sopenharmony_ci#define NR_CLKS			(PCLK_PCM + 1)
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_ci#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
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