1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2017-2018 NXP 4 */ 5 6#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H 7#define __DT_BINDINGS_CLOCK_IMX8MM_H 8 9#define IMX8MM_CLK_DUMMY 0 10#define IMX8MM_CLK_32K 1 11#define IMX8MM_CLK_24M 2 12#define IMX8MM_OSC_HDMI_CLK 3 13#define IMX8MM_CLK_EXT1 4 14#define IMX8MM_CLK_EXT2 5 15#define IMX8MM_CLK_EXT3 6 16#define IMX8MM_CLK_EXT4 7 17#define IMX8MM_AUDIO_PLL1_REF_SEL 8 18#define IMX8MM_AUDIO_PLL2_REF_SEL 9 19#define IMX8MM_VIDEO_PLL1_REF_SEL 10 20#define IMX8MM_DRAM_PLL_REF_SEL 11 21#define IMX8MM_GPU_PLL_REF_SEL 12 22#define IMX8MM_VPU_PLL_REF_SEL 13 23#define IMX8MM_ARM_PLL_REF_SEL 14 24#define IMX8MM_SYS_PLL1_REF_SEL 15 25#define IMX8MM_SYS_PLL2_REF_SEL 16 26#define IMX8MM_SYS_PLL3_REF_SEL 17 27#define IMX8MM_AUDIO_PLL1 18 28#define IMX8MM_AUDIO_PLL2 19 29#define IMX8MM_VIDEO_PLL1 20 30#define IMX8MM_DRAM_PLL 21 31#define IMX8MM_GPU_PLL 22 32#define IMX8MM_VPU_PLL 23 33#define IMX8MM_ARM_PLL 24 34#define IMX8MM_SYS_PLL1 25 35#define IMX8MM_SYS_PLL2 26 36#define IMX8MM_SYS_PLL3 27 37#define IMX8MM_AUDIO_PLL1_BYPASS 28 38#define IMX8MM_AUDIO_PLL2_BYPASS 29 39#define IMX8MM_VIDEO_PLL1_BYPASS 30 40#define IMX8MM_DRAM_PLL_BYPASS 31 41#define IMX8MM_GPU_PLL_BYPASS 32 42#define IMX8MM_VPU_PLL_BYPASS 33 43#define IMX8MM_ARM_PLL_BYPASS 34 44#define IMX8MM_SYS_PLL1_BYPASS 35 45#define IMX8MM_SYS_PLL2_BYPASS 36 46#define IMX8MM_SYS_PLL3_BYPASS 37 47#define IMX8MM_AUDIO_PLL1_OUT 38 48#define IMX8MM_AUDIO_PLL2_OUT 39 49#define IMX8MM_VIDEO_PLL1_OUT 40 50#define IMX8MM_DRAM_PLL_OUT 41 51#define IMX8MM_GPU_PLL_OUT 42 52#define IMX8MM_VPU_PLL_OUT 43 53#define IMX8MM_ARM_PLL_OUT 44 54#define IMX8MM_SYS_PLL1_OUT 45 55#define IMX8MM_SYS_PLL2_OUT 46 56#define IMX8MM_SYS_PLL3_OUT 47 57#define IMX8MM_SYS_PLL1_40M 48 58#define IMX8MM_SYS_PLL1_80M 49 59#define IMX8MM_SYS_PLL1_100M 50 60#define IMX8MM_SYS_PLL1_133M 51 61#define IMX8MM_SYS_PLL1_160M 52 62#define IMX8MM_SYS_PLL1_200M 53 63#define IMX8MM_SYS_PLL1_266M 54 64#define IMX8MM_SYS_PLL1_400M 55 65#define IMX8MM_SYS_PLL1_800M 56 66#define IMX8MM_SYS_PLL2_50M 57 67#define IMX8MM_SYS_PLL2_100M 58 68#define IMX8MM_SYS_PLL2_125M 59 69#define IMX8MM_SYS_PLL2_166M 60 70#define IMX8MM_SYS_PLL2_200M 61 71#define IMX8MM_SYS_PLL2_250M 62 72#define IMX8MM_SYS_PLL2_333M 63 73#define IMX8MM_SYS_PLL2_500M 64 74#define IMX8MM_SYS_PLL2_1000M 65 75 76/* core */ 77#define IMX8MM_CLK_A53_SRC 66 78#define IMX8MM_CLK_M4_SRC 67 79#define IMX8MM_CLK_VPU_SRC 68 80#define IMX8MM_CLK_GPU3D_SRC 69 81#define IMX8MM_CLK_GPU2D_SRC 70 82#define IMX8MM_CLK_A53_CG 71 83#define IMX8MM_CLK_M4_CG 72 84#define IMX8MM_CLK_VPU_CG 73 85#define IMX8MM_CLK_GPU3D_CG 74 86#define IMX8MM_CLK_GPU2D_CG 75 87#define IMX8MM_CLK_A53_DIV 76 88#define IMX8MM_CLK_M4_DIV 77 89#define IMX8MM_CLK_VPU_DIV 78 90#define IMX8MM_CLK_GPU3D_DIV 79 91#define IMX8MM_CLK_GPU2D_DIV 80 92 93/* bus */ 94#define IMX8MM_CLK_MAIN_AXI 81 95#define IMX8MM_CLK_ENET_AXI 82 96#define IMX8MM_CLK_NAND_USDHC_BUS 83 97#define IMX8MM_CLK_VPU_BUS 84 98#define IMX8MM_CLK_DISP_AXI 85 99#define IMX8MM_CLK_DISP_APB 86 100#define IMX8MM_CLK_DISP_RTRM 87 101#define IMX8MM_CLK_USB_BUS 88 102#define IMX8MM_CLK_GPU_AXI 89 103#define IMX8MM_CLK_GPU_AHB 90 104#define IMX8MM_CLK_NOC 91 105#define IMX8MM_CLK_NOC_APB 92 106 107#define IMX8MM_CLK_AHB 93 108#define IMX8MM_CLK_AUDIO_AHB 94 109#define IMX8MM_CLK_IPG_ROOT 95 110#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 111 112#define IMX8MM_CLK_DRAM_ALT 97 113#define IMX8MM_CLK_DRAM_APB 98 114#define IMX8MM_CLK_VPU_G1 99 115#define IMX8MM_CLK_VPU_G2 100 116#define IMX8MM_CLK_DISP_DTRC 101 117#define IMX8MM_CLK_DISP_DC8000 102 118#define IMX8MM_CLK_PCIE1_CTRL 103 119#define IMX8MM_CLK_PCIE1_PHY 104 120#define IMX8MM_CLK_PCIE1_AUX 105 121#define IMX8MM_CLK_DC_PIXEL 106 122#define IMX8MM_CLK_LCDIF_PIXEL 107 123#define IMX8MM_CLK_SAI1 108 124#define IMX8MM_CLK_SAI2 109 125#define IMX8MM_CLK_SAI3 110 126#define IMX8MM_CLK_SAI4 111 127#define IMX8MM_CLK_SAI5 112 128#define IMX8MM_CLK_SAI6 113 129#define IMX8MM_CLK_SPDIF1 114 130#define IMX8MM_CLK_SPDIF2 115 131#define IMX8MM_CLK_ENET_REF 116 132#define IMX8MM_CLK_ENET_TIMER 117 133#define IMX8MM_CLK_ENET_PHY_REF 118 134#define IMX8MM_CLK_NAND 119 135#define IMX8MM_CLK_QSPI 120 136#define IMX8MM_CLK_USDHC1 121 137#define IMX8MM_CLK_USDHC2 122 138#define IMX8MM_CLK_I2C1 123 139#define IMX8MM_CLK_I2C2 124 140#define IMX8MM_CLK_I2C3 125 141#define IMX8MM_CLK_I2C4 126 142#define IMX8MM_CLK_UART1 127 143#define IMX8MM_CLK_UART2 128 144#define IMX8MM_CLK_UART3 129 145#define IMX8MM_CLK_UART4 130 146#define IMX8MM_CLK_USB_CORE_REF 131 147#define IMX8MM_CLK_USB_PHY_REF 132 148#define IMX8MM_CLK_ECSPI1 133 149#define IMX8MM_CLK_ECSPI2 134 150#define IMX8MM_CLK_PWM1 135 151#define IMX8MM_CLK_PWM2 136 152#define IMX8MM_CLK_PWM3 137 153#define IMX8MM_CLK_PWM4 138 154#define IMX8MM_CLK_GPT1 139 155#define IMX8MM_CLK_WDOG 140 156#define IMX8MM_CLK_WRCLK 141 157#define IMX8MM_CLK_DSI_CORE 142 158#define IMX8MM_CLK_DSI_PHY_REF 143 159#define IMX8MM_CLK_DSI_DBI 144 160#define IMX8MM_CLK_USDHC3 145 161#define IMX8MM_CLK_CSI1_CORE 146 162#define IMX8MM_CLK_CSI1_PHY_REF 147 163#define IMX8MM_CLK_CSI1_ESC 148 164#define IMX8MM_CLK_CSI2_CORE 149 165#define IMX8MM_CLK_CSI2_PHY_REF 150 166#define IMX8MM_CLK_CSI2_ESC 151 167#define IMX8MM_CLK_PCIE2_CTRL 152 168#define IMX8MM_CLK_PCIE2_PHY 153 169#define IMX8MM_CLK_PCIE2_AUX 154 170#define IMX8MM_CLK_ECSPI3 155 171#define IMX8MM_CLK_PDM 156 172#define IMX8MM_CLK_VPU_H1 157 173#define IMX8MM_CLK_CLKO1 158 174 175#define IMX8MM_CLK_ECSPI1_ROOT 159 176#define IMX8MM_CLK_ECSPI2_ROOT 160 177#define IMX8MM_CLK_ECSPI3_ROOT 161 178#define IMX8MM_CLK_ENET1_ROOT 162 179#define IMX8MM_CLK_GPT1_ROOT 163 180#define IMX8MM_CLK_I2C1_ROOT 164 181#define IMX8MM_CLK_I2C2_ROOT 165 182#define IMX8MM_CLK_I2C3_ROOT 166 183#define IMX8MM_CLK_I2C4_ROOT 167 184#define IMX8MM_CLK_OCOTP_ROOT 168 185#define IMX8MM_CLK_PCIE1_ROOT 169 186#define IMX8MM_CLK_PWM1_ROOT 170 187#define IMX8MM_CLK_PWM2_ROOT 171 188#define IMX8MM_CLK_PWM3_ROOT 172 189#define IMX8MM_CLK_PWM4_ROOT 173 190#define IMX8MM_CLK_QSPI_ROOT 174 191#define IMX8MM_CLK_NAND_ROOT 175 192#define IMX8MM_CLK_SAI1_ROOT 176 193#define IMX8MM_CLK_SAI1_IPG 177 194#define IMX8MM_CLK_SAI2_ROOT 178 195#define IMX8MM_CLK_SAI2_IPG 179 196#define IMX8MM_CLK_SAI3_ROOT 180 197#define IMX8MM_CLK_SAI3_IPG 181 198#define IMX8MM_CLK_SAI4_ROOT 182 199#define IMX8MM_CLK_SAI4_IPG 183 200#define IMX8MM_CLK_SAI5_ROOT 184 201#define IMX8MM_CLK_SAI5_IPG 185 202#define IMX8MM_CLK_SAI6_ROOT 186 203#define IMX8MM_CLK_SAI6_IPG 187 204#define IMX8MM_CLK_UART1_ROOT 188 205#define IMX8MM_CLK_UART2_ROOT 189 206#define IMX8MM_CLK_UART3_ROOT 190 207#define IMX8MM_CLK_UART4_ROOT 191 208#define IMX8MM_CLK_USB1_CTRL_ROOT 192 209#define IMX8MM_CLK_GPU3D_ROOT 193 210#define IMX8MM_CLK_USDHC1_ROOT 194 211#define IMX8MM_CLK_USDHC2_ROOT 195 212#define IMX8MM_CLK_WDOG1_ROOT 196 213#define IMX8MM_CLK_WDOG2_ROOT 197 214#define IMX8MM_CLK_WDOG3_ROOT 198 215#define IMX8MM_CLK_VPU_G1_ROOT 199 216#define IMX8MM_CLK_GPU_BUS_ROOT 200 217#define IMX8MM_CLK_VPU_H1_ROOT 201 218#define IMX8MM_CLK_VPU_G2_ROOT 202 219#define IMX8MM_CLK_PDM_ROOT 203 220#define IMX8MM_CLK_DISP_ROOT 204 221#define IMX8MM_CLK_DISP_AXI_ROOT 205 222#define IMX8MM_CLK_DISP_APB_ROOT 206 223#define IMX8MM_CLK_DISP_RTRM_ROOT 207 224#define IMX8MM_CLK_USDHC3_ROOT 208 225#define IMX8MM_CLK_TMU_ROOT 209 226#define IMX8MM_CLK_VPU_DEC_ROOT 210 227#define IMX8MM_CLK_SDMA1_ROOT 211 228#define IMX8MM_CLK_SDMA2_ROOT 212 229#define IMX8MM_CLK_SDMA3_ROOT 213 230#define IMX8MM_CLK_GPT_3M 214 231#define IMX8MM_CLK_ARM 215 232#define IMX8MM_CLK_PDM_IPG 216 233#define IMX8MM_CLK_GPU2D_ROOT 217 234#define IMX8MM_CLK_MU_ROOT 218 235#define IMX8MM_CLK_CSI1_ROOT 219 236 237#define IMX8MM_CLK_DRAM_CORE 220 238#define IMX8MM_CLK_DRAM_ALT_ROOT 221 239 240#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 241 242#define IMX8MM_CLK_GPIO1_ROOT 223 243#define IMX8MM_CLK_GPIO2_ROOT 224 244#define IMX8MM_CLK_GPIO3_ROOT 225 245#define IMX8MM_CLK_GPIO4_ROOT 226 246#define IMX8MM_CLK_GPIO5_ROOT 227 247 248#define IMX8MM_CLK_SNVS_ROOT 228 249#define IMX8MM_CLK_GIC 229 250 251#define IMX8MM_SYS_PLL1_40M_CG 230 252#define IMX8MM_SYS_PLL1_80M_CG 231 253#define IMX8MM_SYS_PLL1_100M_CG 232 254#define IMX8MM_SYS_PLL1_133M_CG 233 255#define IMX8MM_SYS_PLL1_160M_CG 234 256#define IMX8MM_SYS_PLL1_200M_CG 235 257#define IMX8MM_SYS_PLL1_266M_CG 236 258#define IMX8MM_SYS_PLL1_400M_CG 237 259#define IMX8MM_SYS_PLL2_50M_CG 238 260#define IMX8MM_SYS_PLL2_100M_CG 239 261#define IMX8MM_SYS_PLL2_125M_CG 240 262#define IMX8MM_SYS_PLL2_166M_CG 241 263#define IMX8MM_SYS_PLL2_200M_CG 242 264#define IMX8MM_SYS_PLL2_250M_CG 243 265#define IMX8MM_SYS_PLL2_333M_CG 244 266#define IMX8MM_SYS_PLL2_500M_CG 245 267 268#define IMX8MM_CLK_M4_CORE 246 269#define IMX8MM_CLK_VPU_CORE 247 270#define IMX8MM_CLK_GPU3D_CORE 248 271#define IMX8MM_CLK_GPU2D_CORE 249 272 273#define IMX8MM_CLK_CLKO2 250 274 275#define IMX8MM_CLK_A53_CORE 251 276 277#define IMX8MM_CLK_END 252 278 279#endif 280