1/* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef __DRM_EDID_H__ 24#define __DRM_EDID_H__ 25 26#include <linux/types.h> 27#include <linux/hdmi.h> 28#include <drm/drm_mode.h> 29 30struct drm_device; 31struct i2c_adapter; 32 33#define EDID_LENGTH 128 34#define DDC_ADDR 0x50 35#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 36 37#define CEA_EXT 0x02 38#define VTB_EXT 0x10 39#define DI_EXT 0x40 40#define LS_EXT 0x50 41#define MI_EXT 0x60 42#define DISPLAYID_EXT 0x70 43 44struct est_timings { 45 u8 t1; 46 u8 t2; 47 u8 mfg_rsvd; 48} __attribute__((packed)); 49 50/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 51#define EDID_TIMING_ASPECT_SHIFT 6 52#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 53 54/* need to add 60 */ 55#define EDID_TIMING_VFREQ_SHIFT 0 56#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 57 58struct std_timing { 59 u8 hsize; /* need to multiply by 8 then add 248 */ 60 u8 vfreq_aspect; 61} __attribute__((packed)); 62 63#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 64#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 65#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 66#define DRM_EDID_PT_STEREO (1 << 5) 67#define DRM_EDID_PT_INTERLACED (1 << 7) 68 69/* If detailed data is pixel timing */ 70struct detailed_pixel_timing { 71 u8 hactive_lo; 72 u8 hblank_lo; 73 u8 hactive_hblank_hi; 74 u8 vactive_lo; 75 u8 vblank_lo; 76 u8 vactive_vblank_hi; 77 u8 hsync_offset_lo; 78 u8 hsync_pulse_width_lo; 79 u8 vsync_offset_pulse_width_lo; 80 u8 hsync_vsync_offset_pulse_width_hi; 81 u8 width_mm_lo; 82 u8 height_mm_lo; 83 u8 width_height_mm_hi; 84 u8 hborder; 85 u8 vborder; 86 u8 misc; 87} __attribute__((packed)); 88 89/* If it's not pixel timing, it'll be one of the below */ 90struct detailed_data_string { 91 u8 str[13]; 92} __attribute__((packed)); 93 94#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 95#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 96#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 97#define DRM_EDID_CVT_SUPPORT_FLAG 0x04 98 99struct detailed_data_monitor_range { 100 u8 min_vfreq; 101 u8 max_vfreq; 102 u8 min_hfreq_khz; 103 u8 max_hfreq_khz; 104 u8 pixel_clock_mhz; /* need to multiply by 10 */ 105 u8 flags; 106 union { 107 struct { 108 u8 reserved; 109 u8 hfreq_start_khz; /* need to multiply by 2 */ 110 u8 c; /* need to divide by 2 */ 111 __le16 m; 112 u8 k; 113 u8 j; /* need to divide by 2 */ 114 } __attribute__((packed)) gtf2; 115 struct { 116 u8 version; 117 u8 data1; /* high 6 bits: extra clock resolution */ 118 u8 data2; /* plus low 2 of above: max hactive */ 119 u8 supported_aspects; 120 u8 flags; /* preferred aspect and blanking support */ 121 u8 supported_scalings; 122 u8 preferred_refresh; 123 } __attribute__((packed)) cvt; 124 } __attribute__((packed)) formula; 125} __attribute__((packed)); 126 127struct detailed_data_wpindex { 128 u8 white_yx_lo; /* Lower 2 bits each */ 129 u8 white_x_hi; 130 u8 white_y_hi; 131 u8 gamma; /* need to divide by 100 then add 1 */ 132} __attribute__((packed)); 133 134struct detailed_data_color_point { 135 u8 windex1; 136 u8 wpindex1[3]; 137 u8 windex2; 138 u8 wpindex2[3]; 139} __attribute__((packed)); 140 141struct cvt_timing { 142 u8 code[3]; 143} __attribute__((packed)); 144 145struct detailed_non_pixel { 146 u8 pad1; 147 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 148 fb=color point data, fa=standard timing data, 149 f9=undefined, f8=mfg. reserved */ 150 u8 pad2; 151 union { 152 struct detailed_data_string str; 153 struct detailed_data_monitor_range range; 154 struct detailed_data_wpindex color; 155 struct std_timing timings[6]; 156 struct cvt_timing cvt[4]; 157 } __attribute__((packed)) data; 158} __attribute__((packed)); 159 160#define EDID_DETAIL_EST_TIMINGS 0xf7 161#define EDID_DETAIL_CVT_3BYTE 0xf8 162#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 163#define EDID_DETAIL_STD_MODES 0xfa 164#define EDID_DETAIL_MONITOR_CPDATA 0xfb 165#define EDID_DETAIL_MONITOR_NAME 0xfc 166#define EDID_DETAIL_MONITOR_RANGE 0xfd 167#define EDID_DETAIL_MONITOR_STRING 0xfe 168#define EDID_DETAIL_MONITOR_SERIAL 0xff 169 170struct detailed_timing { 171 __le16 pixel_clock; /* need to multiply by 10 KHz */ 172 union { 173 struct detailed_pixel_timing pixel_data; 174 struct detailed_non_pixel other_data; 175 } __attribute__((packed)) data; 176} __attribute__((packed)); 177 178#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 179#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 180#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 181#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 182#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 183#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 184#define DRM_EDID_INPUT_DIGITAL (1 << 7) 185#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 186#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 187#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 188#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 189#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 190#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 191#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 192#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 193#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 194#define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 195#define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 196#define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 197#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 198#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 199#define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 200#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 201#define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 202 203#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 204#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 205#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 206/* If analog */ 207#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 208/* If digital */ 209#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 210#define DRM_EDID_FEATURE_RGB (0 << 3) 211#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 212#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 213#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 214 215#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 216#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 217#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 218 219#define DRM_EDID_HDMI_DC_48 (1 << 6) 220#define DRM_EDID_HDMI_DC_36 (1 << 5) 221#define DRM_EDID_HDMI_DC_30 (1 << 4) 222#define DRM_EDID_HDMI_DC_Y444 (1 << 3) 223 224/* YCBCR 420 deep color modes */ 225#define DRM_EDID_YCBCR420_DC_48 (1 << 2) 226#define DRM_EDID_YCBCR420_DC_36 (1 << 1) 227#define DRM_EDID_YCBCR420_DC_30 (1 << 0) 228#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 229 DRM_EDID_YCBCR420_DC_36 | \ 230 DRM_EDID_YCBCR420_DC_30) 231 232/* ELD Header Block */ 233#define DRM_ELD_HEADER_BLOCK_SIZE 4 234 235#define DRM_ELD_VER 0 236# define DRM_ELD_VER_SHIFT 3 237# define DRM_ELD_VER_MASK (0x1f << 3) 238# define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 239# define DRM_ELD_VER_CANNED (0x1f << 3) 240 241#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 242 243/* ELD Baseline Block for ELD_Ver == 2 */ 244#define DRM_ELD_CEA_EDID_VER_MNL 4 245# define DRM_ELD_CEA_EDID_VER_SHIFT 5 246# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 247# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 248# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 249# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 250# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 251# define DRM_ELD_MNL_SHIFT 0 252# define DRM_ELD_MNL_MASK (0x1f << 0) 253 254#define DRM_ELD_SAD_COUNT_CONN_TYPE 5 255# define DRM_ELD_SAD_COUNT_SHIFT 4 256# define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 257# define DRM_ELD_CONN_TYPE_SHIFT 2 258# define DRM_ELD_CONN_TYPE_MASK (3 << 2) 259# define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 260# define DRM_ELD_CONN_TYPE_DP (1 << 2) 261# define DRM_ELD_SUPPORTS_AI (1 << 1) 262# define DRM_ELD_SUPPORTS_HDCP (1 << 0) 263 264#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 265# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 266 267#define DRM_ELD_SPEAKER 7 268# define DRM_ELD_SPEAKER_MASK 0x7f 269# define DRM_ELD_SPEAKER_RLRC (1 << 6) 270# define DRM_ELD_SPEAKER_FLRC (1 << 5) 271# define DRM_ELD_SPEAKER_RC (1 << 4) 272# define DRM_ELD_SPEAKER_RLR (1 << 3) 273# define DRM_ELD_SPEAKER_FC (1 << 2) 274# define DRM_ELD_SPEAKER_LFE (1 << 1) 275# define DRM_ELD_SPEAKER_FLR (1 << 0) 276 277#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 278# define DRM_ELD_PORT_ID_LEN 8 279 280#define DRM_ELD_MANUFACTURER_NAME0 16 281#define DRM_ELD_MANUFACTURER_NAME1 17 282 283#define DRM_ELD_PRODUCT_CODE0 18 284#define DRM_ELD_PRODUCT_CODE1 19 285 286#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 287 288#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 289 290struct edid { 291 u8 header[8]; 292 /* Vendor & product info */ 293 u8 mfg_id[2]; 294 u8 prod_code[2]; 295 u32 serial; /* FIXME: byte order */ 296 u8 mfg_week; 297 u8 mfg_year; 298 /* EDID version */ 299 u8 version; 300 u8 revision; 301 /* Display info: */ 302 u8 input; 303 u8 width_cm; 304 u8 height_cm; 305 u8 gamma; 306 u8 features; 307 /* Color characteristics */ 308 u8 red_green_lo; 309 u8 black_white_lo; 310 u8 red_x; 311 u8 red_y; 312 u8 green_x; 313 u8 green_y; 314 u8 blue_x; 315 u8 blue_y; 316 u8 white_x; 317 u8 white_y; 318 /* Est. timings and mfg rsvd timings*/ 319 struct est_timings established_timings; 320 /* Standard timings 1-8*/ 321 struct std_timing standard_timings[8]; 322 /* Detailing timings 1-4 */ 323 struct detailed_timing detailed_timings[4]; 324 /* Number of 128 byte ext. blocks */ 325 u8 extensions; 326 /* Checksum */ 327 u8 checksum; 328} __attribute__((packed)); 329 330#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 331 332/* Short Audio Descriptor */ 333struct cea_sad { 334 u8 format; 335 u8 channels; /* max number of channels - 1 */ 336 u8 freq; 337 u8 byte2; /* meaning depends on format */ 338}; 339 340struct drm_encoder; 341struct drm_connector; 342struct drm_connector_state; 343struct drm_display_mode; 344 345int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); 346int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); 347int drm_av_sync_delay(struct drm_connector *connector, 348 const struct drm_display_mode *mode); 349 350#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 351struct edid *drm_load_edid_firmware(struct drm_connector *connector); 352int __drm_set_edid_firmware_path(const char *path); 353int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 354#else 355static inline struct edid * 356drm_load_edid_firmware(struct drm_connector *connector) 357{ 358 return ERR_PTR(-ENOENT); 359} 360#endif 361 362bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); 363 364int 365drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 366 const struct drm_connector *connector, 367 const struct drm_display_mode *mode); 368int 369drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 370 const struct drm_connector *connector, 371 const struct drm_display_mode *mode); 372 373void 374drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 375 const struct drm_connector_state *conn_state); 376 377void 378drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 379 const struct drm_connector_state *conn_state); 380 381void 382drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 383 const struct drm_connector *connector, 384 const struct drm_display_mode *mode, 385 enum hdmi_quantization_range rgb_quant_range); 386 387int 388drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 389 const struct drm_connector_state *conn_state); 390 391/** 392 * drm_eld_mnl - Get ELD monitor name length in bytes. 393 * @eld: pointer to an eld memory structure with mnl set 394 */ 395static inline int drm_eld_mnl(const uint8_t *eld) 396{ 397 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 398} 399 400/** 401 * drm_eld_sad - Get ELD SAD structures. 402 * @eld: pointer to an eld memory structure with sad_count set 403 */ 404static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 405{ 406 unsigned int ver, mnl; 407 408 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 409 if (ver != 2 && ver != 31) 410 return NULL; 411 412 mnl = drm_eld_mnl(eld); 413 if (mnl > 16) 414 return NULL; 415 416 return eld + DRM_ELD_CEA_SAD(mnl, 0); 417} 418 419/** 420 * drm_eld_sad_count - Get ELD SAD count. 421 * @eld: pointer to an eld memory structure with sad_count set 422 */ 423static inline int drm_eld_sad_count(const uint8_t *eld) 424{ 425 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 426 DRM_ELD_SAD_COUNT_SHIFT; 427} 428 429/** 430 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 431 * @eld: pointer to an eld memory structure with mnl and sad_count set 432 * 433 * This is a helper for determining the payload size of the baseline block, in 434 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 435 */ 436static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 437{ 438 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 439 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 440} 441 442/** 443 * drm_eld_size - Get ELD size in bytes 444 * @eld: pointer to a complete eld memory structure 445 * 446 * The returned value does not include the vendor block. It's vendor specific, 447 * and comprises of the remaining bytes in the ELD memory buffer after 448 * drm_eld_size() bytes of header and baseline block. 449 * 450 * The returned value is guaranteed to be a multiple of 4. 451 */ 452static inline int drm_eld_size(const uint8_t *eld) 453{ 454 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 455} 456 457/** 458 * drm_eld_get_spk_alloc - Get speaker allocation 459 * @eld: pointer to an ELD memory structure 460 * 461 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 462 * field definitions to identify speakers. 463 */ 464static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 465{ 466 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 467} 468 469/** 470 * drm_eld_get_conn_type - Get device type hdmi/dp connected 471 * @eld: pointer to an ELD memory structure 472 * 473 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 474 * identify the display type connected. 475 */ 476static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 477{ 478 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 479} 480 481bool drm_probe_ddc(struct i2c_adapter *adapter); 482struct edid *drm_do_get_edid(struct drm_connector *connector, 483 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 484 size_t len), 485 void *data); 486struct edid *drm_get_edid(struct drm_connector *connector, 487 struct i2c_adapter *adapter); 488struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 489 struct i2c_adapter *adapter); 490struct edid *drm_edid_duplicate(const struct edid *edid); 491int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 492int drm_add_override_edid_modes(struct drm_connector *connector); 493 494u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 495bool drm_detect_hdmi_monitor(struct edid *edid); 496bool drm_detect_monitor_audio(struct edid *edid); 497enum hdmi_quantization_range 498drm_default_rgb_quant_range(const struct drm_display_mode *mode); 499int drm_add_modes_noedid(struct drm_connector *connector, 500 int hdisplay, int vdisplay); 501void drm_set_preferred_mode(struct drm_connector *connector, 502 int hpref, int vpref); 503 504int drm_edid_header_is_valid(const u8 *raw_edid); 505bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 506 bool *edid_corrupt); 507bool drm_edid_is_valid(struct edid *edid); 508void drm_edid_get_monitor_name(struct edid *edid, char *name, 509 int buflen); 510struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 511 int hsize, int vsize, int fresh, 512 bool rb); 513struct drm_display_mode * 514drm_display_mode_from_cea_vic(struct drm_device *dev, 515 u8 video_code); 516 517#endif /* __DRM_EDID_H__ */ 518