1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *	sp5100_tco :	TCO timer driver for sp5100 chipsets
4 *
5 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
6 *
7 *	Based on i8xx_tco.c:
8 *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
9 *	Reserved.
10 *				https://www.kernelconcepts.de
11 *
12 *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
13 *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
14 *	                                                      Reference Guide"
15 *	    AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
16 *				for AMD Family 16h Models 00h-0Fh Processors"
17 *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
18 *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
19 *				for AMD Family 16h Models 30h-3Fh Processors"
20 *	    AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
21 *				for AMD Family 17h Model 18h, Revision B1
22 *				Processors (PUB)
23 *	    AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
24 *				for AMD Family 17h Model 20h, Revision A1
25 *				Processors (PUB)
26 */
27
28/*
29 *	Includes, defines, variables, module parameters, ...
30 */
31
32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34#include <linux/init.h>
35#include <linux/io.h>
36#include <linux/ioport.h>
37#include <linux/module.h>
38#include <linux/moduleparam.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/types.h>
42#include <linux/watchdog.h>
43
44#include "sp5100_tco.h"
45
46#define TCO_DRIVER_NAME	"sp5100-tco"
47
48/* internal variables */
49
50enum tco_reg_layout {
51	sp5100, sb800, efch
52};
53
54struct sp5100_tco {
55	struct watchdog_device wdd;
56	void __iomem *tcobase;
57	enum tco_reg_layout tco_reg_layout;
58};
59
60/* the watchdog platform device */
61static struct platform_device *sp5100_tco_platform_device;
62/* the associated PCI device */
63static struct pci_dev *sp5100_tco_pci;
64
65/* module parameters */
66
67#define WATCHDOG_HEARTBEAT 60	/* 60 sec default heartbeat. */
68static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
69module_param(heartbeat, int, 0);
70MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
71		 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
72
73static bool nowayout = WATCHDOG_NOWAYOUT;
74module_param(nowayout, bool, 0);
75MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
76		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
77
78/*
79 * Some TCO specific functions
80 */
81
82static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
83{
84	if (dev->vendor == PCI_VENDOR_ID_ATI &&
85	    dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
86	    dev->revision < 0x40) {
87		return sp5100;
88	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
89	    ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
90	     dev->revision >= 0x41) ||
91	    (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
92	     dev->revision >= 0x49))) {
93		return efch;
94	}
95	return sb800;
96}
97
98static int tco_timer_start(struct watchdog_device *wdd)
99{
100	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
101	u32 val;
102
103	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
104	val |= SP5100_WDT_START_STOP_BIT;
105	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
106
107	/* This must be a distinct write. */
108	val |= SP5100_WDT_TRIGGER_BIT;
109	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
110
111	return 0;
112}
113
114static int tco_timer_stop(struct watchdog_device *wdd)
115{
116	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
117	u32 val;
118
119	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
120	val &= ~SP5100_WDT_START_STOP_BIT;
121	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
122
123	return 0;
124}
125
126static int tco_timer_ping(struct watchdog_device *wdd)
127{
128	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
129	u32 val;
130
131	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
132	val |= SP5100_WDT_TRIGGER_BIT;
133	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
134
135	return 0;
136}
137
138static int tco_timer_set_timeout(struct watchdog_device *wdd,
139				 unsigned int t)
140{
141	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
142
143	/* Write new heartbeat to watchdog */
144	writel(t, SP5100_WDT_COUNT(tco->tcobase));
145
146	wdd->timeout = t;
147
148	return 0;
149}
150
151static u8 sp5100_tco_read_pm_reg8(u8 index)
152{
153	outb(index, SP5100_IO_PM_INDEX_REG);
154	return inb(SP5100_IO_PM_DATA_REG);
155}
156
157static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
158{
159	u8 val;
160
161	outb(index, SP5100_IO_PM_INDEX_REG);
162	val = inb(SP5100_IO_PM_DATA_REG);
163	val &= reset;
164	val |= set;
165	outb(val, SP5100_IO_PM_DATA_REG);
166}
167
168static void tco_timer_enable(struct sp5100_tco *tco)
169{
170	u32 val;
171
172	switch (tco->tco_reg_layout) {
173	case sb800:
174		/* For SB800 or later */
175		/* Set the Watchdog timer resolution to 1 sec */
176		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
177					  0xff, SB800_PM_WATCHDOG_SECOND_RES);
178
179		/* Enable watchdog decode bit and watchdog timer */
180		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
181					  ~SB800_PM_WATCHDOG_DISABLE,
182					  SB800_PCI_WATCHDOG_DECODE_EN);
183		break;
184	case sp5100:
185		/* For SP5100 or SB7x0 */
186		/* Enable watchdog decode bit */
187		pci_read_config_dword(sp5100_tco_pci,
188				      SP5100_PCI_WATCHDOG_MISC_REG,
189				      &val);
190
191		val |= SP5100_PCI_WATCHDOG_DECODE_EN;
192
193		pci_write_config_dword(sp5100_tco_pci,
194				       SP5100_PCI_WATCHDOG_MISC_REG,
195				       val);
196
197		/* Enable Watchdog timer and set the resolution to 1 sec */
198		sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
199					  ~SP5100_PM_WATCHDOG_DISABLE,
200					  SP5100_PM_WATCHDOG_SECOND_RES);
201		break;
202	case efch:
203		/* Set the Watchdog timer resolution to 1 sec and enable */
204		sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
205					  ~EFCH_PM_WATCHDOG_DISABLE,
206					  EFCH_PM_DECODEEN_SECOND_RES);
207		break;
208	}
209}
210
211static u32 sp5100_tco_read_pm_reg32(u8 index)
212{
213	u32 val = 0;
214	int i;
215
216	for (i = 3; i >= 0; i--)
217		val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
218
219	return val;
220}
221
222static int sp5100_tco_setupdevice(struct device *dev,
223				  struct watchdog_device *wdd)
224{
225	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
226	const char *dev_name;
227	u32 mmio_addr = 0, val;
228	int ret;
229
230	/* Request the IO ports used by this driver */
231	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
232				  SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
233		dev_err(dev, "I/O address 0x%04x already in use\n",
234			SP5100_IO_PM_INDEX_REG);
235		return -EBUSY;
236	}
237
238	/*
239	 * Determine type of southbridge chipset.
240	 */
241	switch (tco->tco_reg_layout) {
242	case sp5100:
243		dev_name = SP5100_DEVNAME;
244		mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
245								0xfffffff8;
246		break;
247	case sb800:
248		dev_name = SB800_DEVNAME;
249		mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
250								0xfffffff8;
251		break;
252	case efch:
253		dev_name = SB800_DEVNAME;
254		/*
255		 * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
256		 * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
257		 * region, it also enables the watchdog itself.
258		 */
259		if (boot_cpu_data.x86 == 0x17) {
260			val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
261			if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
262				sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
263							  EFCH_PM_DECODEEN_WDT_TMREN);
264			}
265		}
266		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
267		if (val & EFCH_PM_DECODEEN_WDT_TMREN)
268			mmio_addr = EFCH_PM_WDT_ADDR;
269		break;
270	default:
271		return -ENODEV;
272	}
273
274	/* Check MMIO address conflict */
275	if (!mmio_addr ||
276	    !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
277				     dev_name)) {
278		if (mmio_addr)
279			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
280				mmio_addr);
281		switch (tco->tco_reg_layout) {
282		case sp5100:
283			/*
284			 * Secondly, Find the watchdog timer MMIO address
285			 * from SBResource_MMIO register.
286			 */
287			/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
288			pci_read_config_dword(sp5100_tco_pci,
289					      SP5100_SB_RESOURCE_MMIO_BASE,
290					      &mmio_addr);
291			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
292					  SB800_ACPI_MMIO_SEL)) !=
293						  SB800_ACPI_MMIO_DECODE_EN) {
294				ret = -ENODEV;
295				goto unreg_region;
296			}
297			mmio_addr &= ~0xFFF;
298			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
299			break;
300		case sb800:
301			/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
302			mmio_addr =
303				sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
304			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
305					  SB800_ACPI_MMIO_SEL)) !=
306						  SB800_ACPI_MMIO_DECODE_EN) {
307				ret = -ENODEV;
308				goto unreg_region;
309			}
310			mmio_addr &= ~0xFFF;
311			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
312			break;
313		case efch:
314			val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
315			if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
316				ret = -ENODEV;
317				goto unreg_region;
318			}
319			mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
320				    EFCH_PM_ACPI_MMIO_WDT_OFFSET;
321			break;
322		}
323		dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
324			mmio_addr);
325		if (!devm_request_mem_region(dev, mmio_addr,
326					     SP5100_WDT_MEM_MAP_SIZE,
327					     dev_name)) {
328			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
329				mmio_addr);
330			ret = -EBUSY;
331			goto unreg_region;
332		}
333	}
334
335	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
336	if (!tco->tcobase) {
337		dev_err(dev, "failed to get tcobase address\n");
338		ret = -ENOMEM;
339		goto unreg_region;
340	}
341
342	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
343
344	/* Setup the watchdog timer */
345	tco_timer_enable(tco);
346
347	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
348	if (val & SP5100_WDT_DISABLED) {
349		dev_err(dev, "Watchdog hardware is disabled\n");
350		ret = -ENODEV;
351		goto unreg_region;
352	}
353
354	/*
355	 * Save WatchDogFired status, because WatchDogFired flag is
356	 * cleared here.
357	 */
358	if (val & SP5100_WDT_FIRED)
359		wdd->bootstatus = WDIOF_CARDRESET;
360	/* Set watchdog action to reset the system */
361	val &= ~SP5100_WDT_ACTION_RESET;
362	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
363
364	/* Set a reasonable heartbeat before we stop the timer */
365	tco_timer_set_timeout(wdd, wdd->timeout);
366
367	/*
368	 * Stop the TCO before we change anything so we don't race with
369	 * a zeroed timer.
370	 */
371	tco_timer_stop(wdd);
372
373	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
374
375	return 0;
376
377unreg_region:
378	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
379	return ret;
380}
381
382static struct watchdog_info sp5100_tco_wdt_info = {
383	.identity = "SP5100 TCO timer",
384	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
385};
386
387static const struct watchdog_ops sp5100_tco_wdt_ops = {
388	.owner = THIS_MODULE,
389	.start = tco_timer_start,
390	.stop = tco_timer_stop,
391	.ping = tco_timer_ping,
392	.set_timeout = tco_timer_set_timeout,
393};
394
395static int sp5100_tco_probe(struct platform_device *pdev)
396{
397	struct device *dev = &pdev->dev;
398	struct watchdog_device *wdd;
399	struct sp5100_tco *tco;
400	int ret;
401
402	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
403	if (!tco)
404		return -ENOMEM;
405
406	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
407
408	wdd = &tco->wdd;
409	wdd->parent = dev;
410	wdd->info = &sp5100_tco_wdt_info;
411	wdd->ops = &sp5100_tco_wdt_ops;
412	wdd->timeout = WATCHDOG_HEARTBEAT;
413	wdd->min_timeout = 1;
414	wdd->max_timeout = 0xffff;
415
416	watchdog_init_timeout(wdd, heartbeat, NULL);
417	watchdog_set_nowayout(wdd, nowayout);
418	watchdog_stop_on_reboot(wdd);
419	watchdog_stop_on_unregister(wdd);
420	watchdog_set_drvdata(wdd, tco);
421
422	ret = sp5100_tco_setupdevice(dev, wdd);
423	if (ret)
424		return ret;
425
426	ret = devm_watchdog_register_device(dev, wdd);
427	if (ret)
428		return ret;
429
430	/* Show module parameters */
431	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
432		 wdd->timeout, nowayout);
433
434	return 0;
435}
436
437static struct platform_driver sp5100_tco_driver = {
438	.probe		= sp5100_tco_probe,
439	.driver		= {
440		.name	= TCO_DRIVER_NAME,
441	},
442};
443
444/*
445 * Data for PCI driver interface
446 *
447 * This data only exists for exporting the supported
448 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
449 * register a pci_driver, because someone else might
450 * want to register another driver on the same PCI id.
451 */
452static const struct pci_device_id sp5100_tco_pci_tbl[] = {
453	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
454	  PCI_ANY_ID, },
455	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
456	  PCI_ANY_ID, },
457	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
458	  PCI_ANY_ID, },
459	{ 0, },			/* End of list */
460};
461MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
462
463static int __init sp5100_tco_init(void)
464{
465	struct pci_dev *dev = NULL;
466	int err;
467
468	/* Match the PCI device */
469	for_each_pci_dev(dev) {
470		if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
471			sp5100_tco_pci = dev;
472			break;
473		}
474	}
475
476	if (!sp5100_tco_pci)
477		return -ENODEV;
478
479	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
480
481	err = platform_driver_register(&sp5100_tco_driver);
482	if (err)
483		return err;
484
485	sp5100_tco_platform_device =
486		platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
487	if (IS_ERR(sp5100_tco_platform_device)) {
488		err = PTR_ERR(sp5100_tco_platform_device);
489		goto unreg_platform_driver;
490	}
491
492	return 0;
493
494unreg_platform_driver:
495	platform_driver_unregister(&sp5100_tco_driver);
496	return err;
497}
498
499static void __exit sp5100_tco_exit(void)
500{
501	platform_device_unregister(sp5100_tco_platform_device);
502	platform_driver_unregister(&sp5100_tco_driver);
503}
504
505module_init(sp5100_tco_init);
506module_exit(sp5100_tco_exit);
507
508MODULE_AUTHOR("Priyanka Gupta");
509MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
510MODULE_LICENSE("GPL");
511