1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * SBSA(Server Base System Architecture) Generic Watchdog driver 4 * 5 * Copyright (c) 2015, Linaro Ltd. 6 * Author: Fu Wei <fu.wei@linaro.org> 7 * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> 8 * Al Stone <al.stone@linaro.org> 9 * Timur Tabi <timur@codeaurora.org> 10 * 11 * ARM SBSA Generic Watchdog has two stage timeouts: 12 * the first signal (WS0) is for alerting the system by interrupt, 13 * the second one (WS1) is a real hardware reset. 14 * More details about the hardware specification of this device: 15 * ARM DEN0029B - Server Base System Architecture (SBSA) 16 * 17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog 18 * or a two stages watchdog, it's set up by the module parameter "action". 19 * In the single stage mode, when the timeout is reached, your system 20 * will be reset by WS1. The first signal (WS0) is ignored. 21 * In the two stages mode, when the timeout is reached, the first signal (WS0) 22 * will trigger panic. If the system is getting into trouble and cannot be reset 23 * by panic or restart properly by the kdump kernel(if supported), then the 24 * second stage (as long as the first stage) will be reached, system will be 25 * reset by WS1. This function can help administrator to backup the system 26 * context info by panic console output or kdump. 27 * 28 * SBSA GWDT: 29 * if action is 1 (the two stages mode): 30 * |--------WOR-------WS0--------WOR-------WS1 31 * |----timeout-----(panic)----timeout-----reset 32 * 33 * if action is 0 (the single stage mode): 34 * |------WOR-----WS0(ignored)-----WOR------WS1 35 * |--------------timeout-------------------reset 36 * 37 * Note: Since this watchdog timer has two stages, and each stage is determined 38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two 39 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode 40 * is half of that in the single stage mode. 41 */ 42 43#include <linux/io.h> 44#include <linux/io-64-nonatomic-lo-hi.h> 45#include <linux/interrupt.h> 46#include <linux/module.h> 47#include <linux/moduleparam.h> 48#include <linux/of.h> 49#include <linux/of_device.h> 50#include <linux/platform_device.h> 51#include <linux/uaccess.h> 52#include <linux/watchdog.h> 53#include <asm/arch_timer.h> 54 55#define DRV_NAME "sbsa-gwdt" 56#define WATCHDOG_NAME "SBSA Generic Watchdog" 57 58/* SBSA Generic Watchdog register definitions */ 59/* refresh frame */ 60#define SBSA_GWDT_WRR 0x000 61 62/* control frame */ 63#define SBSA_GWDT_WCS 0x000 64#define SBSA_GWDT_WOR 0x008 65#define SBSA_GWDT_WCV 0x010 66 67/* refresh/control frame */ 68#define SBSA_GWDT_W_IIDR 0xfcc 69#define SBSA_GWDT_IDR 0xfd0 70 71/* Watchdog Control and Status Register */ 72#define SBSA_GWDT_WCS_EN BIT(0) 73#define SBSA_GWDT_WCS_WS0 BIT(1) 74#define SBSA_GWDT_WCS_WS1 BIT(2) 75 76/** 77 * struct sbsa_gwdt - Internal representation of the SBSA GWDT 78 * @wdd: kernel watchdog_device structure 79 * @clk: store the System Counter clock frequency, in Hz. 80 * @refresh_base: Virtual address of the watchdog refresh frame 81 * @control_base: Virtual address of the watchdog control frame 82 */ 83struct sbsa_gwdt { 84 struct watchdog_device wdd; 85 u32 clk; 86 void __iomem *refresh_base; 87 void __iomem *control_base; 88}; 89 90#define DEFAULT_TIMEOUT 10 /* seconds */ 91 92static unsigned int timeout; 93module_param(timeout, uint, 0); 94MODULE_PARM_DESC(timeout, 95 "Watchdog timeout in seconds. (>=0, default=" 96 __MODULE_STRING(DEFAULT_TIMEOUT) ")"); 97 98/* 99 * action refers to action taken when watchdog gets WS0 100 * 0 = skip 101 * 1 = panic 102 * defaults to skip (0) 103 */ 104static int action; 105module_param(action, int, 0); 106MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: " 107 "0 = skip(*) 1 = panic"); 108 109static bool nowayout = WATCHDOG_NOWAYOUT; 110module_param(nowayout, bool, S_IRUGO); 111MODULE_PARM_DESC(nowayout, 112 "Watchdog cannot be stopped once started (default=" 113 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 114 115/* 116 * watchdog operation functions 117 */ 118static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, 119 unsigned int timeout) 120{ 121 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 122 123 wdd->timeout = timeout; 124 timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000); 125 126 if (action) 127 writel(gwdt->clk * timeout, 128 gwdt->control_base + SBSA_GWDT_WOR); 129 else 130 /* 131 * In the single stage mode, The first signal (WS0) is ignored, 132 * the timeout is (WOR * 2), so the WOR should be configured 133 * to half value of timeout. 134 */ 135 writel(gwdt->clk / 2 * timeout, 136 gwdt->control_base + SBSA_GWDT_WOR); 137 138 return 0; 139} 140 141static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd) 142{ 143 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 144 u64 timeleft = 0; 145 146 /* 147 * In the single stage mode, if WS0 is deasserted 148 * (watchdog is in the first stage), 149 * timeleft = WOR + (WCV - system counter) 150 */ 151 if (!action && 152 !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0)) 153 timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR); 154 155 timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) - 156 arch_timer_read_counter(); 157 158 do_div(timeleft, gwdt->clk); 159 160 return timeleft; 161} 162 163static int sbsa_gwdt_keepalive(struct watchdog_device *wdd) 164{ 165 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 166 167 /* 168 * Writing WRR for an explicit watchdog refresh. 169 * You can write anyting (like 0). 170 */ 171 writel(0, gwdt->refresh_base + SBSA_GWDT_WRR); 172 173 return 0; 174} 175 176static int sbsa_gwdt_start(struct watchdog_device *wdd) 177{ 178 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 179 180 /* writing WCS will cause an explicit watchdog refresh */ 181 writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS); 182 183 return 0; 184} 185 186static int sbsa_gwdt_stop(struct watchdog_device *wdd) 187{ 188 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); 189 190 /* Simply write 0 to WCS to clean WCS_EN bit */ 191 writel(0, gwdt->control_base + SBSA_GWDT_WCS); 192 193 return 0; 194} 195 196static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id) 197{ 198 panic(WATCHDOG_NAME " timeout"); 199 200 return IRQ_HANDLED; 201} 202 203static const struct watchdog_info sbsa_gwdt_info = { 204 .identity = WATCHDOG_NAME, 205 .options = WDIOF_SETTIMEOUT | 206 WDIOF_KEEPALIVEPING | 207 WDIOF_MAGICCLOSE | 208 WDIOF_CARDRESET, 209}; 210 211static const struct watchdog_ops sbsa_gwdt_ops = { 212 .owner = THIS_MODULE, 213 .start = sbsa_gwdt_start, 214 .stop = sbsa_gwdt_stop, 215 .ping = sbsa_gwdt_keepalive, 216 .set_timeout = sbsa_gwdt_set_timeout, 217 .get_timeleft = sbsa_gwdt_get_timeleft, 218}; 219 220static int sbsa_gwdt_probe(struct platform_device *pdev) 221{ 222 void __iomem *rf_base, *cf_base; 223 struct device *dev = &pdev->dev; 224 struct watchdog_device *wdd; 225 struct sbsa_gwdt *gwdt; 226 int ret, irq; 227 u32 status; 228 229 gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); 230 if (!gwdt) 231 return -ENOMEM; 232 platform_set_drvdata(pdev, gwdt); 233 234 cf_base = devm_platform_ioremap_resource(pdev, 0); 235 if (IS_ERR(cf_base)) 236 return PTR_ERR(cf_base); 237 238 rf_base = devm_platform_ioremap_resource(pdev, 1); 239 if (IS_ERR(rf_base)) 240 return PTR_ERR(rf_base); 241 242 /* 243 * Get the frequency of system counter from the cp15 interface of ARM 244 * Generic timer. We don't need to check it, because if it returns "0", 245 * system would panic in very early stage. 246 */ 247 gwdt->clk = arch_timer_get_cntfrq(); 248 gwdt->refresh_base = rf_base; 249 gwdt->control_base = cf_base; 250 251 wdd = &gwdt->wdd; 252 wdd->parent = dev; 253 wdd->info = &sbsa_gwdt_info; 254 wdd->ops = &sbsa_gwdt_ops; 255 wdd->min_timeout = 1; 256 wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000; 257 wdd->timeout = DEFAULT_TIMEOUT; 258 watchdog_set_drvdata(wdd, gwdt); 259 watchdog_set_nowayout(wdd, nowayout); 260 261 status = readl(cf_base + SBSA_GWDT_WCS); 262 if (status & SBSA_GWDT_WCS_WS1) { 263 dev_warn(dev, "System reset by WDT.\n"); 264 wdd->bootstatus |= WDIOF_CARDRESET; 265 } 266 if (status & SBSA_GWDT_WCS_EN) 267 set_bit(WDOG_HW_RUNNING, &wdd->status); 268 269 if (action) { 270 irq = platform_get_irq(pdev, 0); 271 if (irq < 0) { 272 action = 0; 273 dev_warn(dev, "unable to get ws0 interrupt.\n"); 274 } else { 275 /* 276 * In case there is a pending ws0 interrupt, just ping 277 * the watchdog before registering the interrupt routine 278 */ 279 writel(0, rf_base + SBSA_GWDT_WRR); 280 if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0, 281 pdev->name, gwdt)) { 282 action = 0; 283 dev_warn(dev, "unable to request IRQ %d.\n", 284 irq); 285 } 286 } 287 if (!action) 288 dev_warn(dev, "falling back to single stage mode.\n"); 289 } 290 /* 291 * In the single stage mode, The first signal (WS0) is ignored, 292 * the timeout is (WOR * 2), so the maximum timeout should be doubled. 293 */ 294 if (!action) 295 wdd->max_hw_heartbeat_ms *= 2; 296 297 watchdog_init_timeout(wdd, timeout, dev); 298 /* 299 * Update timeout to WOR. 300 * Because of the explicit watchdog refresh mechanism, 301 * it's also a ping, if watchdog is enabled. 302 */ 303 sbsa_gwdt_set_timeout(wdd, wdd->timeout); 304 305 watchdog_stop_on_reboot(wdd); 306 ret = devm_watchdog_register_device(dev, wdd); 307 if (ret) 308 return ret; 309 310 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n", 311 wdd->timeout, gwdt->clk, action, 312 status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); 313 314 return 0; 315} 316 317/* Disable watchdog if it is active during suspend */ 318static int __maybe_unused sbsa_gwdt_suspend(struct device *dev) 319{ 320 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 321 322 if (watchdog_active(&gwdt->wdd)) 323 sbsa_gwdt_stop(&gwdt->wdd); 324 325 return 0; 326} 327 328/* Enable watchdog if necessary */ 329static int __maybe_unused sbsa_gwdt_resume(struct device *dev) 330{ 331 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); 332 333 if (watchdog_active(&gwdt->wdd)) 334 sbsa_gwdt_start(&gwdt->wdd); 335 336 return 0; 337} 338 339static const struct dev_pm_ops sbsa_gwdt_pm_ops = { 340 SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume) 341}; 342 343static const struct of_device_id sbsa_gwdt_of_match[] = { 344 { .compatible = "arm,sbsa-gwdt", }, 345 {}, 346}; 347MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); 348 349static const struct platform_device_id sbsa_gwdt_pdev_match[] = { 350 { .name = DRV_NAME, }, 351 {}, 352}; 353MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match); 354 355static struct platform_driver sbsa_gwdt_driver = { 356 .driver = { 357 .name = DRV_NAME, 358 .pm = &sbsa_gwdt_pm_ops, 359 .of_match_table = sbsa_gwdt_of_match, 360 }, 361 .probe = sbsa_gwdt_probe, 362 .id_table = sbsa_gwdt_pdev_match, 363}; 364 365module_platform_driver(sbsa_gwdt_driver); 366 367MODULE_DESCRIPTION("SBSA Generic Watchdog Driver"); 368MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>"); 369MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>"); 370MODULE_AUTHOR("Al Stone <al.stone@linaro.org>"); 371MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>"); 372MODULE_LICENSE("GPL v2"); 373MODULE_ALIAS("platform:" DRV_NAME); 374