1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 */
4#include <linux/bits.h>
5#include <linux/clk.h>
6#include <linux/delay.h>
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/watchdog.h>
14#include <linux/of_device.h>
15
16enum wdt_reg {
17	WDT_RST,
18	WDT_EN,
19	WDT_STS,
20	WDT_BARK_TIME,
21	WDT_BITE_TIME,
22};
23
24#define QCOM_WDT_ENABLE		BIT(0)
25
26static const u32 reg_offset_data_apcs_tmr[] = {
27	[WDT_RST] = 0x38,
28	[WDT_EN] = 0x40,
29	[WDT_STS] = 0x44,
30	[WDT_BARK_TIME] = 0x4C,
31	[WDT_BITE_TIME] = 0x5C,
32};
33
34static const u32 reg_offset_data_kpss[] = {
35	[WDT_RST] = 0x4,
36	[WDT_EN] = 0x8,
37	[WDT_STS] = 0xC,
38	[WDT_BARK_TIME] = 0x10,
39	[WDT_BITE_TIME] = 0x14,
40};
41
42struct qcom_wdt_match_data {
43	const u32 *offset;
44	bool pretimeout;
45};
46
47struct qcom_wdt {
48	struct watchdog_device	wdd;
49	unsigned long		rate;
50	void __iomem		*base;
51	const u32		*layout;
52};
53
54static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
55{
56	return wdt->base + wdt->layout[reg];
57}
58
59static inline
60struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
61{
62	return container_of(wdd, struct qcom_wdt, wdd);
63}
64
65static irqreturn_t qcom_wdt_isr(int irq, void *arg)
66{
67	struct watchdog_device *wdd = arg;
68
69	watchdog_notify_pretimeout(wdd);
70
71	return IRQ_HANDLED;
72}
73
74static int qcom_wdt_start(struct watchdog_device *wdd)
75{
76	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
77	unsigned int bark = wdd->timeout - wdd->pretimeout;
78
79	writel(0, wdt_addr(wdt, WDT_EN));
80	writel(1, wdt_addr(wdt, WDT_RST));
81	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
82	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
83	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
84	return 0;
85}
86
87static int qcom_wdt_stop(struct watchdog_device *wdd)
88{
89	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
90
91	writel(0, wdt_addr(wdt, WDT_EN));
92	return 0;
93}
94
95static int qcom_wdt_ping(struct watchdog_device *wdd)
96{
97	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
98
99	writel(1, wdt_addr(wdt, WDT_RST));
100	return 0;
101}
102
103static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
104				unsigned int timeout)
105{
106	wdd->timeout = timeout;
107	return qcom_wdt_start(wdd);
108}
109
110static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
111				   unsigned int timeout)
112{
113	wdd->pretimeout = timeout;
114	return qcom_wdt_start(wdd);
115}
116
117static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
118			    void *data)
119{
120	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
121	u32 timeout;
122
123	/*
124	 * Trigger watchdog bite:
125	 *    Setup BITE_TIME to be 128ms, and enable WDT.
126	 */
127	timeout = 128 * wdt->rate / 1000;
128
129	writel(0, wdt_addr(wdt, WDT_EN));
130	writel(1, wdt_addr(wdt, WDT_RST));
131	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
132	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
133	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
134
135	/*
136	 * Actually make sure the above sequence hits hardware before sleeping.
137	 */
138	wmb();
139
140	mdelay(150);
141	return 0;
142}
143
144static const struct watchdog_ops qcom_wdt_ops = {
145	.start		= qcom_wdt_start,
146	.stop		= qcom_wdt_stop,
147	.ping		= qcom_wdt_ping,
148	.set_timeout	= qcom_wdt_set_timeout,
149	.set_pretimeout	= qcom_wdt_set_pretimeout,
150	.restart        = qcom_wdt_restart,
151	.owner		= THIS_MODULE,
152};
153
154static const struct watchdog_info qcom_wdt_info = {
155	.options	= WDIOF_KEEPALIVEPING
156			| WDIOF_MAGICCLOSE
157			| WDIOF_SETTIMEOUT
158			| WDIOF_CARDRESET,
159	.identity	= KBUILD_MODNAME,
160};
161
162static const struct watchdog_info qcom_wdt_pt_info = {
163	.options	= WDIOF_KEEPALIVEPING
164			| WDIOF_MAGICCLOSE
165			| WDIOF_SETTIMEOUT
166			| WDIOF_PRETIMEOUT
167			| WDIOF_CARDRESET,
168	.identity	= KBUILD_MODNAME,
169};
170
171static void qcom_clk_disable_unprepare(void *data)
172{
173	clk_disable_unprepare(data);
174}
175
176static const struct qcom_wdt_match_data match_data_apcs_tmr = {
177	.offset = reg_offset_data_apcs_tmr,
178	.pretimeout = false,
179};
180
181static const struct qcom_wdt_match_data match_data_kpss = {
182	.offset = reg_offset_data_kpss,
183	.pretimeout = true,
184};
185
186static int qcom_wdt_probe(struct platform_device *pdev)
187{
188	struct device *dev = &pdev->dev;
189	struct qcom_wdt *wdt;
190	struct resource *res;
191	struct device_node *np = dev->of_node;
192	const struct qcom_wdt_match_data *data;
193	u32 percpu_offset;
194	int irq, ret;
195	struct clk *clk;
196
197	data = of_device_get_match_data(dev);
198	if (!data) {
199		dev_err(dev, "Unsupported QCOM WDT module\n");
200		return -ENODEV;
201	}
202
203	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
204	if (!wdt)
205		return -ENOMEM;
206
207	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208	if (!res)
209		return -ENOMEM;
210
211	/* We use CPU0's DGT for the watchdog */
212	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
213		percpu_offset = 0;
214
215	res->start += percpu_offset;
216	res->end += percpu_offset;
217
218	wdt->base = devm_ioremap_resource(dev, res);
219	if (IS_ERR(wdt->base))
220		return PTR_ERR(wdt->base);
221
222	clk = devm_clk_get(dev, NULL);
223	if (IS_ERR(clk)) {
224		dev_err(dev, "failed to get input clock\n");
225		return PTR_ERR(clk);
226	}
227
228	ret = clk_prepare_enable(clk);
229	if (ret) {
230		dev_err(dev, "failed to setup clock\n");
231		return ret;
232	}
233	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
234	if (ret)
235		return ret;
236
237	/*
238	 * We use the clock rate to calculate the max timeout, so ensure it's
239	 * not zero to avoid a divide-by-zero exception.
240	 *
241	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
242	 * that it would bite before a second elapses it's usefulness is
243	 * limited.  Bail if this is the case.
244	 */
245	wdt->rate = clk_get_rate(clk);
246	if (wdt->rate == 0 ||
247	    wdt->rate > 0x10000000U) {
248		dev_err(dev, "invalid clock rate\n");
249		return -EINVAL;
250	}
251
252	/* check if there is pretimeout support */
253	irq = platform_get_irq_optional(pdev, 0);
254	if (data->pretimeout && irq > 0) {
255		ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
256				       "wdt_bark", &wdt->wdd);
257		if (ret)
258			return ret;
259
260		wdt->wdd.info = &qcom_wdt_pt_info;
261		wdt->wdd.pretimeout = 1;
262	} else {
263		if (irq == -EPROBE_DEFER)
264			return -EPROBE_DEFER;
265
266		wdt->wdd.info = &qcom_wdt_info;
267	}
268
269	wdt->wdd.ops = &qcom_wdt_ops;
270	wdt->wdd.min_timeout = 1;
271	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
272	wdt->wdd.parent = dev;
273	wdt->layout = data->offset;
274
275	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
276		wdt->wdd.bootstatus = WDIOF_CARDRESET;
277
278	/*
279	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
280	 * default, unless the max timeout is less than 30 seconds, then use
281	 * the max instead.
282	 */
283	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
284	watchdog_init_timeout(&wdt->wdd, 0, dev);
285
286	ret = devm_watchdog_register_device(dev, &wdt->wdd);
287	if (ret)
288		return ret;
289
290	platform_set_drvdata(pdev, wdt);
291	return 0;
292}
293
294static int __maybe_unused qcom_wdt_suspend(struct device *dev)
295{
296	struct qcom_wdt *wdt = dev_get_drvdata(dev);
297
298	if (watchdog_active(&wdt->wdd))
299		qcom_wdt_stop(&wdt->wdd);
300
301	return 0;
302}
303
304static int __maybe_unused qcom_wdt_resume(struct device *dev)
305{
306	struct qcom_wdt *wdt = dev_get_drvdata(dev);
307
308	if (watchdog_active(&wdt->wdd))
309		qcom_wdt_start(&wdt->wdd);
310
311	return 0;
312}
313
314static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
315
316static const struct of_device_id qcom_wdt_of_table[] = {
317	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
318	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
319	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
320	{ },
321};
322MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
323
324static struct platform_driver qcom_watchdog_driver = {
325	.probe	= qcom_wdt_probe,
326	.driver	= {
327		.name		= KBUILD_MODNAME,
328		.of_match_table	= qcom_wdt_of_table,
329		.pm		= &qcom_wdt_pm_ops,
330	},
331};
332module_platform_driver(qcom_watchdog_driver);
333
334MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
335MODULE_LICENSE("GPL v2");
336