1// SPDX-License-Identifier: GPL-2.0-or-later 2/*************************************************************************** 3 * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> * 4 * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> * 5 * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> * 6 * * 7 ***************************************************************************/ 8 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11#include <linux/err.h> 12#include <linux/fs.h> 13#include <linux/init.h> 14#include <linux/io.h> 15#include <linux/ioport.h> 16#include <linux/miscdevice.h> 17#include <linux/module.h> 18#include <linux/mutex.h> 19#include <linux/notifier.h> 20#include <linux/reboot.h> 21#include <linux/uaccess.h> 22#include <linux/watchdog.h> 23 24#define DRVNAME "f71808e_wdt" 25 26#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */ 27#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */ 28#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ 29 30#define SIO_REG_LDSEL 0x07 /* Logical device select */ 31#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ 32#define SIO_REG_DEVREV 0x22 /* Device revision */ 33#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */ 34#define SIO_REG_CLOCK_SEL 0x26 /* Clock select */ 35#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */ 36#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */ 37#define SIO_REG_TSI_LEVEL_SEL 0x28 /* TSI Level select */ 38#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */ 39#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */ 40#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */ 41#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */ 42#define SIO_REG_ENABLE 0x30 /* Logical device enable */ 43#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ 44 45#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */ 46#define SIO_F71808_ID 0x0901 /* Chipset ID */ 47#define SIO_F71858_ID 0x0507 /* Chipset ID */ 48#define SIO_F71862_ID 0x0601 /* Chipset ID */ 49#define SIO_F71868_ID 0x1106 /* Chipset ID */ 50#define SIO_F71869_ID 0x0814 /* Chipset ID */ 51#define SIO_F71869A_ID 0x1007 /* Chipset ID */ 52#define SIO_F71882_ID 0x0541 /* Chipset ID */ 53#define SIO_F71889_ID 0x0723 /* Chipset ID */ 54#define SIO_F81803_ID 0x1210 /* Chipset ID */ 55#define SIO_F81865_ID 0x0704 /* Chipset ID */ 56#define SIO_F81866_ID 0x1010 /* Chipset ID */ 57 58#define F71808FG_REG_WDO_CONF 0xf0 59#define F71808FG_REG_WDT_CONF 0xf5 60#define F71808FG_REG_WD_TIME 0xf6 61 62#define F71808FG_FLAG_WDOUT_EN 7 63 64#define F71808FG_FLAG_WDTMOUT_STS 6 65#define F71808FG_FLAG_WD_EN 5 66#define F71808FG_FLAG_WD_PULSE 4 67#define F71808FG_FLAG_WD_UNIT 3 68 69#define F81865_REG_WDO_CONF 0xfa 70#define F81865_FLAG_WDOUT_EN 0 71 72/* Default values */ 73#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */ 74#define WATCHDOG_MAX_TIMEOUT (60 * 255) 75#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for 76 watchdog signal */ 77#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output 78 pin number 63 */ 79 80static unsigned short force_id; 81module_param(force_id, ushort, 0); 82MODULE_PARM_DESC(force_id, "Override the detected device ID"); 83 84static const int max_timeout = WATCHDOG_MAX_TIMEOUT; 85static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */ 86module_param(timeout, int, 0); 87MODULE_PARM_DESC(timeout, 88 "Watchdog timeout in seconds. 1<= timeout <=" 89 __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default=" 90 __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); 91 92static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH; 93module_param(pulse_width, uint, 0); 94MODULE_PARM_DESC(pulse_width, 95 "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms" 96 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")"); 97 98static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN; 99module_param(f71862fg_pin, uint, 0); 100MODULE_PARM_DESC(f71862fg_pin, 101 "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63" 102 " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")"); 103 104static bool nowayout = WATCHDOG_NOWAYOUT; 105module_param(nowayout, bool, 0444); 106MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); 107 108static unsigned int start_withtimeout; 109module_param(start_withtimeout, uint, 0); 110MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with" 111 " given initial timeout. Zero (default) disables this feature."); 112 113enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg, 114 f81803, f81865, f81866}; 115 116static const char *f71808e_names[] = { 117 "f71808fg", 118 "f71858fg", 119 "f71862fg", 120 "f71868", 121 "f71869", 122 "f71882fg", 123 "f71889fg", 124 "f81803", 125 "f81865", 126 "f81866", 127}; 128 129/* Super-I/O Function prototypes */ 130static inline int superio_inb(int base, int reg); 131static inline int superio_inw(int base, int reg); 132static inline void superio_outb(int base, int reg, u8 val); 133static inline void superio_set_bit(int base, int reg, int bit); 134static inline void superio_clear_bit(int base, int reg, int bit); 135static inline int superio_enter(int base); 136static inline void superio_select(int base, int ld); 137static inline void superio_exit(int base); 138 139struct watchdog_data { 140 unsigned short sioaddr; 141 enum chips type; 142 unsigned long opened; 143 struct mutex lock; 144 char expect_close; 145 struct watchdog_info ident; 146 147 unsigned short timeout; 148 u8 timer_val; /* content for the wd_time register */ 149 char minutes_mode; 150 u8 pulse_val; /* pulse width flag */ 151 char pulse_mode; /* enable pulse output mode? */ 152 char caused_reboot; /* last reboot was by the watchdog */ 153}; 154 155static struct watchdog_data watchdog = { 156 .lock = __MUTEX_INITIALIZER(watchdog.lock), 157}; 158 159/* Super I/O functions */ 160static inline int superio_inb(int base, int reg) 161{ 162 outb(reg, base); 163 return inb(base + 1); 164} 165 166static int superio_inw(int base, int reg) 167{ 168 int val; 169 val = superio_inb(base, reg) << 8; 170 val |= superio_inb(base, reg + 1); 171 return val; 172} 173 174static inline void superio_outb(int base, int reg, u8 val) 175{ 176 outb(reg, base); 177 outb(val, base + 1); 178} 179 180static inline void superio_set_bit(int base, int reg, int bit) 181{ 182 unsigned long val = superio_inb(base, reg); 183 __set_bit(bit, &val); 184 superio_outb(base, reg, val); 185} 186 187static inline void superio_clear_bit(int base, int reg, int bit) 188{ 189 unsigned long val = superio_inb(base, reg); 190 __clear_bit(bit, &val); 191 superio_outb(base, reg, val); 192} 193 194static inline int superio_enter(int base) 195{ 196 /* Don't step on other drivers' I/O space by accident */ 197 if (!request_muxed_region(base, 2, DRVNAME)) { 198 pr_err("I/O address 0x%04x already in use\n", (int)base); 199 return -EBUSY; 200 } 201 202 /* according to the datasheet the key must be sent twice! */ 203 outb(SIO_UNLOCK_KEY, base); 204 outb(SIO_UNLOCK_KEY, base); 205 206 return 0; 207} 208 209static inline void superio_select(int base, int ld) 210{ 211 outb(SIO_REG_LDSEL, base); 212 outb(ld, base + 1); 213} 214 215static inline void superio_exit(int base) 216{ 217 outb(SIO_LOCK_KEY, base); 218 release_region(base, 2); 219} 220 221static int watchdog_set_timeout(int timeout) 222{ 223 if (timeout <= 0 224 || timeout > max_timeout) { 225 pr_err("watchdog timeout out of range\n"); 226 return -EINVAL; 227 } 228 229 mutex_lock(&watchdog.lock); 230 231 if (timeout > 0xff) { 232 watchdog.timer_val = DIV_ROUND_UP(timeout, 60); 233 watchdog.minutes_mode = true; 234 timeout = watchdog.timer_val * 60; 235 } else { 236 watchdog.timer_val = timeout; 237 watchdog.minutes_mode = false; 238 } 239 240 watchdog.timeout = timeout; 241 242 mutex_unlock(&watchdog.lock); 243 244 return 0; 245} 246 247static int watchdog_set_pulse_width(unsigned int pw) 248{ 249 int err = 0; 250 unsigned int t1 = 25, t2 = 125, t3 = 5000; 251 252 if (watchdog.type == f71868) { 253 t1 = 30; 254 t2 = 150; 255 t3 = 6000; 256 } 257 258 mutex_lock(&watchdog.lock); 259 260 if (pw <= 1) { 261 watchdog.pulse_val = 0; 262 } else if (pw <= t1) { 263 watchdog.pulse_val = 1; 264 } else if (pw <= t2) { 265 watchdog.pulse_val = 2; 266 } else if (pw <= t3) { 267 watchdog.pulse_val = 3; 268 } else { 269 pr_err("pulse width out of range\n"); 270 err = -EINVAL; 271 goto exit_unlock; 272 } 273 274 watchdog.pulse_mode = pw; 275 276exit_unlock: 277 mutex_unlock(&watchdog.lock); 278 return err; 279} 280 281static int watchdog_keepalive(void) 282{ 283 int err = 0; 284 285 mutex_lock(&watchdog.lock); 286 err = superio_enter(watchdog.sioaddr); 287 if (err) 288 goto exit_unlock; 289 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 290 291 if (watchdog.minutes_mode) 292 /* select minutes for timer units */ 293 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 294 F71808FG_FLAG_WD_UNIT); 295 else 296 /* select seconds for timer units */ 297 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 298 F71808FG_FLAG_WD_UNIT); 299 300 /* Set timer value */ 301 superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME, 302 watchdog.timer_val); 303 304 superio_exit(watchdog.sioaddr); 305 306exit_unlock: 307 mutex_unlock(&watchdog.lock); 308 return err; 309} 310 311static int watchdog_start(void) 312{ 313 int err; 314 u8 tmp; 315 316 /* Make sure we don't die as soon as the watchdog is enabled below */ 317 err = watchdog_keepalive(); 318 if (err) 319 return err; 320 321 mutex_lock(&watchdog.lock); 322 err = superio_enter(watchdog.sioaddr); 323 if (err) 324 goto exit_unlock; 325 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 326 327 /* Watchdog pin configuration */ 328 switch (watchdog.type) { 329 case f71808fg: 330 /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */ 331 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3); 332 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3); 333 break; 334 335 case f71862fg: 336 if (f71862fg_pin == 63) { 337 /* SPI must be disabled first to use this pin! */ 338 superio_clear_bit(watchdog.sioaddr, SIO_REG_ROM_ADDR_SEL, 6); 339 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 4); 340 } else if (f71862fg_pin == 56) { 341 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1); 342 } 343 break; 344 345 case f71868: 346 case f71869: 347 /* GPIO14 --> WDTRST# */ 348 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4); 349 break; 350 351 case f71882fg: 352 /* Set pin 56 to WDTRST# */ 353 superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1); 354 break; 355 356 case f71889fg: 357 /* set pin 40 to WDTRST# */ 358 superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3, 359 superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf); 360 break; 361 362 case f81803: 363 /* Enable TSI Level register bank */ 364 superio_clear_bit(watchdog.sioaddr, SIO_REG_CLOCK_SEL, 3); 365 /* Set pin 27 to WDTRST# */ 366 superio_outb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f & 367 superio_inb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL)); 368 break; 369 370 case f81865: 371 /* Set pin 70 to WDTRST# */ 372 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5); 373 break; 374 375 case f81866: 376 /* 377 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0. 378 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch: 379 * BIT5: 0 -> WDTRST# 380 * 1 -> GPIO15 381 */ 382 tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL); 383 tmp &= ~(BIT(3) | BIT(0)); 384 tmp |= BIT(2); 385 superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp); 386 387 superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5); 388 break; 389 390 default: 391 /* 392 * 'default' label to shut up the compiler and catch 393 * programmer errors 394 */ 395 err = -ENODEV; 396 goto exit_superio; 397 } 398 399 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 400 superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0); 401 402 if (watchdog.type == f81865 || watchdog.type == f81866) 403 superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF, 404 F81865_FLAG_WDOUT_EN); 405 else 406 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF, 407 F71808FG_FLAG_WDOUT_EN); 408 409 superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 410 F71808FG_FLAG_WD_EN); 411 412 if (watchdog.pulse_mode) { 413 /* Select "pulse" output mode with given duration */ 414 u8 wdt_conf = superio_inb(watchdog.sioaddr, 415 F71808FG_REG_WDT_CONF); 416 417 /* Set WD_PSWIDTH bits (1:0) */ 418 wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03); 419 /* Set WD_PULSE to "pulse" mode */ 420 wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE); 421 422 superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 423 wdt_conf); 424 } else { 425 /* Select "level" output mode */ 426 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 427 F71808FG_FLAG_WD_PULSE); 428 } 429 430exit_superio: 431 superio_exit(watchdog.sioaddr); 432exit_unlock: 433 mutex_unlock(&watchdog.lock); 434 435 return err; 436} 437 438static int watchdog_stop(void) 439{ 440 int err = 0; 441 442 mutex_lock(&watchdog.lock); 443 err = superio_enter(watchdog.sioaddr); 444 if (err) 445 goto exit_unlock; 446 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 447 448 superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, 449 F71808FG_FLAG_WD_EN); 450 451 superio_exit(watchdog.sioaddr); 452 453exit_unlock: 454 mutex_unlock(&watchdog.lock); 455 456 return err; 457} 458 459static int watchdog_get_status(void) 460{ 461 int status = 0; 462 463 mutex_lock(&watchdog.lock); 464 status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0; 465 mutex_unlock(&watchdog.lock); 466 467 return status; 468} 469 470static bool watchdog_is_running(void) 471{ 472 /* 473 * if we fail to determine the watchdog's status assume it to be 474 * running to be on the safe side 475 */ 476 bool is_running = true; 477 478 mutex_lock(&watchdog.lock); 479 if (superio_enter(watchdog.sioaddr)) 480 goto exit_unlock; 481 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 482 483 is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0)) 484 && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF) 485 & BIT(F71808FG_FLAG_WD_EN)); 486 487 superio_exit(watchdog.sioaddr); 488 489exit_unlock: 490 mutex_unlock(&watchdog.lock); 491 return is_running; 492} 493 494/* /dev/watchdog api */ 495 496static int watchdog_open(struct inode *inode, struct file *file) 497{ 498 int err; 499 500 /* If the watchdog is alive we don't need to start it again */ 501 if (test_and_set_bit(0, &watchdog.opened)) 502 return -EBUSY; 503 504 err = watchdog_start(); 505 if (err) { 506 clear_bit(0, &watchdog.opened); 507 return err; 508 } 509 510 if (nowayout) 511 __module_get(THIS_MODULE); 512 513 watchdog.expect_close = 0; 514 return stream_open(inode, file); 515} 516 517static int watchdog_release(struct inode *inode, struct file *file) 518{ 519 clear_bit(0, &watchdog.opened); 520 521 if (!watchdog.expect_close) { 522 watchdog_keepalive(); 523 pr_crit("Unexpected close, not stopping watchdog!\n"); 524 } else if (!nowayout) { 525 watchdog_stop(); 526 } 527 return 0; 528} 529 530/* 531 * watchdog_write: 532 * @file: file handle to the watchdog 533 * @buf: buffer to write 534 * @count: count of bytes 535 * @ppos: pointer to the position to write. No seeks allowed 536 * 537 * A write to a watchdog device is defined as a keepalive signal. Any 538 * write of data will do, as we we don't define content meaning. 539 */ 540 541static ssize_t watchdog_write(struct file *file, const char __user *buf, 542 size_t count, loff_t *ppos) 543{ 544 if (count) { 545 if (!nowayout) { 546 size_t i; 547 548 /* In case it was set long ago */ 549 bool expect_close = false; 550 551 for (i = 0; i != count; i++) { 552 char c; 553 if (get_user(c, buf + i)) 554 return -EFAULT; 555 if (c == 'V') 556 expect_close = true; 557 } 558 559 /* Properly order writes across fork()ed processes */ 560 mutex_lock(&watchdog.lock); 561 watchdog.expect_close = expect_close; 562 mutex_unlock(&watchdog.lock); 563 } 564 565 /* someone wrote to us, we should restart timer */ 566 watchdog_keepalive(); 567 } 568 return count; 569} 570 571/* 572 * watchdog_ioctl: 573 * @inode: inode of the device 574 * @file: file handle to the device 575 * @cmd: watchdog command 576 * @arg: argument pointer 577 * 578 * The watchdog API defines a common set of functions for all watchdogs 579 * according to their available features. 580 */ 581static long watchdog_ioctl(struct file *file, unsigned int cmd, 582 unsigned long arg) 583{ 584 int status; 585 int new_options; 586 int new_timeout; 587 union { 588 struct watchdog_info __user *ident; 589 int __user *i; 590 } uarg; 591 592 uarg.i = (int __user *)arg; 593 594 switch (cmd) { 595 case WDIOC_GETSUPPORT: 596 return copy_to_user(uarg.ident, &watchdog.ident, 597 sizeof(watchdog.ident)) ? -EFAULT : 0; 598 599 case WDIOC_GETSTATUS: 600 status = watchdog_get_status(); 601 if (status < 0) 602 return status; 603 return put_user(status, uarg.i); 604 605 case WDIOC_GETBOOTSTATUS: 606 return put_user(0, uarg.i); 607 608 case WDIOC_SETOPTIONS: 609 if (get_user(new_options, uarg.i)) 610 return -EFAULT; 611 612 if (new_options & WDIOS_DISABLECARD) 613 watchdog_stop(); 614 615 if (new_options & WDIOS_ENABLECARD) 616 return watchdog_start(); 617 fallthrough; 618 619 case WDIOC_KEEPALIVE: 620 watchdog_keepalive(); 621 return 0; 622 623 case WDIOC_SETTIMEOUT: 624 if (get_user(new_timeout, uarg.i)) 625 return -EFAULT; 626 627 if (watchdog_set_timeout(new_timeout)) 628 return -EINVAL; 629 630 watchdog_keepalive(); 631 fallthrough; 632 633 case WDIOC_GETTIMEOUT: 634 return put_user(watchdog.timeout, uarg.i); 635 636 default: 637 return -ENOTTY; 638 639 } 640} 641 642static int watchdog_notify_sys(struct notifier_block *this, unsigned long code, 643 void *unused) 644{ 645 if (code == SYS_DOWN || code == SYS_HALT) 646 watchdog_stop(); 647 return NOTIFY_DONE; 648} 649 650static const struct file_operations watchdog_fops = { 651 .owner = THIS_MODULE, 652 .llseek = no_llseek, 653 .open = watchdog_open, 654 .release = watchdog_release, 655 .write = watchdog_write, 656 .unlocked_ioctl = watchdog_ioctl, 657 .compat_ioctl = compat_ptr_ioctl, 658}; 659 660static struct miscdevice watchdog_miscdev = { 661 .minor = WATCHDOG_MINOR, 662 .name = "watchdog", 663 .fops = &watchdog_fops, 664}; 665 666static struct notifier_block watchdog_notifier = { 667 .notifier_call = watchdog_notify_sys, 668}; 669 670static int __init watchdog_init(int sioaddr) 671{ 672 int wdt_conf, err = 0; 673 674 /* No need to lock watchdog.lock here because no entry points 675 * into the module have been registered yet. 676 */ 677 watchdog.sioaddr = sioaddr; 678 watchdog.ident.options = WDIOF_MAGICCLOSE 679 | WDIOF_KEEPALIVEPING 680 | WDIOF_CARDRESET; 681 682 snprintf(watchdog.ident.identity, 683 sizeof(watchdog.ident.identity), "%s watchdog", 684 f71808e_names[watchdog.type]); 685 686 err = superio_enter(sioaddr); 687 if (err) 688 return err; 689 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 690 691 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF); 692 watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS); 693 694 /* 695 * We don't want WDTMOUT_STS to stick around till regular reboot. 696 * Write 1 to the bit to clear it to zero. 697 */ 698 superio_outb(sioaddr, F71808FG_REG_WDT_CONF, 699 wdt_conf | BIT(F71808FG_FLAG_WDTMOUT_STS)); 700 701 superio_exit(sioaddr); 702 703 err = watchdog_set_timeout(timeout); 704 if (err) 705 return err; 706 err = watchdog_set_pulse_width(pulse_width); 707 if (err) 708 return err; 709 710 err = register_reboot_notifier(&watchdog_notifier); 711 if (err) 712 return err; 713 714 err = misc_register(&watchdog_miscdev); 715 if (err) { 716 pr_err("cannot register miscdev on minor=%d\n", 717 watchdog_miscdev.minor); 718 goto exit_reboot; 719 } 720 721 if (start_withtimeout) { 722 if (start_withtimeout <= 0 723 || start_withtimeout > max_timeout) { 724 pr_err("starting timeout out of range\n"); 725 err = -EINVAL; 726 goto exit_miscdev; 727 } 728 729 err = watchdog_start(); 730 if (err) { 731 pr_err("cannot start watchdog timer\n"); 732 goto exit_miscdev; 733 } 734 735 mutex_lock(&watchdog.lock); 736 err = superio_enter(sioaddr); 737 if (err) 738 goto exit_unlock; 739 superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); 740 741 if (start_withtimeout > 0xff) { 742 /* select minutes for timer units */ 743 superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF, 744 F71808FG_FLAG_WD_UNIT); 745 superio_outb(sioaddr, F71808FG_REG_WD_TIME, 746 DIV_ROUND_UP(start_withtimeout, 60)); 747 } else { 748 /* select seconds for timer units */ 749 superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF, 750 F71808FG_FLAG_WD_UNIT); 751 superio_outb(sioaddr, F71808FG_REG_WD_TIME, 752 start_withtimeout); 753 } 754 755 superio_exit(sioaddr); 756 mutex_unlock(&watchdog.lock); 757 758 if (nowayout) 759 __module_get(THIS_MODULE); 760 761 pr_info("watchdog started with initial timeout of %u sec\n", 762 start_withtimeout); 763 } 764 765 return 0; 766 767exit_unlock: 768 mutex_unlock(&watchdog.lock); 769exit_miscdev: 770 misc_deregister(&watchdog_miscdev); 771exit_reboot: 772 unregister_reboot_notifier(&watchdog_notifier); 773 774 return err; 775} 776 777static int __init f71808e_find(int sioaddr) 778{ 779 u16 devid; 780 int err = superio_enter(sioaddr); 781 if (err) 782 return err; 783 784 devid = superio_inw(sioaddr, SIO_REG_MANID); 785 if (devid != SIO_FINTEK_ID) { 786 pr_debug("Not a Fintek device\n"); 787 err = -ENODEV; 788 goto exit; 789 } 790 791 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID); 792 switch (devid) { 793 case SIO_F71808_ID: 794 watchdog.type = f71808fg; 795 break; 796 case SIO_F71862_ID: 797 watchdog.type = f71862fg; 798 break; 799 case SIO_F71868_ID: 800 watchdog.type = f71868; 801 break; 802 case SIO_F71869_ID: 803 case SIO_F71869A_ID: 804 watchdog.type = f71869; 805 break; 806 case SIO_F71882_ID: 807 watchdog.type = f71882fg; 808 break; 809 case SIO_F71889_ID: 810 watchdog.type = f71889fg; 811 break; 812 case SIO_F71858_ID: 813 /* Confirmed (by datasheet) not to have a watchdog. */ 814 err = -ENODEV; 815 goto exit; 816 case SIO_F81803_ID: 817 watchdog.type = f81803; 818 break; 819 case SIO_F81865_ID: 820 watchdog.type = f81865; 821 break; 822 case SIO_F81866_ID: 823 watchdog.type = f81866; 824 break; 825 default: 826 pr_info("Unrecognized Fintek device: %04x\n", 827 (unsigned int)devid); 828 err = -ENODEV; 829 goto exit; 830 } 831 832 pr_info("Found %s watchdog chip, revision %d\n", 833 f71808e_names[watchdog.type], 834 (int)superio_inb(sioaddr, SIO_REG_DEVREV)); 835exit: 836 superio_exit(sioaddr); 837 return err; 838} 839 840static int __init f71808e_init(void) 841{ 842 static const unsigned short addrs[] = { 0x2e, 0x4e }; 843 int err = -ENODEV; 844 int i; 845 846 if (f71862fg_pin != 63 && f71862fg_pin != 56) { 847 pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin); 848 return -EINVAL; 849 } 850 851 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 852 err = f71808e_find(addrs[i]); 853 if (err == 0) 854 break; 855 } 856 if (i == ARRAY_SIZE(addrs)) 857 return err; 858 859 return watchdog_init(addrs[i]); 860} 861 862static void __exit f71808e_exit(void) 863{ 864 if (watchdog_is_running()) { 865 pr_warn("Watchdog timer still running, stopping it\n"); 866 watchdog_stop(); 867 } 868 misc_deregister(&watchdog_miscdev); 869 unregister_reboot_notifier(&watchdog_notifier); 870} 871 872MODULE_DESCRIPTION("F71808E Watchdog Driver"); 873MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>"); 874MODULE_LICENSE("GPL"); 875 876module_init(f71808e_init); 877module_exit(f71808e_exit); 878