18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
48c2ecf20Sopenharmony_ci * Copyright 2008 Luotao Fu, kernel@pengutronix.de
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci#include <linux/clk.h>
88c2ecf20Sopenharmony_ci#include <linux/delay.h>
98c2ecf20Sopenharmony_ci#include <linux/io.h>
108c2ecf20Sopenharmony_ci#include <linux/ktime.h>
118c2ecf20Sopenharmony_ci#include <linux/module.h>
128c2ecf20Sopenharmony_ci#include <linux/mod_devicetable.h>
138c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci#include <linux/w1.h>
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci/*
188c2ecf20Sopenharmony_ci * MXC W1 Register offsets
198c2ecf20Sopenharmony_ci */
208c2ecf20Sopenharmony_ci#define MXC_W1_CONTROL		0x00
218c2ecf20Sopenharmony_ci# define MXC_W1_CONTROL_RDST	BIT(3)
228c2ecf20Sopenharmony_ci# define MXC_W1_CONTROL_WR(x)	BIT(5 - (x))
238c2ecf20Sopenharmony_ci# define MXC_W1_CONTROL_PST	BIT(6)
248c2ecf20Sopenharmony_ci# define MXC_W1_CONTROL_RPP	BIT(7)
258c2ecf20Sopenharmony_ci#define MXC_W1_TIME_DIVIDER	0x02
268c2ecf20Sopenharmony_ci#define MXC_W1_RESET		0x04
278c2ecf20Sopenharmony_ci# define MXC_W1_RESET_RST	BIT(0)
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_cistruct mxc_w1_device {
308c2ecf20Sopenharmony_ci	void __iomem *regs;
318c2ecf20Sopenharmony_ci	struct clk *clk;
328c2ecf20Sopenharmony_ci	struct w1_bus_master bus_master;
338c2ecf20Sopenharmony_ci};
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci/*
368c2ecf20Sopenharmony_ci * this is the low level routine to
378c2ecf20Sopenharmony_ci * reset the device on the One Wire interface
388c2ecf20Sopenharmony_ci * on the hardware
398c2ecf20Sopenharmony_ci */
408c2ecf20Sopenharmony_cistatic u8 mxc_w1_ds2_reset_bus(void *data)
418c2ecf20Sopenharmony_ci{
428c2ecf20Sopenharmony_ci	struct mxc_w1_device *dev = data;
438c2ecf20Sopenharmony_ci	ktime_t timeout;
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ci	writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci	/* Wait for reset sequence 511+512us, use 1500us for sure */
488c2ecf20Sopenharmony_ci	timeout = ktime_add_us(ktime_get(), 1500);
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci	udelay(511 + 512);
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci	do {
538c2ecf20Sopenharmony_ci		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci		/* PST bit is valid after the RPP bit is self-cleared */
568c2ecf20Sopenharmony_ci		if (!(ctrl & MXC_W1_CONTROL_RPP))
578c2ecf20Sopenharmony_ci			return !(ctrl & MXC_W1_CONTROL_PST);
588c2ecf20Sopenharmony_ci	} while (ktime_before(ktime_get(), timeout));
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci	return 1;
618c2ecf20Sopenharmony_ci}
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci/*
648c2ecf20Sopenharmony_ci * this is the low level routine to read/write a bit on the One Wire
658c2ecf20Sopenharmony_ci * interface on the hardware. It does write 0 if parameter bit is set
668c2ecf20Sopenharmony_ci * to 0, otherwise a write 1/read.
678c2ecf20Sopenharmony_ci */
688c2ecf20Sopenharmony_cistatic u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
698c2ecf20Sopenharmony_ci{
708c2ecf20Sopenharmony_ci	struct mxc_w1_device *dev = data;
718c2ecf20Sopenharmony_ci	ktime_t timeout;
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ci	writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci	/* Wait for read/write bit (60us, Max 120us), use 200us for sure */
768c2ecf20Sopenharmony_ci	timeout = ktime_add_us(ktime_get(), 200);
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci	udelay(60);
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ci	do {
818c2ecf20Sopenharmony_ci		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ci		/* RDST bit is valid after the WR1/RD bit is self-cleared */
848c2ecf20Sopenharmony_ci		if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
858c2ecf20Sopenharmony_ci			return !!(ctrl & MXC_W1_CONTROL_RDST);
868c2ecf20Sopenharmony_ci	} while (ktime_before(ktime_get(), timeout));
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci	return 0;
898c2ecf20Sopenharmony_ci}
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_cistatic int mxc_w1_probe(struct platform_device *pdev)
928c2ecf20Sopenharmony_ci{
938c2ecf20Sopenharmony_ci	struct mxc_w1_device *mdev;
948c2ecf20Sopenharmony_ci	unsigned long clkrate;
958c2ecf20Sopenharmony_ci	unsigned int clkdiv;
968c2ecf20Sopenharmony_ci	int err;
978c2ecf20Sopenharmony_ci
988c2ecf20Sopenharmony_ci	mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
998c2ecf20Sopenharmony_ci			    GFP_KERNEL);
1008c2ecf20Sopenharmony_ci	if (!mdev)
1018c2ecf20Sopenharmony_ci		return -ENOMEM;
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ci	mdev->clk = devm_clk_get(&pdev->dev, NULL);
1048c2ecf20Sopenharmony_ci	if (IS_ERR(mdev->clk))
1058c2ecf20Sopenharmony_ci		return PTR_ERR(mdev->clk);
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ci	err = clk_prepare_enable(mdev->clk);
1088c2ecf20Sopenharmony_ci	if (err)
1098c2ecf20Sopenharmony_ci		return err;
1108c2ecf20Sopenharmony_ci
1118c2ecf20Sopenharmony_ci	clkrate = clk_get_rate(mdev->clk);
1128c2ecf20Sopenharmony_ci	if (clkrate < 10000000)
1138c2ecf20Sopenharmony_ci		dev_warn(&pdev->dev,
1148c2ecf20Sopenharmony_ci			 "Low clock frequency causes improper function\n");
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ci	clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
1178c2ecf20Sopenharmony_ci	clkrate /= clkdiv;
1188c2ecf20Sopenharmony_ci	if ((clkrate < 980000) || (clkrate > 1020000))
1198c2ecf20Sopenharmony_ci		dev_warn(&pdev->dev,
1208c2ecf20Sopenharmony_ci			 "Incorrect time base frequency %lu Hz\n", clkrate);
1218c2ecf20Sopenharmony_ci
1228c2ecf20Sopenharmony_ci	mdev->regs = devm_platform_ioremap_resource(pdev, 0);
1238c2ecf20Sopenharmony_ci	if (IS_ERR(mdev->regs)) {
1248c2ecf20Sopenharmony_ci		err = PTR_ERR(mdev->regs);
1258c2ecf20Sopenharmony_ci		goto out_disable_clk;
1268c2ecf20Sopenharmony_ci	}
1278c2ecf20Sopenharmony_ci
1288c2ecf20Sopenharmony_ci	/* Software reset 1-Wire module */
1298c2ecf20Sopenharmony_ci	writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
1308c2ecf20Sopenharmony_ci	writeb(0, mdev->regs + MXC_W1_RESET);
1318c2ecf20Sopenharmony_ci
1328c2ecf20Sopenharmony_ci	writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
1338c2ecf20Sopenharmony_ci
1348c2ecf20Sopenharmony_ci	mdev->bus_master.data = mdev;
1358c2ecf20Sopenharmony_ci	mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
1368c2ecf20Sopenharmony_ci	mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
1378c2ecf20Sopenharmony_ci
1388c2ecf20Sopenharmony_ci	platform_set_drvdata(pdev, mdev);
1398c2ecf20Sopenharmony_ci
1408c2ecf20Sopenharmony_ci	err = w1_add_master_device(&mdev->bus_master);
1418c2ecf20Sopenharmony_ci	if (err)
1428c2ecf20Sopenharmony_ci		goto out_disable_clk;
1438c2ecf20Sopenharmony_ci
1448c2ecf20Sopenharmony_ci	return 0;
1458c2ecf20Sopenharmony_ci
1468c2ecf20Sopenharmony_ciout_disable_clk:
1478c2ecf20Sopenharmony_ci	clk_disable_unprepare(mdev->clk);
1488c2ecf20Sopenharmony_ci	return err;
1498c2ecf20Sopenharmony_ci}
1508c2ecf20Sopenharmony_ci
1518c2ecf20Sopenharmony_ci/*
1528c2ecf20Sopenharmony_ci * disassociate the w1 device from the driver
1538c2ecf20Sopenharmony_ci */
1548c2ecf20Sopenharmony_cistatic int mxc_w1_remove(struct platform_device *pdev)
1558c2ecf20Sopenharmony_ci{
1568c2ecf20Sopenharmony_ci	struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
1578c2ecf20Sopenharmony_ci
1588c2ecf20Sopenharmony_ci	w1_remove_master_device(&mdev->bus_master);
1598c2ecf20Sopenharmony_ci
1608c2ecf20Sopenharmony_ci	clk_disable_unprepare(mdev->clk);
1618c2ecf20Sopenharmony_ci
1628c2ecf20Sopenharmony_ci	return 0;
1638c2ecf20Sopenharmony_ci}
1648c2ecf20Sopenharmony_ci
1658c2ecf20Sopenharmony_cistatic const struct of_device_id mxc_w1_dt_ids[] = {
1668c2ecf20Sopenharmony_ci	{ .compatible = "fsl,imx21-owire" },
1678c2ecf20Sopenharmony_ci	{ /* sentinel */ }
1688c2ecf20Sopenharmony_ci};
1698c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
1708c2ecf20Sopenharmony_ci
1718c2ecf20Sopenharmony_cistatic struct platform_driver mxc_w1_driver = {
1728c2ecf20Sopenharmony_ci	.driver = {
1738c2ecf20Sopenharmony_ci		.name = "mxc_w1",
1748c2ecf20Sopenharmony_ci		.of_match_table = mxc_w1_dt_ids,
1758c2ecf20Sopenharmony_ci	},
1768c2ecf20Sopenharmony_ci	.probe = mxc_w1_probe,
1778c2ecf20Sopenharmony_ci	.remove = mxc_w1_remove,
1788c2ecf20Sopenharmony_ci};
1798c2ecf20Sopenharmony_cimodule_platform_driver(mxc_w1_driver);
1808c2ecf20Sopenharmony_ci
1818c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL");
1828c2ecf20Sopenharmony_ciMODULE_AUTHOR("Freescale Semiconductors Inc");
1838c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Driver for One-Wire on MXC");
184