1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 5 6 */ 7 8#ifndef __SHARE_H__ 9#define __SHARE_H__ 10 11#include "via_modesetting.h" 12 13/* Define Bit Field */ 14#define BIT0 0x01 15#define BIT1 0x02 16#define BIT2 0x04 17#define BIT3 0x08 18#define BIT4 0x10 19#define BIT5 0x20 20#define BIT6 0x40 21#define BIT7 0x80 22 23/* Video Memory Size */ 24#define VIDEO_MEMORY_SIZE_16M 0x1000000 25 26/* 27 * Lengths of the VPIT structure arrays. 28 */ 29#define StdCR 0x19 30#define StdSR 0x04 31#define StdGR 0x09 32#define StdAR 0x14 33 34#define PatchCR 11 35 36/* Display path */ 37#define IGA1 1 38#define IGA2 2 39 40/* Define Color Depth */ 41#define MODE_8BPP 1 42#define MODE_16BPP 2 43#define MODE_32BPP 4 44 45#define GR20 0x20 46#define GR21 0x21 47#define GR22 0x22 48 49/* Sequencer Registers */ 50#define SR01 0x01 51#define SR10 0x10 52#define SR12 0x12 53#define SR15 0x15 54#define SR16 0x16 55#define SR17 0x17 56#define SR18 0x18 57#define SR1B 0x1B 58#define SR1A 0x1A 59#define SR1C 0x1C 60#define SR1D 0x1D 61#define SR1E 0x1E 62#define SR1F 0x1F 63#define SR20 0x20 64#define SR21 0x21 65#define SR22 0x22 66#define SR2A 0x2A 67#define SR2D 0x2D 68#define SR2E 0x2E 69 70#define SR30 0x30 71#define SR39 0x39 72#define SR3D 0x3D 73#define SR3E 0x3E 74#define SR3F 0x3F 75#define SR40 0x40 76#define SR43 0x43 77#define SR44 0x44 78#define SR45 0x45 79#define SR46 0x46 80#define SR47 0x47 81#define SR48 0x48 82#define SR49 0x49 83#define SR4A 0x4A 84#define SR4B 0x4B 85#define SR4C 0x4C 86#define SR52 0x52 87#define SR57 0x57 88#define SR58 0x58 89#define SR59 0x59 90#define SR5D 0x5D 91#define SR5E 0x5E 92#define SR65 0x65 93 94/* CRT Controller Registers */ 95#define CR00 0x00 96#define CR01 0x01 97#define CR02 0x02 98#define CR03 0x03 99#define CR04 0x04 100#define CR05 0x05 101#define CR06 0x06 102#define CR07 0x07 103#define CR08 0x08 104#define CR09 0x09 105#define CR0A 0x0A 106#define CR0B 0x0B 107#define CR0C 0x0C 108#define CR0D 0x0D 109#define CR0E 0x0E 110#define CR0F 0x0F 111#define CR10 0x10 112#define CR11 0x11 113#define CR12 0x12 114#define CR13 0x13 115#define CR14 0x14 116#define CR15 0x15 117#define CR16 0x16 118#define CR17 0x17 119#define CR18 0x18 120 121/* Extend CRT Controller Registers */ 122#define CR30 0x30 123#define CR31 0x31 124#define CR32 0x32 125#define CR33 0x33 126#define CR34 0x34 127#define CR35 0x35 128#define CR36 0x36 129#define CR37 0x37 130#define CR38 0x38 131#define CR39 0x39 132#define CR3A 0x3A 133#define CR3B 0x3B 134#define CR3C 0x3C 135#define CR3D 0x3D 136#define CR3E 0x3E 137#define CR3F 0x3F 138#define CR40 0x40 139#define CR41 0x41 140#define CR42 0x42 141#define CR43 0x43 142#define CR44 0x44 143#define CR45 0x45 144#define CR46 0x46 145#define CR47 0x47 146#define CR48 0x48 147#define CR49 0x49 148#define CR4A 0x4A 149#define CR4B 0x4B 150#define CR4C 0x4C 151#define CR4D 0x4D 152#define CR4E 0x4E 153#define CR4F 0x4F 154#define CR50 0x50 155#define CR51 0x51 156#define CR52 0x52 157#define CR53 0x53 158#define CR54 0x54 159#define CR55 0x55 160#define CR56 0x56 161#define CR57 0x57 162#define CR58 0x58 163#define CR59 0x59 164#define CR5A 0x5A 165#define CR5B 0x5B 166#define CR5C 0x5C 167#define CR5D 0x5D 168#define CR5E 0x5E 169#define CR5F 0x5F 170#define CR60 0x60 171#define CR61 0x61 172#define CR62 0x62 173#define CR63 0x63 174#define CR64 0x64 175#define CR65 0x65 176#define CR66 0x66 177#define CR67 0x67 178#define CR68 0x68 179#define CR69 0x69 180#define CR6A 0x6A 181#define CR6B 0x6B 182#define CR6C 0x6C 183#define CR6D 0x6D 184#define CR6E 0x6E 185#define CR6F 0x6F 186#define CR70 0x70 187#define CR71 0x71 188#define CR72 0x72 189#define CR73 0x73 190#define CR74 0x74 191#define CR75 0x75 192#define CR76 0x76 193#define CR77 0x77 194#define CR78 0x78 195#define CR79 0x79 196#define CR7A 0x7A 197#define CR7B 0x7B 198#define CR7C 0x7C 199#define CR7D 0x7D 200#define CR7E 0x7E 201#define CR7F 0x7F 202#define CR80 0x80 203#define CR81 0x81 204#define CR82 0x82 205#define CR83 0x83 206#define CR84 0x84 207#define CR85 0x85 208#define CR86 0x86 209#define CR87 0x87 210#define CR88 0x88 211#define CR89 0x89 212#define CR8A 0x8A 213#define CR8B 0x8B 214#define CR8C 0x8C 215#define CR8D 0x8D 216#define CR8E 0x8E 217#define CR8F 0x8F 218#define CR90 0x90 219#define CR91 0x91 220#define CR92 0x92 221#define CR93 0x93 222#define CR94 0x94 223#define CR95 0x95 224#define CR96 0x96 225#define CR97 0x97 226#define CR98 0x98 227#define CR99 0x99 228#define CR9A 0x9A 229#define CR9B 0x9B 230#define CR9C 0x9C 231#define CR9D 0x9D 232#define CR9E 0x9E 233#define CR9F 0x9F 234#define CRA0 0xA0 235#define CRA1 0xA1 236#define CRA2 0xA2 237#define CRA3 0xA3 238#define CRD2 0xD2 239#define CRD3 0xD3 240#define CRD4 0xD4 241 242/* LUT Table*/ 243#define LUT_DATA 0x3C9 /* DACDATA */ 244#define LUT_INDEX_READ 0x3C7 /* DACRX */ 245#define LUT_INDEX_WRITE 0x3C8 /* DACWX */ 246#define DACMASK 0x3C6 247 248/* Definition Device */ 249#define DEVICE_CRT 0x01 250#define DEVICE_DVI 0x03 251#define DEVICE_LCD 0x04 252 253/* Device output interface */ 254#define INTERFACE_NONE 0x00 255#define INTERFACE_ANALOG_RGB 0x01 256#define INTERFACE_DVP0 0x02 257#define INTERFACE_DVP1 0x03 258#define INTERFACE_DFP_HIGH 0x04 259#define INTERFACE_DFP_LOW 0x05 260#define INTERFACE_DFP 0x06 261#define INTERFACE_LVDS0 0x07 262#define INTERFACE_LVDS1 0x08 263#define INTERFACE_LVDS0LVDS1 0x09 264#define INTERFACE_TMDS 0x0A 265 266#define HW_LAYOUT_LCD_ONLY 0x01 267#define HW_LAYOUT_DVI_ONLY 0x02 268#define HW_LAYOUT_LCD_DVI 0x03 269#define HW_LAYOUT_LCD1_LCD2 0x04 270#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 271 272/* Definition CRTC Timing Index */ 273#define H_TOTAL_INDEX 0 274#define H_ADDR_INDEX 1 275#define H_BLANK_START_INDEX 2 276#define H_BLANK_END_INDEX 3 277#define H_SYNC_START_INDEX 4 278#define H_SYNC_END_INDEX 5 279#define V_TOTAL_INDEX 6 280#define V_ADDR_INDEX 7 281#define V_BLANK_START_INDEX 8 282#define V_BLANK_END_INDEX 9 283#define V_SYNC_START_INDEX 10 284#define V_SYNC_END_INDEX 11 285#define H_TOTAL_SHADOW_INDEX 12 286#define H_BLANK_END_SHADOW_INDEX 13 287#define V_TOTAL_SHADOW_INDEX 14 288#define V_ADDR_SHADOW_INDEX 15 289#define V_BLANK_SATRT_SHADOW_INDEX 16 290#define V_BLANK_END_SHADOW_INDEX 17 291#define V_SYNC_SATRT_SHADOW_INDEX 18 292#define V_SYNC_END_SHADOW_INDEX 19 293 294/* LCD display method 295*/ 296#define LCD_EXPANDSION 0x00 297#define LCD_CENTERING 0x01 298 299/* LCD mode 300*/ 301#define LCD_OPENLDI 0x00 302#define LCD_SPWG 0x01 303 304struct crt_mode_table { 305 int refresh_rate; 306 int h_sync_polarity; 307 int v_sync_polarity; 308 struct via_display_timing crtc; 309}; 310 311struct io_reg { 312 int port; 313 u8 index; 314 u8 mask; 315 u8 value; 316}; 317 318#endif /* __SHARE_H__ */ 319