1/* drivers/video/s1d13xxxfb.c 2 * 3 * (c) 2004 Simtec Electronics 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org> 5 * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com> 6 * 7 * Driver for Epson S1D13xxx series framebuffer chips 8 * 9 * Adapted from 10 * linux/drivers/video/skeletonfb.c 11 * linux/drivers/video/epson1355fb.c 12 * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson) 13 * 14 * TODO: - handle dual screen display (CRT and LCD at the same time). 15 * - check_var(), mode change, etc. 16 * - probably not SMP safe :) 17 * - support all bitblt operations on all cards 18 * 19 * This file is subject to the terms and conditions of the GNU General Public 20 * License. See the file COPYING in the main directory of this archive for 21 * more details. 22 */ 23 24#include <linux/module.h> 25#include <linux/platform_device.h> 26#include <linux/delay.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/mm.h> 30#include <linux/mman.h> 31#include <linux/fb.h> 32#include <linux/spinlock_types.h> 33#include <linux/spinlock.h> 34#include <linux/slab.h> 35#include <linux/io.h> 36 37#include <video/s1d13xxxfb.h> 38 39#define PFX "s1d13xxxfb: " 40#define BLIT "s1d13xxxfb_bitblt: " 41 42/* 43 * set this to enable debugging on general functions 44 */ 45#if 0 46#define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0) 47#else 48#define dbg(fmt, args...) do { } while (0) 49#endif 50 51/* 52 * set this to enable debugging on 2D acceleration 53 */ 54#if 0 55#define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0) 56#else 57#define dbg_blit(fmt, args...) do { } while (0) 58#endif 59 60/* 61 * we make sure only one bitblt operation is running 62 */ 63static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock); 64 65/* 66 * list of card production ids 67 */ 68static const int s1d13xxxfb_prod_ids[] = { 69 S1D13505_PROD_ID, 70 S1D13506_PROD_ID, 71 S1D13806_PROD_ID, 72}; 73 74/* 75 * List of card strings 76 */ 77static const char *s1d13xxxfb_prod_names[] = { 78 "S1D13505", 79 "S1D13506", 80 "S1D13806", 81}; 82 83/* 84 * here we define the default struct fb_fix_screeninfo 85 */ 86static const struct fb_fix_screeninfo s1d13xxxfb_fix = { 87 .id = S1D_FBID, 88 .type = FB_TYPE_PACKED_PIXELS, 89 .visual = FB_VISUAL_PSEUDOCOLOR, 90 .xpanstep = 0, 91 .ypanstep = 1, 92 .ywrapstep = 0, 93 .accel = FB_ACCEL_NONE, 94}; 95 96static inline u8 97s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno) 98{ 99 return readb(par->regs + regno); 100} 101 102static inline void 103s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value) 104{ 105 writeb(value, par->regs + regno); 106} 107 108static inline void 109s1d13xxxfb_runinit(struct s1d13xxxfb_par *par, 110 const struct s1d13xxxfb_regval *initregs, 111 const unsigned int size) 112{ 113 int i; 114 115 for (i = 0; i < size; i++) { 116 if ((initregs[i].addr == S1DREG_DELAYOFF) || 117 (initregs[i].addr == S1DREG_DELAYON)) 118 mdelay((int)initregs[i].value); 119 else { 120 s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value); 121 } 122 } 123 124 /* make sure the hardware can cope with us */ 125 mdelay(1); 126} 127 128static inline void 129lcd_enable(struct s1d13xxxfb_par *par, int enable) 130{ 131 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 132 133 if (enable) 134 mode |= 0x01; 135 else 136 mode &= ~0x01; 137 138 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); 139} 140 141static inline void 142crt_enable(struct s1d13xxxfb_par *par, int enable) 143{ 144 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 145 146 if (enable) 147 mode |= 0x02; 148 else 149 mode &= ~0x02; 150 151 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode); 152} 153 154 155/************************************************************* 156 framebuffer control functions 157 *************************************************************/ 158static inline void 159s1d13xxxfb_setup_pseudocolour(struct fb_info *info) 160{ 161 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 162 163 info->var.red.length = 4; 164 info->var.green.length = 4; 165 info->var.blue.length = 4; 166} 167 168static inline void 169s1d13xxxfb_setup_truecolour(struct fb_info *info) 170{ 171 info->fix.visual = FB_VISUAL_TRUECOLOR; 172 info->var.bits_per_pixel = 16; 173 174 info->var.red.length = 5; 175 info->var.red.offset = 11; 176 177 info->var.green.length = 6; 178 info->var.green.offset = 5; 179 180 info->var.blue.length = 5; 181 info->var.blue.offset = 0; 182} 183 184/** 185 * s1d13xxxfb_set_par - Alters the hardware state. 186 * @info: frame buffer structure 187 * 188 * Using the fb_var_screeninfo in fb_info we set the depth of the 189 * framebuffer. This function alters the par AND the 190 * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in 191 * fb_info since we are using that data. This means we depend on the 192 * data in var inside fb_info to be supported by the hardware. 193 * xxxfb_check_var is always called before xxxfb_set_par to ensure this. 194 * 195 * XXX TODO: write proper s1d13xxxfb_check_var(), without which that 196 * function is quite useless. 197 */ 198static int 199s1d13xxxfb_set_par(struct fb_info *info) 200{ 201 struct s1d13xxxfb_par *s1dfb = info->par; 202 unsigned int val; 203 204 dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel); 205 206 if ((s1dfb->display & 0x01)) /* LCD */ 207 val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */ 208 else /* CRT */ 209 val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */ 210 211 val &= ~0x07; 212 213 switch (info->var.bits_per_pixel) { 214 case 4: 215 dbg("pseudo colour 4\n"); 216 s1d13xxxfb_setup_pseudocolour(info); 217 val |= 2; 218 break; 219 case 8: 220 dbg("pseudo colour 8\n"); 221 s1d13xxxfb_setup_pseudocolour(info); 222 val |= 3; 223 break; 224 case 16: 225 dbg("true colour\n"); 226 s1d13xxxfb_setup_truecolour(info); 227 val |= 5; 228 break; 229 230 default: 231 dbg("bpp not supported!\n"); 232 return -EINVAL; 233 } 234 235 dbg("writing %02x to display mode register\n", val); 236 237 if ((s1dfb->display & 0x01)) /* LCD */ 238 s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val); 239 else /* CRT */ 240 s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val); 241 242 info->fix.line_length = info->var.xres * info->var.bits_per_pixel; 243 info->fix.line_length /= 8; 244 245 dbg("setting line_length to %d\n", info->fix.line_length); 246 247 dbg("done setup\n"); 248 249 return 0; 250} 251 252/** 253 * s1d13xxxfb_setcolreg - sets a color register. 254 * @regno: Which register in the CLUT we are programming 255 * @red: The red value which can be up to 16 bits wide 256 * @green: The green value which can be up to 16 bits wide 257 * @blue: The blue value which can be up to 16 bits wide. 258 * @transp: If supported the alpha value which can be up to 16 bits wide. 259 * @info: frame buffer info structure 260 * 261 * Returns negative errno on error, or zero on success. 262 */ 263static int 264s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 265 u_int transp, struct fb_info *info) 266{ 267 struct s1d13xxxfb_par *s1dfb = info->par; 268 unsigned int pseudo_val; 269 270 if (regno >= S1D_PALETTE_SIZE) 271 return -EINVAL; 272 273 dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n", 274 regno, red, green, blue, transp); 275 276 if (info->var.grayscale) 277 red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16; 278 279 switch (info->fix.visual) { 280 case FB_VISUAL_TRUECOLOR: 281 if (regno >= 16) 282 return -EINVAL; 283 284 /* deal with creating pseudo-palette entries */ 285 286 pseudo_val = (red >> 11) << info->var.red.offset; 287 pseudo_val |= (green >> 10) << info->var.green.offset; 288 pseudo_val |= (blue >> 11) << info->var.blue.offset; 289 290 dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n", 291 regno, pseudo_val); 292 293 ((u32 *)info->pseudo_palette)[regno] = pseudo_val; 294 295 break; 296 case FB_VISUAL_PSEUDOCOLOR: 297 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno); 298 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red); 299 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green); 300 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue); 301 302 break; 303 default: 304 return -ENOSYS; 305 } 306 307 dbg("s1d13xxxfb_setcolreg: done\n"); 308 309 return 0; 310} 311 312/** 313 * s1d13xxxfb_blank - blanks the display. 314 * @blank_mode: the blank mode we want. 315 * @info: frame buffer structure that represents a single frame buffer 316 * 317 * Blank the screen if blank_mode != 0, else unblank. Return 0 if 318 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a 319 * video mode which doesn't support it. Implements VESA suspend 320 * and powerdown modes on hardware that supports disabling hsync/vsync: 321 * blank_mode == 2: suspend vsync 322 * blank_mode == 3: suspend hsync 323 * blank_mode == 4: powerdown 324 * 325 * Returns negative errno on error, or zero on success. 326 */ 327static int 328s1d13xxxfb_blank(int blank_mode, struct fb_info *info) 329{ 330 struct s1d13xxxfb_par *par = info->par; 331 332 dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info); 333 334 switch (blank_mode) { 335 case FB_BLANK_UNBLANK: 336 case FB_BLANK_NORMAL: 337 if ((par->display & 0x01) != 0) 338 lcd_enable(par, 1); 339 if ((par->display & 0x02) != 0) 340 crt_enable(par, 1); 341 break; 342 case FB_BLANK_VSYNC_SUSPEND: 343 case FB_BLANK_HSYNC_SUSPEND: 344 break; 345 case FB_BLANK_POWERDOWN: 346 lcd_enable(par, 0); 347 crt_enable(par, 0); 348 break; 349 default: 350 return -EINVAL; 351 } 352 353 /* let fbcon do a soft blank for us */ 354 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0); 355} 356 357/** 358 * s1d13xxxfb_pan_display - Pans the display. 359 * @var: frame buffer variable screen structure 360 * @info: frame buffer structure that represents a single frame buffer 361 * 362 * Pan (or wrap, depending on the `vmode' field) the display using the 363 * `yoffset' field of the `var' structure (`xoffset' not yet supported). 364 * If the values don't fit, return -EINVAL. 365 * 366 * Returns negative errno on error, or zero on success. 367 */ 368static int 369s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 370{ 371 struct s1d13xxxfb_par *par = info->par; 372 u32 start; 373 374 if (var->xoffset != 0) /* not yet ... */ 375 return -EINVAL; 376 377 if (var->yoffset + info->var.yres > info->var.yres_virtual) 378 return -EINVAL; 379 380 start = (info->fix.line_length >> 1) * var->yoffset; 381 382 if ((par->display & 0x01)) { 383 /* LCD */ 384 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff)); 385 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff)); 386 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f)); 387 } else { 388 /* CRT */ 389 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff)); 390 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff)); 391 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f)); 392 } 393 394 return 0; 395} 396 397/************************************************************ 398 functions to handle bitblt acceleration 399 ************************************************************/ 400 401/** 402 * bltbit_wait_bitclear - waits for change in register value 403 * @info : frambuffer structure 404 * @bit : value currently in register 405 * @timeout : ... 406 * 407 * waits until value changes FROM bit 408 * 409 */ 410static u8 411bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout) 412{ 413 while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) { 414 udelay(10); 415 if (!--timeout) { 416 dbg_blit("wait_bitclear timeout\n"); 417 break; 418 } 419 } 420 421 return timeout; 422} 423 424/* 425 * s1d13xxxfb_bitblt_copyarea - accelerated copyarea function 426 * @info : framebuffer structure 427 * @area : fb_copyarea structure 428 * 429 * supports (atleast) S1D13506 430 * 431 */ 432static void 433s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area) 434{ 435 u32 dst, src; 436 u32 stride; 437 u16 reverse = 0; 438 u16 sx = area->sx, sy = area->sy; 439 u16 dx = area->dx, dy = area->dy; 440 u16 width = area->width, height = area->height; 441 u16 bpp; 442 443 spin_lock(&s1d13xxxfb_bitblt_lock); 444 445 /* bytes per xres line */ 446 bpp = (info->var.bits_per_pixel >> 3); 447 stride = bpp * info->var.xres; 448 449 /* reverse, calculate the last pixel in rectangle */ 450 if ((dy > sy) || ((dy == sy) && (dx >= sx))) { 451 dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1))); 452 src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1))); 453 reverse = 1; 454 /* not reverse, calculate the first pixel in rectangle */ 455 } else { /* (y * xres) + (bpp * x) */ 456 dst = (dy * stride) + (bpp * dx); 457 src = (sy * stride) + (bpp * sx); 458 } 459 460 /* set source address */ 461 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff)); 462 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff); 463 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff); 464 465 /* set destination address */ 466 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff)); 467 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff); 468 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff); 469 470 /* program height and width */ 471 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1); 472 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8)); 473 474 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1); 475 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8)); 476 477 /* negative direction ROP */ 478 if (reverse == 1) { 479 dbg_blit("(copyarea) negative rop\n"); 480 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03); 481 } else /* positive direction ROP */ { 482 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02); 483 dbg_blit("(copyarea) positive rop\n"); 484 } 485 486 /* set for rectangel mode and not linear */ 487 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0); 488 489 /* setup the bpp 1 = 16bpp, 0 = 8bpp*/ 490 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1)); 491 492 /* set words per xres */ 493 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff); 494 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9)); 495 496 dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy); 497 dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy); 498 dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1); 499 dbg_blit("(copyarea) stride=%d\n", stride); 500 dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1), 501 (stride >> 1) & 0xff, stride >> 9); 502 503 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c); 504 505 /* initialize the engine */ 506 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80); 507 508 /* wait to complete */ 509 bltbit_wait_bitclear(info, 0x80, 8000); 510 511 spin_unlock(&s1d13xxxfb_bitblt_lock); 512} 513 514/** 515 * 516 * s1d13xxxfb_bitblt_solidfill - accelerated solidfill function 517 * @info : framebuffer structure 518 * @rect : fb_fillrect structure 519 * 520 * supports (atleast 13506) 521 * 522 **/ 523static void 524s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect) 525{ 526 u32 screen_stride, dest; 527 u32 fg; 528 u16 bpp = (info->var.bits_per_pixel >> 3); 529 530 /* grab spinlock */ 531 spin_lock(&s1d13xxxfb_bitblt_lock); 532 533 /* bytes per x width */ 534 screen_stride = (bpp * info->var.xres); 535 536 /* bytes to starting point */ 537 dest = ((rect->dy * screen_stride) + (bpp * rect->dx)); 538 539 dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n" 540 "(solidfill) : rect_width=%d, rect_height=%d\n", 541 rect->dx, rect->dy, screen_stride, dest, 542 rect->width - 1, rect->height - 1); 543 544 dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n", 545 info->var.xres, info->var.yres, 546 info->var.bits_per_pixel); 547 dbg_blit("(solidfill) : rop=%d\n", rect->rop); 548 549 /* We split the destination into the three registers */ 550 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff)); 551 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff)); 552 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff)); 553 554 /* give information regarding rectangel width */ 555 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1); 556 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8)); 557 558 /* give information regarding rectangel height */ 559 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1); 560 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8)); 561 562 if (info->fix.visual == FB_VISUAL_TRUECOLOR || 563 info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 564 fg = ((u32 *)info->pseudo_palette)[rect->color]; 565 dbg_blit("(solidfill) truecolor/directcolor\n"); 566 dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg); 567 } else { 568 fg = rect->color; 569 dbg_blit("(solidfill) color = %d\n", rect->color); 570 } 571 572 /* set foreground color */ 573 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff)); 574 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff); 575 576 /* set rectangual region of memory (rectangle and not linear) */ 577 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0); 578 579 /* set operation mode SOLID_FILL */ 580 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL); 581 582 /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */ 583 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4)); 584 585 /* set the memory offset for the bblt in word sizes */ 586 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff); 587 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9)); 588 589 /* and away we go.... */ 590 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80); 591 592 /* wait until its done */ 593 bltbit_wait_bitclear(info, 0x80, 8000); 594 595 /* let others play */ 596 spin_unlock(&s1d13xxxfb_bitblt_lock); 597} 598 599/* framebuffer information structures */ 600static struct fb_ops s1d13xxxfb_fbops = { 601 .owner = THIS_MODULE, 602 .fb_set_par = s1d13xxxfb_set_par, 603 .fb_setcolreg = s1d13xxxfb_setcolreg, 604 .fb_blank = s1d13xxxfb_blank, 605 606 .fb_pan_display = s1d13xxxfb_pan_display, 607 608 /* gets replaced at chip detection time */ 609 .fb_fillrect = cfb_fillrect, 610 .fb_copyarea = cfb_copyarea, 611 .fb_imageblit = cfb_imageblit, 612}; 613 614static int s1d13xxxfb_width_tab[2][4] = { 615 {4, 8, 16, -1}, 616 {9, 12, 18, -1}, 617}; 618 619/** 620 * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to 621 * hardware setup. 622 * @info: frame buffer structure 623 * 624 * We setup the framebuffer structures according to the current 625 * hardware setup. On some machines, the BIOS will have filled 626 * the chip registers with such info, on others, these values will 627 * have been written in some init procedure. In any case, the 628 * software values needs to match the hardware ones. This is what 629 * this function ensures. 630 * 631 * Note: some of the hardcoded values here might need some love to 632 * work on various chips, and might need to no longer be hardcoded. 633 */ 634static void s1d13xxxfb_fetch_hw_state(struct fb_info *info) 635{ 636 struct fb_var_screeninfo *var = &info->var; 637 struct fb_fix_screeninfo *fix = &info->fix; 638 struct s1d13xxxfb_par *par = info->par; 639 u8 panel, display; 640 u16 offset; 641 u32 xres, yres; 642 u32 xres_virtual, yres_virtual; 643 int bpp, lcd_bpp; 644 int is_color, is_dual, is_tft; 645 int lcd_enabled, crt_enabled; 646 647 fix->type = FB_TYPE_PACKED_PIXELS; 648 649 /* general info */ 650 par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE); 651 crt_enabled = (par->display & 0x02) != 0; 652 lcd_enabled = (par->display & 0x01) != 0; 653 654 if (lcd_enabled && crt_enabled) 655 printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n"); 656 657 if (lcd_enabled) 658 display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE); 659 else /* CRT */ 660 display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE); 661 662 bpp = display & 0x07; 663 664 switch (bpp) { 665 case 2: /* 4 bpp */ 666 case 3: /* 8 bpp */ 667 var->bits_per_pixel = 8; 668 var->red.offset = var->green.offset = var->blue.offset = 0; 669 var->red.length = var->green.length = var->blue.length = 8; 670 break; 671 case 5: /* 16 bpp */ 672 s1d13xxxfb_setup_truecolour(info); 673 break; 674 default: 675 dbg("bpp: %i\n", bpp); 676 } 677 fb_alloc_cmap(&info->cmap, 256, 0); 678 679 /* LCD info */ 680 panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE); 681 is_color = (panel & 0x04) != 0; 682 is_dual = (panel & 0x02) != 0; 683 is_tft = (panel & 0x01) != 0; 684 lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3]; 685 686 if (lcd_enabled) { 687 xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8; 688 yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) + 689 ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1); 690 691 offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) + 692 ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8)); 693 } else { /* crt */ 694 xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8; 695 yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) + 696 ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1); 697 698 offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) + 699 ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8)); 700 } 701 xres_virtual = offset * 16 / var->bits_per_pixel; 702 yres_virtual = fix->smem_len / (offset * 2); 703 704 var->xres = xres; 705 var->yres = yres; 706 var->xres_virtual = xres_virtual; 707 var->yres_virtual = yres_virtual; 708 var->xoffset = var->yoffset = 0; 709 710 fix->line_length = offset * 2; 711 712 var->grayscale = !is_color; 713 714 var->activate = FB_ACTIVATE_NOW; 715 716 dbg(PFX "bpp=%d, lcd_bpp=%d, " 717 "crt_enabled=%d, lcd_enabled=%d\n", 718 var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled); 719 dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d " 720 "is_color=%d, is_dual=%d, is_tft=%d\n", 721 xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft); 722} 723 724static void __s1d13xxxfb_remove(struct platform_device *pdev) 725{ 726 struct fb_info *info = platform_get_drvdata(pdev); 727 struct s1d13xxxfb_par *par = NULL; 728 729 if (info) { 730 par = info->par; 731 if (par && par->regs) { 732 /* disable output & enable powersave */ 733 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00); 734 s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11); 735 iounmap(par->regs); 736 } 737 738 fb_dealloc_cmap(&info->cmap); 739 740 if (info->screen_base) 741 iounmap(info->screen_base); 742 743 framebuffer_release(info); 744 } 745 746 release_mem_region(pdev->resource[0].start, 747 resource_size(&pdev->resource[0])); 748 release_mem_region(pdev->resource[1].start, 749 resource_size(&pdev->resource[1])); 750} 751 752static int s1d13xxxfb_remove(struct platform_device *pdev) 753{ 754 struct fb_info *info = platform_get_drvdata(pdev); 755 756 unregister_framebuffer(info); 757 __s1d13xxxfb_remove(pdev); 758 return 0; 759} 760 761static int s1d13xxxfb_probe(struct platform_device *pdev) 762{ 763 struct s1d13xxxfb_par *default_par; 764 struct fb_info *info; 765 struct s1d13xxxfb_pdata *pdata = NULL; 766 int ret = 0; 767 int i; 768 u8 revision, prod_id; 769 770 dbg("probe called: device is %p\n", pdev); 771 772 printk(KERN_INFO "Epson S1D13XXX FB Driver\n"); 773 774 /* enable platform-dependent hardware glue, if any */ 775 if (dev_get_platdata(&pdev->dev)) 776 pdata = dev_get_platdata(&pdev->dev); 777 778 if (pdata && pdata->platform_init_video) 779 pdata->platform_init_video(); 780 781 if (pdev->num_resources != 2) { 782 dev_err(&pdev->dev, "invalid num_resources: %i\n", 783 pdev->num_resources); 784 ret = -ENODEV; 785 goto bail; 786 } 787 788 /* resource[0] is VRAM, resource[1] is registers */ 789 if (pdev->resource[0].flags != IORESOURCE_MEM 790 || pdev->resource[1].flags != IORESOURCE_MEM) { 791 dev_err(&pdev->dev, "invalid resource type\n"); 792 ret = -ENODEV; 793 goto bail; 794 } 795 796 if (!request_mem_region(pdev->resource[0].start, 797 resource_size(&pdev->resource[0]), "s1d13xxxfb mem")) { 798 dev_dbg(&pdev->dev, "request_mem_region failed\n"); 799 ret = -EBUSY; 800 goto bail; 801 } 802 803 if (!request_mem_region(pdev->resource[1].start, 804 resource_size(&pdev->resource[1]), "s1d13xxxfb regs")) { 805 dev_dbg(&pdev->dev, "request_mem_region failed\n"); 806 ret = -EBUSY; 807 goto bail; 808 } 809 810 info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev); 811 if (!info) { 812 ret = -ENOMEM; 813 goto bail; 814 } 815 816 platform_set_drvdata(pdev, info); 817 default_par = info->par; 818 default_par->regs = ioremap(pdev->resource[1].start, 819 resource_size(&pdev->resource[1])); 820 if (!default_par->regs) { 821 printk(KERN_ERR PFX "unable to map registers\n"); 822 ret = -ENOMEM; 823 goto bail; 824 } 825 info->pseudo_palette = default_par->pseudo_palette; 826 827 info->screen_base = ioremap(pdev->resource[0].start, 828 resource_size(&pdev->resource[0])); 829 830 if (!info->screen_base) { 831 printk(KERN_ERR PFX "unable to map framebuffer\n"); 832 ret = -ENOMEM; 833 goto bail; 834 } 835 836 /* production id is top 6 bits */ 837 prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2; 838 /* revision id is lower 2 bits */ 839 revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3; 840 ret = -ENODEV; 841 842 for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) { 843 if (prod_id == s1d13xxxfb_prod_ids[i]) { 844 /* looks like we got it in our list */ 845 default_par->prod_id = prod_id; 846 default_par->revision = revision; 847 ret = 0; 848 break; 849 } 850 } 851 852 if (!ret) { 853 printk(KERN_INFO PFX "chip production id %i = %s\n", 854 prod_id, s1d13xxxfb_prod_names[i]); 855 printk(KERN_INFO PFX "chip revision %i\n", revision); 856 } else { 857 printk(KERN_INFO PFX 858 "unknown chip production id %i, revision %i\n", 859 prod_id, revision); 860 printk(KERN_INFO PFX "please contact maintainer\n"); 861 goto bail; 862 } 863 864 info->fix = s1d13xxxfb_fix; 865 info->fix.mmio_start = pdev->resource[1].start; 866 info->fix.mmio_len = resource_size(&pdev->resource[1]); 867 info->fix.smem_start = pdev->resource[0].start; 868 info->fix.smem_len = resource_size(&pdev->resource[0]); 869 870 printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n", 871 default_par->regs, info->fix.smem_len / 1024, info->screen_base); 872 873 info->par = default_par; 874 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 875 info->fbops = &s1d13xxxfb_fbops; 876 877 switch(prod_id) { 878 case S1D13506_PROD_ID: /* activate acceleration */ 879 s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill; 880 s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea; 881 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN | 882 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA; 883 break; 884 default: 885 break; 886 } 887 888 /* perform "manual" chip initialization, if needed */ 889 if (pdata && pdata->initregs) 890 s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize); 891 892 s1d13xxxfb_fetch_hw_state(info); 893 894 if (register_framebuffer(info) < 0) { 895 ret = -EINVAL; 896 goto bail; 897 } 898 899 fb_info(info, "%s frame buffer device\n", info->fix.id); 900 901 return 0; 902 903bail: 904 __s1d13xxxfb_remove(pdev); 905 return ret; 906 907} 908 909#ifdef CONFIG_PM 910static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state) 911{ 912 struct fb_info *info = platform_get_drvdata(dev); 913 struct s1d13xxxfb_par *s1dfb = info->par; 914 struct s1d13xxxfb_pdata *pdata = NULL; 915 916 /* disable display */ 917 lcd_enable(s1dfb, 0); 918 crt_enable(s1dfb, 0); 919 920 if (dev_get_platdata(&dev->dev)) 921 pdata = dev_get_platdata(&dev->dev); 922 923#if 0 924 if (!s1dfb->disp_save) 925 s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL); 926 927 if (!s1dfb->disp_save) { 928 printk(KERN_ERR PFX "no memory to save screen\n"); 929 return -ENOMEM; 930 } 931 932 memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len); 933#else 934 s1dfb->disp_save = NULL; 935#endif 936 937 if (!s1dfb->regs_save) 938 s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL); 939 940 if (!s1dfb->regs_save) { 941 printk(KERN_ERR PFX "no memory to save registers"); 942 return -ENOMEM; 943 } 944 945 /* backup all registers */ 946 memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len); 947 948 /* now activate power save mode */ 949 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11); 950 951 if (pdata && pdata->platform_suspend_video) 952 return pdata->platform_suspend_video(); 953 else 954 return 0; 955} 956 957static int s1d13xxxfb_resume(struct platform_device *dev) 958{ 959 struct fb_info *info = platform_get_drvdata(dev); 960 struct s1d13xxxfb_par *s1dfb = info->par; 961 struct s1d13xxxfb_pdata *pdata = NULL; 962 963 /* awaken the chip */ 964 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10); 965 966 /* do not let go until SDRAM "wakes up" */ 967 while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01)) 968 udelay(10); 969 970 if (dev_get_platdata(&dev->dev)) 971 pdata = dev_get_platdata(&dev->dev); 972 973 if (s1dfb->regs_save) { 974 /* will write RO regs, *should* get away with it :) */ 975 memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len); 976 kfree(s1dfb->regs_save); 977 } 978 979 if (s1dfb->disp_save) { 980 memcpy_toio(info->screen_base, s1dfb->disp_save, 981 info->fix.smem_len); 982 kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */ 983 } 984 985 if ((s1dfb->display & 0x01) != 0) 986 lcd_enable(s1dfb, 1); 987 if ((s1dfb->display & 0x02) != 0) 988 crt_enable(s1dfb, 1); 989 990 if (pdata && pdata->platform_resume_video) 991 return pdata->platform_resume_video(); 992 else 993 return 0; 994} 995#endif /* CONFIG_PM */ 996 997static struct platform_driver s1d13xxxfb_driver = { 998 .probe = s1d13xxxfb_probe, 999 .remove = s1d13xxxfb_remove, 1000#ifdef CONFIG_PM 1001 .suspend = s1d13xxxfb_suspend, 1002 .resume = s1d13xxxfb_resume, 1003#endif 1004 .driver = { 1005 .name = S1D_DEVICENAME, 1006 }, 1007}; 1008 1009 1010static int __init 1011s1d13xxxfb_init(void) 1012{ 1013 1014#ifndef MODULE 1015 if (fb_get_options("s1d13xxxfb", NULL)) 1016 return -ENODEV; 1017#endif 1018 1019 return platform_driver_register(&s1d13xxxfb_driver); 1020} 1021 1022 1023static void __exit 1024s1d13xxxfb_exit(void) 1025{ 1026 platform_driver_unregister(&s1d13xxxfb_driver); 1027} 1028 1029module_init(s1d13xxxfb_init); 1030module_exit(s1d13xxxfb_exit); 1031 1032 1033MODULE_LICENSE("GPL"); 1034MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices"); 1035MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>"); 1036