1/* 2 * Freescale i.MX Frame Buffer device driver 3 * 4 * Copyright (C) 2004 Sascha Hauer, Pengutronix 5 * Based on acornfb.c Copyright (C) Russell King. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 * 11 * Please direct your questions and comments on this driver to the following 12 * email address: 13 * 14 * linux-arm-kernel@lists.arm.linux.org.uk 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/errno.h> 20#include <linux/string.h> 21#include <linux/interrupt.h> 22#include <linux/slab.h> 23#include <linux/mm.h> 24#include <linux/fb.h> 25#include <linux/delay.h> 26#include <linux/init.h> 27#include <linux/ioport.h> 28#include <linux/cpufreq.h> 29#include <linux/clk.h> 30#include <linux/platform_device.h> 31#include <linux/dma-mapping.h> 32#include <linux/io.h> 33#include <linux/lcd.h> 34#include <linux/math64.h> 35#include <linux/of.h> 36#include <linux/of_device.h> 37 38#include <linux/regulator/consumer.h> 39 40#include <video/of_display_timing.h> 41#include <video/of_videomode.h> 42#include <video/videomode.h> 43 44#include <linux/platform_data/video-imxfb.h> 45 46/* 47 * Complain if VAR is out of range. 48 */ 49#define DEBUG_VAR 1 50 51#define DRIVER_NAME "imx-fb" 52 53#define LCDC_SSA 0x00 54 55#define LCDC_SIZE 0x04 56#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) 57 58#define YMAX_MASK_IMX1 0x1ff 59#define YMAX_MASK_IMX21 0x3ff 60 61#define LCDC_VPW 0x08 62#define VPW_VPW(x) ((x) & 0x3ff) 63 64#define LCDC_CPOS 0x0C 65#define CPOS_CC1 (1<<31) 66#define CPOS_CC0 (1<<30) 67#define CPOS_OP (1<<28) 68#define CPOS_CXP(x) (((x) & 3ff) << 16) 69 70#define LCDC_LCWHB 0x10 71#define LCWHB_BK_EN (1<<31) 72#define LCWHB_CW(w) (((w) & 0x1f) << 24) 73#define LCWHB_CH(h) (((h) & 0x1f) << 16) 74#define LCWHB_BD(x) ((x) & 0xff) 75 76#define LCDC_LCHCC 0x14 77 78#define LCDC_PCR 0x18 79 80#define LCDC_HCR 0x1C 81#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) 82#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) 83#define HCR_H_WAIT_2(x) ((x) & 0xff) 84 85#define LCDC_VCR 0x20 86#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) 87#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) 88#define VCR_V_WAIT_2(x) ((x) & 0xff) 89 90#define LCDC_POS 0x24 91#define POS_POS(x) ((x) & 1f) 92 93#define LCDC_LSCR1 0x28 94/* bit fields in imxfb.h */ 95 96#define LCDC_PWMR 0x2C 97/* bit fields in imxfb.h */ 98 99#define LCDC_DMACR 0x30 100/* bit fields in imxfb.h */ 101 102#define LCDC_RMCR 0x34 103 104#define RMCR_LCDC_EN_MX1 (1<<1) 105 106#define RMCR_SELF_REF (1<<0) 107 108#define LCDC_LCDICR 0x38 109#define LCDICR_INT_SYN (1<<2) 110#define LCDICR_INT_CON (1) 111 112#define LCDC_LCDISR 0x40 113#define LCDISR_UDR_ERR (1<<3) 114#define LCDISR_ERR_RES (1<<2) 115#define LCDISR_EOF (1<<1) 116#define LCDISR_BOF (1<<0) 117 118#define IMXFB_LSCR1_DEFAULT 0x00120300 119 120#define LCDC_LAUSCR 0x80 121#define LAUSCR_AUS_MODE (1<<31) 122 123/* Used fb-mode. Can be set on kernel command line, therefore file-static. */ 124static const char *fb_mode; 125 126/* 127 * These are the bitfields for each 128 * display depth that we support. 129 */ 130struct imxfb_rgb { 131 struct fb_bitfield red; 132 struct fb_bitfield green; 133 struct fb_bitfield blue; 134 struct fb_bitfield transp; 135}; 136 137enum imxfb_type { 138 IMX1_FB, 139 IMX21_FB, 140}; 141 142struct imxfb_info { 143 struct platform_device *pdev; 144 void __iomem *regs; 145 struct clk *clk_ipg; 146 struct clk *clk_ahb; 147 struct clk *clk_per; 148 enum imxfb_type devtype; 149 bool enabled; 150 151 /* 152 * These are the addresses we mapped 153 * the framebuffer memory region to. 154 */ 155 dma_addr_t map_dma; 156 u_int map_size; 157 158 u_int palette_size; 159 160 dma_addr_t dbar1; 161 dma_addr_t dbar2; 162 163 u_int pcr; 164 u_int lauscr; 165 u_int pwmr; 166 u_int lscr1; 167 u_int dmacr; 168 bool cmap_inverse; 169 bool cmap_static; 170 171 struct imx_fb_videomode *mode; 172 int num_modes; 173 174 struct regulator *lcd_pwr; 175 int lcd_pwr_enabled; 176}; 177 178static const struct platform_device_id imxfb_devtype[] = { 179 { 180 .name = "imx1-fb", 181 .driver_data = IMX1_FB, 182 }, { 183 .name = "imx21-fb", 184 .driver_data = IMX21_FB, 185 }, { 186 /* sentinel */ 187 } 188}; 189MODULE_DEVICE_TABLE(platform, imxfb_devtype); 190 191static const struct of_device_id imxfb_of_dev_id[] = { 192 { 193 .compatible = "fsl,imx1-fb", 194 .data = &imxfb_devtype[IMX1_FB], 195 }, { 196 .compatible = "fsl,imx21-fb", 197 .data = &imxfb_devtype[IMX21_FB], 198 }, { 199 /* sentinel */ 200 } 201}; 202MODULE_DEVICE_TABLE(of, imxfb_of_dev_id); 203 204static inline int is_imx1_fb(struct imxfb_info *fbi) 205{ 206 return fbi->devtype == IMX1_FB; 207} 208 209#define IMX_NAME "IMX" 210 211/* 212 * Minimum X and Y resolutions 213 */ 214#define MIN_XRES 64 215#define MIN_YRES 64 216 217/* Actually this really is 18bit support, the lowest 2 bits of each colour 218 * are unused in hardware. We claim to have 24bit support to make software 219 * like X work, which does not support 18bit. 220 */ 221static struct imxfb_rgb def_rgb_18 = { 222 .red = {.offset = 16, .length = 8,}, 223 .green = {.offset = 8, .length = 8,}, 224 .blue = {.offset = 0, .length = 8,}, 225 .transp = {.offset = 0, .length = 0,}, 226}; 227 228static struct imxfb_rgb def_rgb_16_tft = { 229 .red = {.offset = 11, .length = 5,}, 230 .green = {.offset = 5, .length = 6,}, 231 .blue = {.offset = 0, .length = 5,}, 232 .transp = {.offset = 0, .length = 0,}, 233}; 234 235static struct imxfb_rgb def_rgb_16_stn = { 236 .red = {.offset = 8, .length = 4,}, 237 .green = {.offset = 4, .length = 4,}, 238 .blue = {.offset = 0, .length = 4,}, 239 .transp = {.offset = 0, .length = 0,}, 240}; 241 242static struct imxfb_rgb def_rgb_8 = { 243 .red = {.offset = 0, .length = 8,}, 244 .green = {.offset = 0, .length = 8,}, 245 .blue = {.offset = 0, .length = 8,}, 246 .transp = {.offset = 0, .length = 0,}, 247}; 248 249static int imxfb_activate_var(struct fb_var_screeninfo *var, 250 struct fb_info *info); 251 252static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 253{ 254 chan &= 0xffff; 255 chan >>= 16 - bf->length; 256 return chan << bf->offset; 257} 258 259static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 260 u_int trans, struct fb_info *info) 261{ 262 struct imxfb_info *fbi = info->par; 263 u_int val, ret = 1; 264 265#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) 266 if (regno < fbi->palette_size) { 267 val = (CNVT_TOHW(red, 4) << 8) | 268 (CNVT_TOHW(green,4) << 4) | 269 CNVT_TOHW(blue, 4); 270 271 writel(val, fbi->regs + 0x800 + (regno << 2)); 272 ret = 0; 273 } 274 return ret; 275} 276 277static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 278 u_int trans, struct fb_info *info) 279{ 280 struct imxfb_info *fbi = info->par; 281 unsigned int val; 282 int ret = 1; 283 284 /* 285 * If inverse mode was selected, invert all the colours 286 * rather than the register number. The register number 287 * is what you poke into the framebuffer to produce the 288 * colour you requested. 289 */ 290 if (fbi->cmap_inverse) { 291 red = 0xffff - red; 292 green = 0xffff - green; 293 blue = 0xffff - blue; 294 } 295 296 /* 297 * If greyscale is true, then we convert the RGB value 298 * to greyscale no mater what visual we are using. 299 */ 300 if (info->var.grayscale) 301 red = green = blue = (19595 * red + 38470 * green + 302 7471 * blue) >> 16; 303 304 switch (info->fix.visual) { 305 case FB_VISUAL_TRUECOLOR: 306 /* 307 * 12 or 16-bit True Colour. We encode the RGB value 308 * according to the RGB bitfield information. 309 */ 310 if (regno < 16) { 311 u32 *pal = info->pseudo_palette; 312 313 val = chan_to_field(red, &info->var.red); 314 val |= chan_to_field(green, &info->var.green); 315 val |= chan_to_field(blue, &info->var.blue); 316 317 pal[regno] = val; 318 ret = 0; 319 } 320 break; 321 322 case FB_VISUAL_STATIC_PSEUDOCOLOR: 323 case FB_VISUAL_PSEUDOCOLOR: 324 ret = imxfb_setpalettereg(regno, red, green, blue, trans, info); 325 break; 326 } 327 328 return ret; 329} 330 331static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi) 332{ 333 struct imx_fb_videomode *m; 334 int i; 335 336 if (!fb_mode) 337 return &fbi->mode[0]; 338 339 for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) { 340 if (!strcmp(m->mode.name, fb_mode)) 341 return m; 342 } 343 return NULL; 344} 345 346/* 347 * imxfb_check_var(): 348 * Round up in the following order: bits_per_pixel, xres, 349 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 350 * bitfields, horizontal timing, vertical timing. 351 */ 352static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 353{ 354 struct imxfb_info *fbi = info->par; 355 struct imxfb_rgb *rgb; 356 const struct imx_fb_videomode *imxfb_mode; 357 unsigned long lcd_clk; 358 unsigned long long tmp; 359 u32 pcr = 0; 360 361 if (var->xres < MIN_XRES) 362 var->xres = MIN_XRES; 363 if (var->yres < MIN_YRES) 364 var->yres = MIN_YRES; 365 366 imxfb_mode = imxfb_find_mode(fbi); 367 if (!imxfb_mode) 368 return -EINVAL; 369 370 var->xres = imxfb_mode->mode.xres; 371 var->yres = imxfb_mode->mode.yres; 372 var->bits_per_pixel = imxfb_mode->bpp; 373 var->pixclock = imxfb_mode->mode.pixclock; 374 var->hsync_len = imxfb_mode->mode.hsync_len; 375 var->left_margin = imxfb_mode->mode.left_margin; 376 var->right_margin = imxfb_mode->mode.right_margin; 377 var->vsync_len = imxfb_mode->mode.vsync_len; 378 var->upper_margin = imxfb_mode->mode.upper_margin; 379 var->lower_margin = imxfb_mode->mode.lower_margin; 380 var->sync = imxfb_mode->mode.sync; 381 var->xres_virtual = max(var->xres_virtual, var->xres); 382 var->yres_virtual = max(var->yres_virtual, var->yres); 383 384 pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); 385 386 lcd_clk = clk_get_rate(fbi->clk_per); 387 388 tmp = var->pixclock * (unsigned long long)lcd_clk; 389 390 do_div(tmp, 1000000); 391 392 if (do_div(tmp, 1000000) > 500000) 393 tmp++; 394 395 pcr = (unsigned int)tmp; 396 397 if (--pcr > 0x3F) { 398 pcr = 0x3F; 399 printk(KERN_WARNING "Must limit pixel clock to %luHz\n", 400 lcd_clk / pcr); 401 } 402 403 switch (var->bits_per_pixel) { 404 case 32: 405 pcr |= PCR_BPIX_18; 406 rgb = &def_rgb_18; 407 break; 408 case 16: 409 default: 410 if (is_imx1_fb(fbi)) 411 pcr |= PCR_BPIX_12; 412 else 413 pcr |= PCR_BPIX_16; 414 415 if (imxfb_mode->pcr & PCR_TFT) 416 rgb = &def_rgb_16_tft; 417 else 418 rgb = &def_rgb_16_stn; 419 break; 420 case 8: 421 pcr |= PCR_BPIX_8; 422 rgb = &def_rgb_8; 423 break; 424 } 425 426 /* add sync polarities */ 427 pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25)); 428 429 fbi->pcr = pcr; 430 /* 431 * The LCDC AUS Mode Control Register does not exist on imx1. 432 */ 433 if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode) 434 fbi->lauscr = LAUSCR_AUS_MODE; 435 436 /* 437 * Copy the RGB parameters for this display 438 * from the machine specific parameters. 439 */ 440 var->red = rgb->red; 441 var->green = rgb->green; 442 var->blue = rgb->blue; 443 var->transp = rgb->transp; 444 445 pr_debug("RGBT length = %d:%d:%d:%d\n", 446 var->red.length, var->green.length, var->blue.length, 447 var->transp.length); 448 449 pr_debug("RGBT offset = %d:%d:%d:%d\n", 450 var->red.offset, var->green.offset, var->blue.offset, 451 var->transp.offset); 452 453 return 0; 454} 455 456/* 457 * imxfb_set_par(): 458 * Set the user defined part of the display for the specified console 459 */ 460static int imxfb_set_par(struct fb_info *info) 461{ 462 struct imxfb_info *fbi = info->par; 463 struct fb_var_screeninfo *var = &info->var; 464 465 if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) 466 info->fix.visual = FB_VISUAL_TRUECOLOR; 467 else if (!fbi->cmap_static) 468 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 469 else { 470 /* 471 * Some people have weird ideas about wanting static 472 * pseudocolor maps. I suspect their user space 473 * applications are broken. 474 */ 475 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 476 } 477 478 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; 479 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; 480 481 imxfb_activate_var(var, info); 482 483 return 0; 484} 485 486static int imxfb_enable_controller(struct imxfb_info *fbi) 487{ 488 int ret; 489 490 if (fbi->enabled) 491 return 0; 492 493 pr_debug("Enabling LCD controller\n"); 494 495 writel(fbi->map_dma, fbi->regs + LCDC_SSA); 496 497 /* panning offset 0 (0 pixel offset) */ 498 writel(0x00000000, fbi->regs + LCDC_POS); 499 500 /* disable hardware cursor */ 501 writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), 502 fbi->regs + LCDC_CPOS); 503 504 /* 505 * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt 506 * on other SoCs 507 */ 508 writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR); 509 510 ret = clk_prepare_enable(fbi->clk_ipg); 511 if (ret) 512 goto err_enable_ipg; 513 514 ret = clk_prepare_enable(fbi->clk_ahb); 515 if (ret) 516 goto err_enable_ahb; 517 518 ret = clk_prepare_enable(fbi->clk_per); 519 if (ret) 520 goto err_enable_per; 521 522 fbi->enabled = true; 523 return 0; 524 525err_enable_per: 526 clk_disable_unprepare(fbi->clk_ahb); 527err_enable_ahb: 528 clk_disable_unprepare(fbi->clk_ipg); 529err_enable_ipg: 530 writel(0, fbi->regs + LCDC_RMCR); 531 532 return ret; 533} 534 535static void imxfb_disable_controller(struct imxfb_info *fbi) 536{ 537 if (!fbi->enabled) 538 return; 539 540 pr_debug("Disabling LCD controller\n"); 541 542 clk_disable_unprepare(fbi->clk_per); 543 clk_disable_unprepare(fbi->clk_ahb); 544 clk_disable_unprepare(fbi->clk_ipg); 545 fbi->enabled = false; 546 547 writel(0, fbi->regs + LCDC_RMCR); 548} 549 550static int imxfb_blank(int blank, struct fb_info *info) 551{ 552 struct imxfb_info *fbi = info->par; 553 554 pr_debug("imxfb_blank: blank=%d\n", blank); 555 556 switch (blank) { 557 case FB_BLANK_POWERDOWN: 558 case FB_BLANK_VSYNC_SUSPEND: 559 case FB_BLANK_HSYNC_SUSPEND: 560 case FB_BLANK_NORMAL: 561 imxfb_disable_controller(fbi); 562 break; 563 564 case FB_BLANK_UNBLANK: 565 return imxfb_enable_controller(fbi); 566 } 567 return 0; 568} 569 570static const struct fb_ops imxfb_ops = { 571 .owner = THIS_MODULE, 572 .fb_check_var = imxfb_check_var, 573 .fb_set_par = imxfb_set_par, 574 .fb_setcolreg = imxfb_setcolreg, 575 .fb_fillrect = cfb_fillrect, 576 .fb_copyarea = cfb_copyarea, 577 .fb_imageblit = cfb_imageblit, 578 .fb_blank = imxfb_blank, 579}; 580 581/* 582 * imxfb_activate_var(): 583 * Configures LCD Controller based on entries in var parameter. Settings are 584 * only written to the controller if changes were made. 585 */ 586static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) 587{ 588 struct imxfb_info *fbi = info->par; 589 u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21; 590 591 pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", 592 var->xres, var->hsync_len, 593 var->left_margin, var->right_margin); 594 pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n", 595 var->yres, var->vsync_len, 596 var->upper_margin, var->lower_margin); 597 598#if DEBUG_VAR 599 if (var->xres < 16 || var->xres > 1024) 600 printk(KERN_ERR "%s: invalid xres %d\n", 601 info->fix.id, var->xres); 602 if (var->hsync_len < 1 || var->hsync_len > 64) 603 printk(KERN_ERR "%s: invalid hsync_len %d\n", 604 info->fix.id, var->hsync_len); 605 if (var->left_margin < 3 || var->left_margin > 255) 606 printk(KERN_ERR "%s: invalid left_margin %d\n", 607 info->fix.id, var->left_margin); 608 if (var->right_margin < 1 || var->right_margin > 255) 609 printk(KERN_ERR "%s: invalid right_margin %d\n", 610 info->fix.id, var->right_margin); 611 if (var->yres < 1 || var->yres > ymax_mask) 612 printk(KERN_ERR "%s: invalid yres %d\n", 613 info->fix.id, var->yres); 614 if (var->vsync_len > 100) 615 printk(KERN_ERR "%s: invalid vsync_len %d\n", 616 info->fix.id, var->vsync_len); 617 if (var->upper_margin > 63) 618 printk(KERN_ERR "%s: invalid upper_margin %d\n", 619 info->fix.id, var->upper_margin); 620 if (var->lower_margin > 255) 621 printk(KERN_ERR "%s: invalid lower_margin %d\n", 622 info->fix.id, var->lower_margin); 623#endif 624 625 /* physical screen start address */ 626 writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4), 627 fbi->regs + LCDC_VPW); 628 629 writel(HCR_H_WIDTH(var->hsync_len - 1) | 630 HCR_H_WAIT_1(var->right_margin - 1) | 631 HCR_H_WAIT_2(var->left_margin - 3), 632 fbi->regs + LCDC_HCR); 633 634 writel(VCR_V_WIDTH(var->vsync_len) | 635 VCR_V_WAIT_1(var->lower_margin) | 636 VCR_V_WAIT_2(var->upper_margin), 637 fbi->regs + LCDC_VCR); 638 639 writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask), 640 fbi->regs + LCDC_SIZE); 641 642 writel(fbi->pcr, fbi->regs + LCDC_PCR); 643 if (fbi->pwmr) 644 writel(fbi->pwmr, fbi->regs + LCDC_PWMR); 645 writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); 646 647 /* dmacr = 0 is no valid value, as we need DMA control marks. */ 648 if (fbi->dmacr) 649 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); 650 651 if (fbi->lauscr) 652 writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR); 653 654 return 0; 655} 656 657static int imxfb_init_fbinfo(struct platform_device *pdev) 658{ 659 struct imx_fb_platform_data *pdata = dev_get_platdata(&pdev->dev); 660 struct fb_info *info = dev_get_drvdata(&pdev->dev); 661 struct imxfb_info *fbi = info->par; 662 struct device_node *np; 663 664 pr_debug("%s\n",__func__); 665 666 info->pseudo_palette = kmalloc_array(16, sizeof(u32), GFP_KERNEL); 667 if (!info->pseudo_palette) 668 return -ENOMEM; 669 670 memset(fbi, 0, sizeof(struct imxfb_info)); 671 672 fbi->devtype = pdev->id_entry->driver_data; 673 674 strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); 675 676 info->fix.type = FB_TYPE_PACKED_PIXELS; 677 info->fix.type_aux = 0; 678 info->fix.xpanstep = 0; 679 info->fix.ypanstep = 0; 680 info->fix.ywrapstep = 0; 681 info->fix.accel = FB_ACCEL_NONE; 682 683 info->var.nonstd = 0; 684 info->var.activate = FB_ACTIVATE_NOW; 685 info->var.height = -1; 686 info->var.width = -1; 687 info->var.accel_flags = 0; 688 info->var.vmode = FB_VMODE_NONINTERLACED; 689 690 info->fbops = &imxfb_ops; 691 info->flags = FBINFO_FLAG_DEFAULT | 692 FBINFO_READS_FAST; 693 if (pdata) { 694 fbi->lscr1 = pdata->lscr1; 695 fbi->dmacr = pdata->dmacr; 696 fbi->pwmr = pdata->pwmr; 697 } else { 698 np = pdev->dev.of_node; 699 info->var.grayscale = of_property_read_bool(np, 700 "cmap-greyscale"); 701 fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse"); 702 fbi->cmap_static = of_property_read_bool(np, "cmap-static"); 703 704 fbi->lscr1 = IMXFB_LSCR1_DEFAULT; 705 706 of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr); 707 708 of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1); 709 710 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); 711 } 712 713 return 0; 714} 715 716static int imxfb_of_read_mode(struct device *dev, struct device_node *np, 717 struct imx_fb_videomode *imxfb_mode) 718{ 719 int ret; 720 struct fb_videomode *of_mode = &imxfb_mode->mode; 721 u32 bpp; 722 u32 pcr; 723 724 ret = of_property_read_string(np, "model", &of_mode->name); 725 if (ret) 726 of_mode->name = NULL; 727 728 ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE); 729 if (ret) { 730 dev_err(dev, "Failed to get videomode from DT\n"); 731 return ret; 732 } 733 734 ret = of_property_read_u32(np, "bits-per-pixel", &bpp); 735 ret |= of_property_read_u32(np, "fsl,pcr", &pcr); 736 737 if (ret) { 738 dev_err(dev, "Failed to read bpp and pcr from DT\n"); 739 return -EINVAL; 740 } 741 742 if (bpp < 1 || bpp > 255) { 743 dev_err(dev, "Bits per pixel have to be between 1 and 255\n"); 744 return -EINVAL; 745 } 746 747 imxfb_mode->bpp = bpp; 748 imxfb_mode->pcr = pcr; 749 750 /* 751 * fsl,aus-mode is optional 752 */ 753 imxfb_mode->aus_mode = of_property_read_bool(np, "fsl,aus-mode"); 754 755 return 0; 756} 757 758static int imxfb_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi) 759{ 760 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 761 762 if (!fi || fi->par == fbi) 763 return 1; 764 765 return 0; 766} 767 768static int imxfb_lcd_get_contrast(struct lcd_device *lcddev) 769{ 770 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 771 772 return fbi->pwmr & 0xff; 773} 774 775static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast) 776{ 777 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 778 779 if (fbi->pwmr && fbi->enabled) { 780 if (contrast > 255) 781 contrast = 255; 782 else if (contrast < 0) 783 contrast = 0; 784 785 fbi->pwmr &= ~0xff; 786 fbi->pwmr |= contrast; 787 788 writel(fbi->pwmr, fbi->regs + LCDC_PWMR); 789 } 790 791 return 0; 792} 793 794static int imxfb_lcd_get_power(struct lcd_device *lcddev) 795{ 796 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 797 798 if (!IS_ERR(fbi->lcd_pwr) && 799 !regulator_is_enabled(fbi->lcd_pwr)) 800 return FB_BLANK_POWERDOWN; 801 802 return FB_BLANK_UNBLANK; 803} 804 805static int imxfb_regulator_set(struct imxfb_info *fbi, int enable) 806{ 807 int ret; 808 809 if (enable == fbi->lcd_pwr_enabled) 810 return 0; 811 812 if (enable) 813 ret = regulator_enable(fbi->lcd_pwr); 814 else 815 ret = regulator_disable(fbi->lcd_pwr); 816 817 if (ret == 0) 818 fbi->lcd_pwr_enabled = enable; 819 820 return ret; 821} 822 823static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power) 824{ 825 struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev); 826 827 if (!IS_ERR(fbi->lcd_pwr)) 828 return imxfb_regulator_set(fbi, power == FB_BLANK_UNBLANK); 829 830 return 0; 831} 832 833static struct lcd_ops imxfb_lcd_ops = { 834 .check_fb = imxfb_lcd_check_fb, 835 .get_contrast = imxfb_lcd_get_contrast, 836 .set_contrast = imxfb_lcd_set_contrast, 837 .get_power = imxfb_lcd_get_power, 838 .set_power = imxfb_lcd_set_power, 839}; 840 841static int imxfb_setup(void) 842{ 843 char *opt, *options = NULL; 844 845 if (fb_get_options("imxfb", &options)) 846 return -ENODEV; 847 848 if (!options || !*options) 849 return 0; 850 851 while ((opt = strsep(&options, ",")) != NULL) { 852 if (!*opt) 853 continue; 854 else 855 fb_mode = opt; 856 } 857 858 return 0; 859} 860 861static int imxfb_probe(struct platform_device *pdev) 862{ 863 struct imxfb_info *fbi; 864 struct lcd_device *lcd; 865 struct fb_info *info; 866 struct imx_fb_platform_data *pdata; 867 struct resource *res; 868 struct imx_fb_videomode *m; 869 const struct of_device_id *of_id; 870 int ret, i; 871 int bytes_per_pixel; 872 873 dev_info(&pdev->dev, "i.MX Framebuffer driver\n"); 874 875 ret = imxfb_setup(); 876 if (ret < 0) 877 return ret; 878 879 of_id = of_match_device(imxfb_of_dev_id, &pdev->dev); 880 if (of_id) 881 pdev->id_entry = of_id->data; 882 883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 884 if (!res) 885 return -ENODEV; 886 887 pdata = dev_get_platdata(&pdev->dev); 888 889 info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); 890 if (!info) 891 return -ENOMEM; 892 893 fbi = info->par; 894 895 platform_set_drvdata(pdev, info); 896 897 ret = imxfb_init_fbinfo(pdev); 898 if (ret < 0) 899 goto failed_init; 900 901 if (pdata) { 902 if (!fb_mode) 903 fb_mode = pdata->mode[0].mode.name; 904 905 fbi->mode = pdata->mode; 906 fbi->num_modes = pdata->num_modes; 907 } else { 908 struct device_node *display_np; 909 fb_mode = NULL; 910 911 display_np = of_parse_phandle(pdev->dev.of_node, "display", 0); 912 if (!display_np) { 913 dev_err(&pdev->dev, "No display defined in devicetree\n"); 914 ret = -EINVAL; 915 goto failed_of_parse; 916 } 917 918 /* 919 * imxfb does not support more modes, we choose only the native 920 * mode. 921 */ 922 fbi->num_modes = 1; 923 924 fbi->mode = devm_kzalloc(&pdev->dev, 925 sizeof(struct imx_fb_videomode), GFP_KERNEL); 926 if (!fbi->mode) { 927 ret = -ENOMEM; 928 goto failed_of_parse; 929 } 930 931 ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode); 932 if (ret) 933 goto failed_of_parse; 934 } 935 936 /* Calculate maximum bytes used per pixel. In most cases this should 937 * be the same as m->bpp/8 */ 938 m = &fbi->mode[0]; 939 bytes_per_pixel = (m->bpp + 7) / 8; 940 for (i = 0; i < fbi->num_modes; i++, m++) 941 info->fix.smem_len = max_t(size_t, info->fix.smem_len, 942 m->mode.xres * m->mode.yres * bytes_per_pixel); 943 944 res = request_mem_region(res->start, resource_size(res), 945 DRIVER_NAME); 946 if (!res) { 947 ret = -EBUSY; 948 goto failed_req; 949 } 950 951 fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 952 if (IS_ERR(fbi->clk_ipg)) { 953 ret = PTR_ERR(fbi->clk_ipg); 954 goto failed_getclock; 955 } 956 957 /* 958 * The LCDC controller does not have an enable bit. The 959 * controller starts directly when the clocks are enabled. 960 * If the clocks are enabled when the controller is not yet 961 * programmed with proper register values (enabled at the 962 * bootloader, for example) then it just goes into some undefined 963 * state. 964 * To avoid this issue, let's enable and disable LCDC IPG clock 965 * so that we force some kind of 'reset' to the LCDC block. 966 */ 967 ret = clk_prepare_enable(fbi->clk_ipg); 968 if (ret) 969 goto failed_getclock; 970 clk_disable_unprepare(fbi->clk_ipg); 971 972 fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 973 if (IS_ERR(fbi->clk_ahb)) { 974 ret = PTR_ERR(fbi->clk_ahb); 975 goto failed_getclock; 976 } 977 978 fbi->clk_per = devm_clk_get(&pdev->dev, "per"); 979 if (IS_ERR(fbi->clk_per)) { 980 ret = PTR_ERR(fbi->clk_per); 981 goto failed_getclock; 982 } 983 984 fbi->regs = ioremap(res->start, resource_size(res)); 985 if (fbi->regs == NULL) { 986 dev_err(&pdev->dev, "Cannot map frame buffer registers\n"); 987 ret = -ENOMEM; 988 goto failed_ioremap; 989 } 990 991 fbi->map_size = PAGE_ALIGN(info->fix.smem_len); 992 info->screen_buffer = dma_alloc_wc(&pdev->dev, fbi->map_size, 993 &fbi->map_dma, GFP_KERNEL); 994 if (!info->screen_buffer) { 995 dev_err(&pdev->dev, "Failed to allocate video RAM\n"); 996 ret = -ENOMEM; 997 goto failed_map; 998 } 999 1000 info->fix.smem_start = fbi->map_dma; 1001 1002 if (pdata && pdata->init) { 1003 ret = pdata->init(fbi->pdev); 1004 if (ret) 1005 goto failed_platform_init; 1006 } 1007 1008 1009 INIT_LIST_HEAD(&info->modelist); 1010 for (i = 0; i < fbi->num_modes; i++) 1011 fb_add_videomode(&fbi->mode[i].mode, &info->modelist); 1012 1013 /* 1014 * This makes sure that our colour bitfield 1015 * descriptors are correctly initialised. 1016 */ 1017 imxfb_check_var(&info->var, info); 1018 1019 /* 1020 * For modes > 8bpp, the color map is bypassed. 1021 * Therefore, 256 entries are enough. 1022 */ 1023 ret = fb_alloc_cmap(&info->cmap, 256, 0); 1024 if (ret < 0) 1025 goto failed_cmap; 1026 1027 imxfb_set_par(info); 1028 ret = register_framebuffer(info); 1029 if (ret < 0) { 1030 dev_err(&pdev->dev, "failed to register framebuffer\n"); 1031 goto failed_register; 1032 } 1033 1034 fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd"); 1035 if (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER) { 1036 ret = -EPROBE_DEFER; 1037 goto failed_lcd; 1038 } 1039 1040 lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi, 1041 &imxfb_lcd_ops); 1042 if (IS_ERR(lcd)) { 1043 ret = PTR_ERR(lcd); 1044 goto failed_lcd; 1045 } 1046 1047 lcd->props.max_contrast = 0xff; 1048 1049 imxfb_enable_controller(fbi); 1050 fbi->pdev = pdev; 1051 1052 return 0; 1053 1054failed_lcd: 1055 unregister_framebuffer(info); 1056 1057failed_register: 1058 fb_dealloc_cmap(&info->cmap); 1059failed_cmap: 1060 if (pdata && pdata->exit) 1061 pdata->exit(fbi->pdev); 1062failed_platform_init: 1063 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1064 fbi->map_dma); 1065failed_map: 1066 iounmap(fbi->regs); 1067failed_ioremap: 1068failed_getclock: 1069 release_mem_region(res->start, resource_size(res)); 1070failed_req: 1071failed_of_parse: 1072 kfree(info->pseudo_palette); 1073failed_init: 1074 framebuffer_release(info); 1075 return ret; 1076} 1077 1078static int imxfb_remove(struct platform_device *pdev) 1079{ 1080 struct imx_fb_platform_data *pdata; 1081 struct fb_info *info = platform_get_drvdata(pdev); 1082 struct imxfb_info *fbi = info->par; 1083 struct resource *res; 1084 1085 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1086 1087 imxfb_disable_controller(fbi); 1088 1089 unregister_framebuffer(info); 1090 fb_dealloc_cmap(&info->cmap); 1091 pdata = dev_get_platdata(&pdev->dev); 1092 if (pdata && pdata->exit) 1093 pdata->exit(fbi->pdev); 1094 dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer, 1095 fbi->map_dma); 1096 iounmap(fbi->regs); 1097 release_mem_region(res->start, resource_size(res)); 1098 kfree(info->pseudo_palette); 1099 framebuffer_release(info); 1100 1101 return 0; 1102} 1103 1104static int __maybe_unused imxfb_suspend(struct device *dev) 1105{ 1106 struct fb_info *info = dev_get_drvdata(dev); 1107 struct imxfb_info *fbi = info->par; 1108 1109 imxfb_disable_controller(fbi); 1110 1111 return 0; 1112} 1113 1114static int __maybe_unused imxfb_resume(struct device *dev) 1115{ 1116 struct fb_info *info = dev_get_drvdata(dev); 1117 struct imxfb_info *fbi = info->par; 1118 1119 imxfb_enable_controller(fbi); 1120 1121 return 0; 1122} 1123 1124static SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume); 1125 1126static struct platform_driver imxfb_driver = { 1127 .driver = { 1128 .name = DRIVER_NAME, 1129 .of_match_table = imxfb_of_dev_id, 1130 .pm = &imxfb_pm_ops, 1131 }, 1132 .probe = imxfb_probe, 1133 .remove = imxfb_remove, 1134 .id_table = imxfb_devtype, 1135}; 1136module_platform_driver(imxfb_driver); 1137 1138MODULE_DESCRIPTION("Freescale i.MX framebuffer driver"); 1139MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1140MODULE_LICENSE("GPL"); 1141