1 /*-*- linux-c -*- 2 * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device 3 * 4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> 5 * All Rights Reserved 6 * 7 * Contributors: 8 * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets 9 * and enabling the power-on state of 10 * external VGA connectors for 11 * secondary displays 12 * 13 * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of 14 * the VESA GTF 15 * 16 * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized 17 * timings support 18 * 19 * The code framework is a modification of vfb.c by Geert Uytterhoeven. 20 * DotClock and PLL calculations are partly based on i810_driver.c 21 * in xfree86 v4.0.3 by Precision Insight. 22 * Watermark calculation and tables are based on i810_wmark.c 23 * in xfre86 v4.0.3 by Precision Insight. Slight modifications 24 * only to allow for integer operations instead of floating point. 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file COPYING in the main directory of this archive for 28 * more details. 29 */ 30 31#include <linux/module.h> 32#include <linux/kernel.h> 33#include <linux/errno.h> 34#include <linux/string.h> 35#include <linux/mm.h> 36#include <linux/slab.h> 37#include <linux/fb.h> 38#include <linux/init.h> 39#include <linux/pci.h> 40#include <linux/pci_ids.h> 41#include <linux/resource.h> 42#include <linux/unistd.h> 43#include <linux/console.h> 44#include <linux/io.h> 45 46#include <asm/io.h> 47#include <asm/div64.h> 48#include <asm/page.h> 49 50#include "i810_regs.h" 51#include "i810.h" 52#include "i810_main.h" 53 54/* 55 * voffset - framebuffer offset in MiB from aperture start address. In order for 56 * the driver to work with X, we must try to use memory holes left untouched by X. The 57 * following table lists where X's different surfaces start at. 58 * 59 * --------------------------------------------- 60 * : : 64 MiB : 32 MiB : 61 * ---------------------------------------------- 62 * : FrontBuffer : 0 : 0 : 63 * : DepthBuffer : 48 : 16 : 64 * : BackBuffer : 56 : 24 : 65 * ---------------------------------------------- 66 * 67 * So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to 68 * 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should 69 * work, allowing 7 + 1 MiB of Framebuffer memory. 70 * Note, the size of the hole may change depending on how much memory you allocate to X, 71 * and how the memory is split up between these surfaces. 72 * 73 * Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with 74 * DRI disabled. But if the Frontbuffer is overlapped, X will fail to load. 75 * 76 * Experiment with v_offset to find out which works best for you. 77 */ 78static u32 v_offset_default; /* For 32 MiB Aper size, 8 should be the default */ 79static u32 voffset; 80 81static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor); 82static int i810fb_init_pci(struct pci_dev *dev, 83 const struct pci_device_id *entry); 84static void i810fb_remove_pci(struct pci_dev *dev); 85static int i810fb_resume(struct pci_dev *dev); 86static int i810fb_suspend(struct pci_dev *dev, pm_message_t state); 87 88/* Chipset Specific Functions */ 89static int i810fb_set_par (struct fb_info *info); 90static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue, 91 u8 *transp, struct fb_info *info); 92static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue, 93 unsigned transp, struct fb_info *info); 94static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); 95static int i810fb_blank (int blank_mode, struct fb_info *info); 96 97/* Initialization */ 98static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par); 99 100/* PCI */ 101static const char * const i810_pci_list[] = { 102 "Intel(R) 810 Framebuffer Device" , 103 "Intel(R) 810-DC100 Framebuffer Device" , 104 "Intel(R) 810E Framebuffer Device" , 105 "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" , 106 "Intel(R) 815 (Internal Graphics only) Framebuffer Device" , 107 "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device" 108}; 109 110static const struct pci_device_id i810fb_pci_tbl[] = { 111 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1, 112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 113 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, 114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, 115 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG, 116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, 117 /* mvo: added i815 PCI-ID */ 118 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, 120 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, 122 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, 124 { 0 }, 125}; 126 127static struct pci_driver i810fb_driver = { 128 .name = "i810fb", 129 .id_table = i810fb_pci_tbl, 130 .probe = i810fb_init_pci, 131 .remove = i810fb_remove_pci, 132 .suspend = i810fb_suspend, 133 .resume = i810fb_resume, 134}; 135 136static char *mode_option = NULL; 137static int vram = 4; 138static int bpp = 8; 139static bool mtrr; 140static bool accel; 141static int hsync1; 142static int hsync2; 143static int vsync1; 144static int vsync2; 145static int xres; 146static int yres; 147static int vyres; 148static bool sync; 149static bool extvga; 150static bool dcolor; 151static bool ddc3; 152 153/*------------------------------------------------------------*/ 154 155/************************************************************** 156 * Hardware Low Level Routines * 157 **************************************************************/ 158 159/** 160 * i810_screen_off - turns off/on display 161 * @mmio: address of register space 162 * @mode: on or off 163 * 164 * DESCRIPTION: 165 * Blanks/unblanks the display 166 */ 167static void i810_screen_off(u8 __iomem *mmio, u8 mode) 168{ 169 u32 count = WAIT_COUNT; 170 u8 val; 171 172 i810_writeb(SR_INDEX, mmio, SR01); 173 val = i810_readb(SR_DATA, mmio); 174 val = (mode == OFF) ? val | SCR_OFF : 175 val & ~SCR_OFF; 176 177 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); 178 i810_writeb(SR_INDEX, mmio, SR01); 179 i810_writeb(SR_DATA, mmio, val); 180} 181 182/** 183 * i810_dram_off - turns off/on dram refresh 184 * @mmio: address of register space 185 * @mode: on or off 186 * 187 * DESCRIPTION: 188 * Turns off DRAM refresh. Must be off for only 2 vsyncs 189 * before data becomes corrupt 190 */ 191static void i810_dram_off(u8 __iomem *mmio, u8 mode) 192{ 193 u8 val; 194 195 val = i810_readb(DRAMCH, mmio); 196 val &= DRAM_OFF; 197 val = (mode == OFF) ? val : val | DRAM_ON; 198 i810_writeb(DRAMCH, mmio, val); 199} 200 201/** 202 * i810_protect_regs - allows rw/ro mode of certain VGA registers 203 * @mmio: address of register space 204 * @mode: protect/unprotect 205 * 206 * DESCRIPTION: 207 * The IBM VGA standard allows protection of certain VGA registers. 208 * This will protect or unprotect them. 209 */ 210static void i810_protect_regs(u8 __iomem *mmio, int mode) 211{ 212 u8 reg; 213 214 i810_writeb(CR_INDEX_CGA, mmio, CR11); 215 reg = i810_readb(CR_DATA_CGA, mmio); 216 reg = (mode == OFF) ? reg & ~0x80 : 217 reg | 0x80; 218 219 i810_writeb(CR_INDEX_CGA, mmio, CR11); 220 i810_writeb(CR_DATA_CGA, mmio, reg); 221} 222 223/** 224 * i810_load_pll - loads values for the hardware PLL clock 225 * @par: pointer to i810fb_par structure 226 * 227 * DESCRIPTION: 228 * Loads the P, M, and N registers. 229 */ 230static void i810_load_pll(struct i810fb_par *par) 231{ 232 u32 tmp1, tmp2; 233 u8 __iomem *mmio = par->mmio_start_virtual; 234 235 tmp1 = par->regs.M | par->regs.N << 16; 236 tmp2 = i810_readl(DCLK_2D, mmio); 237 tmp2 &= ~MN_MASK; 238 i810_writel(DCLK_2D, mmio, tmp1 | tmp2); 239 240 tmp1 = par->regs.P; 241 tmp2 = i810_readl(DCLK_0DS, mmio); 242 tmp2 &= ~(P_OR << 16); 243 i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2); 244 245 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1); 246 247} 248 249/** 250 * i810_load_vga - load standard VGA registers 251 * @par: pointer to i810fb_par structure 252 * 253 * DESCRIPTION: 254 * Load values to VGA registers 255 */ 256static void i810_load_vga(struct i810fb_par *par) 257{ 258 u8 __iomem *mmio = par->mmio_start_virtual; 259 260 /* interlace */ 261 i810_writeb(CR_INDEX_CGA, mmio, CR70); 262 i810_writeb(CR_DATA_CGA, mmio, par->interlace); 263 264 i810_writeb(CR_INDEX_CGA, mmio, CR00); 265 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00); 266 i810_writeb(CR_INDEX_CGA, mmio, CR01); 267 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01); 268 i810_writeb(CR_INDEX_CGA, mmio, CR02); 269 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02); 270 i810_writeb(CR_INDEX_CGA, mmio, CR03); 271 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03); 272 i810_writeb(CR_INDEX_CGA, mmio, CR04); 273 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04); 274 i810_writeb(CR_INDEX_CGA, mmio, CR05); 275 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05); 276 i810_writeb(CR_INDEX_CGA, mmio, CR06); 277 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06); 278 i810_writeb(CR_INDEX_CGA, mmio, CR09); 279 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09); 280 i810_writeb(CR_INDEX_CGA, mmio, CR10); 281 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10); 282 i810_writeb(CR_INDEX_CGA, mmio, CR11); 283 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11); 284 i810_writeb(CR_INDEX_CGA, mmio, CR12); 285 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12); 286 i810_writeb(CR_INDEX_CGA, mmio, CR15); 287 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15); 288 i810_writeb(CR_INDEX_CGA, mmio, CR16); 289 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16); 290} 291 292/** 293 * i810_load_vgax - load extended VGA registers 294 * @par: pointer to i810fb_par structure 295 * 296 * DESCRIPTION: 297 * Load values to extended VGA registers 298 */ 299static void i810_load_vgax(struct i810fb_par *par) 300{ 301 u8 __iomem *mmio = par->mmio_start_virtual; 302 303 i810_writeb(CR_INDEX_CGA, mmio, CR30); 304 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30); 305 i810_writeb(CR_INDEX_CGA, mmio, CR31); 306 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31); 307 i810_writeb(CR_INDEX_CGA, mmio, CR32); 308 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32); 309 i810_writeb(CR_INDEX_CGA, mmio, CR33); 310 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33); 311 i810_writeb(CR_INDEX_CGA, mmio, CR35); 312 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35); 313 i810_writeb(CR_INDEX_CGA, mmio, CR39); 314 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39); 315} 316 317/** 318 * i810_load_2d - load grahics registers 319 * @par: pointer to i810fb_par structure 320 * 321 * DESCRIPTION: 322 * Load values to graphics registers 323 */ 324static void i810_load_2d(struct i810fb_par *par) 325{ 326 u32 tmp; 327 u8 tmp8; 328 u8 __iomem *mmio = par->mmio_start_virtual; 329 330 i810_writel(FW_BLC, mmio, par->watermark); 331 tmp = i810_readl(PIXCONF, mmio); 332 tmp |= 1 | 1 << 20; 333 i810_writel(PIXCONF, mmio, tmp); 334 335 i810_writel(OVRACT, mmio, par->ovract); 336 337 i810_writeb(GR_INDEX, mmio, GR10); 338 tmp8 = i810_readb(GR_DATA, mmio); 339 tmp8 |= 2; 340 i810_writeb(GR_INDEX, mmio, GR10); 341 i810_writeb(GR_DATA, mmio, tmp8); 342} 343 344/** 345 * i810_hires - enables high resolution mode 346 * @mmio: address of register space 347 */ 348static void i810_hires(u8 __iomem *mmio) 349{ 350 u8 val; 351 352 i810_writeb(CR_INDEX_CGA, mmio, CR80); 353 val = i810_readb(CR_DATA_CGA, mmio); 354 i810_writeb(CR_INDEX_CGA, mmio, CR80); 355 i810_writeb(CR_DATA_CGA, mmio, val | 1); 356 /* Stop LCD displays from flickering */ 357 i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4); 358} 359 360/** 361 * i810_load_pitch - loads the characters per line of the display 362 * @par: pointer to i810fb_par structure 363 * 364 * DESCRIPTION: 365 * Loads the characters per line 366 */ 367static void i810_load_pitch(struct i810fb_par *par) 368{ 369 u32 tmp, pitch; 370 u8 val; 371 u8 __iomem *mmio = par->mmio_start_virtual; 372 373 pitch = par->pitch >> 3; 374 i810_writeb(SR_INDEX, mmio, SR01); 375 val = i810_readb(SR_DATA, mmio); 376 val &= 0xE0; 377 val |= 1 | 1 << 2; 378 i810_writeb(SR_INDEX, mmio, SR01); 379 i810_writeb(SR_DATA, mmio, val); 380 381 tmp = pitch & 0xFF; 382 i810_writeb(CR_INDEX_CGA, mmio, CR13); 383 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp); 384 385 tmp = pitch >> 8; 386 i810_writeb(CR_INDEX_CGA, mmio, CR41); 387 val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F; 388 i810_writeb(CR_INDEX_CGA, mmio, CR41); 389 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val); 390} 391 392/** 393 * i810_load_color - loads the color depth of the display 394 * @par: pointer to i810fb_par structure 395 * 396 * DESCRIPTION: 397 * Loads the color depth of the display and the graphics engine 398 */ 399static void i810_load_color(struct i810fb_par *par) 400{ 401 u8 __iomem *mmio = par->mmio_start_virtual; 402 u32 reg1; 403 u16 reg2; 404 405 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27); 406 reg2 = i810_readw(BLTCNTL, mmio) & ~0x30; 407 408 reg1 |= 0x8000 | par->pixconf; 409 reg2 |= par->bltcntl; 410 i810_writel(PIXCONF, mmio, reg1); 411 i810_writew(BLTCNTL, mmio, reg2); 412} 413 414/** 415 * i810_load_regs - loads all registers for the mode 416 * @par: pointer to i810fb_par structure 417 * 418 * DESCRIPTION: 419 * Loads registers 420 */ 421static void i810_load_regs(struct i810fb_par *par) 422{ 423 u8 __iomem *mmio = par->mmio_start_virtual; 424 425 i810_screen_off(mmio, OFF); 426 i810_protect_regs(mmio, OFF); 427 i810_dram_off(mmio, OFF); 428 i810_load_pll(par); 429 i810_load_vga(par); 430 i810_load_vgax(par); 431 i810_dram_off(mmio, ON); 432 i810_load_2d(par); 433 i810_hires(mmio); 434 i810_screen_off(mmio, ON); 435 i810_protect_regs(mmio, ON); 436 i810_load_color(par); 437 i810_load_pitch(par); 438} 439 440static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue, 441 u8 __iomem *mmio) 442{ 443 i810_writeb(CLUT_INDEX_WRITE, mmio, regno); 444 i810_writeb(CLUT_DATA, mmio, red); 445 i810_writeb(CLUT_DATA, mmio, green); 446 i810_writeb(CLUT_DATA, mmio, blue); 447} 448 449static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue, 450 u8 __iomem *mmio) 451{ 452 i810_writeb(CLUT_INDEX_READ, mmio, regno); 453 *red = i810_readb(CLUT_DATA, mmio); 454 *green = i810_readb(CLUT_DATA, mmio); 455 *blue = i810_readb(CLUT_DATA, mmio); 456} 457 458/************************************************************ 459 * VGA State Restore * 460 ************************************************************/ 461static void i810_restore_pll(struct i810fb_par *par) 462{ 463 u32 tmp1, tmp2; 464 u8 __iomem *mmio = par->mmio_start_virtual; 465 466 tmp1 = par->hw_state.dclk_2d; 467 tmp2 = i810_readl(DCLK_2D, mmio); 468 tmp1 &= ~MN_MASK; 469 tmp2 &= MN_MASK; 470 i810_writel(DCLK_2D, mmio, tmp1 | tmp2); 471 472 tmp1 = par->hw_state.dclk_1d; 473 tmp2 = i810_readl(DCLK_1D, mmio); 474 tmp1 &= ~MN_MASK; 475 tmp2 &= MN_MASK; 476 i810_writel(DCLK_1D, mmio, tmp1 | tmp2); 477 478 i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds); 479} 480 481static void i810_restore_dac(struct i810fb_par *par) 482{ 483 u32 tmp1, tmp2; 484 u8 __iomem *mmio = par->mmio_start_virtual; 485 486 tmp1 = par->hw_state.pixconf; 487 tmp2 = i810_readl(PIXCONF, mmio); 488 tmp1 &= DAC_BIT; 489 tmp2 &= ~DAC_BIT; 490 i810_writel(PIXCONF, mmio, tmp1 | tmp2); 491} 492 493static void i810_restore_vgax(struct i810fb_par *par) 494{ 495 u8 i, j; 496 u8 __iomem *mmio = par->mmio_start_virtual; 497 498 for (i = 0; i < 4; i++) { 499 i810_writeb(CR_INDEX_CGA, mmio, CR30+i); 500 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i)); 501 } 502 i810_writeb(CR_INDEX_CGA, mmio, CR35); 503 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35); 504 i810_writeb(CR_INDEX_CGA, mmio, CR39); 505 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); 506 i810_writeb(CR_INDEX_CGA, mmio, CR41); 507 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); 508 509 /*restore interlace*/ 510 i810_writeb(CR_INDEX_CGA, mmio, CR70); 511 i = par->hw_state.cr70; 512 i &= INTERLACE_BIT; 513 j = i810_readb(CR_DATA_CGA, mmio); 514 i810_writeb(CR_INDEX_CGA, mmio, CR70); 515 i810_writeb(CR_DATA_CGA, mmio, j | i); 516 517 i810_writeb(CR_INDEX_CGA, mmio, CR80); 518 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80); 519 i810_writeb(MSR_WRITE, mmio, par->hw_state.msr); 520 i810_writeb(SR_INDEX, mmio, SR01); 521 i = (par->hw_state.sr01) & ~0xE0 ; 522 j = i810_readb(SR_DATA, mmio) & 0xE0; 523 i810_writeb(SR_INDEX, mmio, SR01); 524 i810_writeb(SR_DATA, mmio, i | j); 525} 526 527static void i810_restore_vga(struct i810fb_par *par) 528{ 529 u8 i; 530 u8 __iomem *mmio = par->mmio_start_virtual; 531 532 for (i = 0; i < 10; i++) { 533 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); 534 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i)); 535 } 536 for (i = 0; i < 8; i++) { 537 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); 538 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i)); 539 } 540} 541 542static void i810_restore_addr_map(struct i810fb_par *par) 543{ 544 u8 tmp; 545 u8 __iomem *mmio = par->mmio_start_virtual; 546 547 i810_writeb(GR_INDEX, mmio, GR10); 548 tmp = i810_readb(GR_DATA, mmio); 549 tmp &= ADDR_MAP_MASK; 550 tmp |= par->hw_state.gr10; 551 i810_writeb(GR_INDEX, mmio, GR10); 552 i810_writeb(GR_DATA, mmio, tmp); 553} 554 555static void i810_restore_2d(struct i810fb_par *par) 556{ 557 u32 tmp_long; 558 u16 tmp_word; 559 u8 __iomem *mmio = par->mmio_start_virtual; 560 561 tmp_word = i810_readw(BLTCNTL, mmio); 562 tmp_word &= ~(3 << 4); 563 tmp_word |= par->hw_state.bltcntl; 564 i810_writew(BLTCNTL, mmio, tmp_word); 565 566 i810_dram_off(mmio, OFF); 567 i810_writel(PIXCONF, mmio, par->hw_state.pixconf); 568 i810_dram_off(mmio, ON); 569 570 tmp_word = i810_readw(HWSTAM, mmio); 571 tmp_word &= 3 << 13; 572 tmp_word |= par->hw_state.hwstam; 573 i810_writew(HWSTAM, mmio, tmp_word); 574 575 tmp_long = i810_readl(FW_BLC, mmio); 576 tmp_long &= FW_BLC_MASK; 577 tmp_long |= par->hw_state.fw_blc; 578 i810_writel(FW_BLC, mmio, tmp_long); 579 580 i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga); 581 i810_writew(IER, mmio, par->hw_state.ier); 582 i810_writew(IMR, mmio, par->hw_state.imr); 583 i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas); 584} 585 586static void i810_restore_vga_state(struct i810fb_par *par) 587{ 588 u8 __iomem *mmio = par->mmio_start_virtual; 589 590 i810_screen_off(mmio, OFF); 591 i810_protect_regs(mmio, OFF); 592 i810_dram_off(mmio, OFF); 593 i810_restore_pll(par); 594 i810_restore_dac(par); 595 i810_restore_vga(par); 596 i810_restore_vgax(par); 597 i810_restore_addr_map(par); 598 i810_dram_off(mmio, ON); 599 i810_restore_2d(par); 600 i810_screen_off(mmio, ON); 601 i810_protect_regs(mmio, ON); 602} 603 604/*********************************************************************** 605 * VGA State Save * 606 ***********************************************************************/ 607 608static void i810_save_vgax(struct i810fb_par *par) 609{ 610 u8 i; 611 u8 __iomem *mmio = par->mmio_start_virtual; 612 613 for (i = 0; i < 4; i++) { 614 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i); 615 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio); 616 } 617 i810_writeb(CR_INDEX_CGA, mmio, CR35); 618 par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio); 619 i810_writeb(CR_INDEX_CGA, mmio, CR39); 620 par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio); 621 i810_writeb(CR_INDEX_CGA, mmio, CR41); 622 par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio); 623 i810_writeb(CR_INDEX_CGA, mmio, CR70); 624 par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio); 625 par->hw_state.msr = i810_readb(MSR_READ, mmio); 626 i810_writeb(CR_INDEX_CGA, mmio, CR80); 627 par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio); 628 i810_writeb(SR_INDEX, mmio, SR01); 629 par->hw_state.sr01 = i810_readb(SR_DATA, mmio); 630} 631 632static void i810_save_vga(struct i810fb_par *par) 633{ 634 u8 i; 635 u8 __iomem *mmio = par->mmio_start_virtual; 636 637 for (i = 0; i < 10; i++) { 638 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i); 639 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio); 640 } 641 for (i = 0; i < 8; i++) { 642 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i); 643 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio); 644 } 645} 646 647static void i810_save_2d(struct i810fb_par *par) 648{ 649 u8 __iomem *mmio = par->mmio_start_virtual; 650 651 par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio); 652 par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio); 653 par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio); 654 par->hw_state.pixconf = i810_readl(PIXCONF, mmio); 655 par->hw_state.fw_blc = i810_readl(FW_BLC, mmio); 656 par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio); 657 par->hw_state.hwstam = i810_readw(HWSTAM, mmio); 658 par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio); 659 par->hw_state.ier = i810_readw(IER, mmio); 660 par->hw_state.imr = i810_readw(IMR, mmio); 661 par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio); 662} 663 664static void i810_save_vga_state(struct i810fb_par *par) 665{ 666 i810_save_vga(par); 667 i810_save_vgax(par); 668 i810_save_2d(par); 669} 670 671/************************************************************ 672 * Helpers * 673 ************************************************************/ 674/** 675 * get_line_length - calculates buffer pitch in bytes 676 * @par: pointer to i810fb_par structure 677 * @xres_virtual: virtual resolution of the frame 678 * @bpp: bits per pixel 679 * 680 * DESCRIPTION: 681 * Calculates buffer pitch in bytes. 682 */ 683static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp) 684{ 685 u32 length; 686 687 length = xres_virtual*bpp; 688 length = (length+31)&-32; 689 length >>= 3; 690 return length; 691} 692 693/** 694 * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value 695 * @freq: target pixelclock in picoseconds 696 * @m: where to write M register 697 * @n: where to write N register 698 * @p: where to write P register 699 * 700 * DESCRIPTION: 701 * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P) 702 * Repeatedly computes the Freq until the actual Freq is equal to 703 * the target Freq or until the loop count is zero. In the latter 704 * case, the actual frequency nearest the target will be used. 705 */ 706static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p) 707{ 708 u32 m_reg, n_reg, p_divisor, n_target_max; 709 u32 m_target, n_target, p_target, n_best, m_best, mod; 710 u32 f_out, target_freq, diff = 0, mod_min, diff_min; 711 712 diff_min = mod_min = 0xFFFFFFFF; 713 n_best = m_best = m_target = f_out = 0; 714 715 target_freq = freq; 716 n_target_max = 30; 717 718 /* 719 * find P such that target freq is 16x reference freq (Hz). 720 */ 721 p_divisor = 1; 722 p_target = 0; 723 while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) && 724 p_divisor <= 32) { 725 p_divisor <<= 1; 726 p_target++; 727 } 728 729 n_reg = m_reg = n_target = 3; 730 while (diff_min && mod_min && (n_target < n_target_max)) { 731 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg); 732 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg); 733 m_target = m_reg; 734 n_target = n_reg; 735 if (f_out <= target_freq) { 736 n_reg++; 737 diff = target_freq - f_out; 738 } else { 739 m_reg++; 740 diff = f_out - target_freq; 741 } 742 743 if (diff_min > diff) { 744 diff_min = diff; 745 n_best = n_target; 746 m_best = m_target; 747 } 748 749 if (!diff && mod_min > mod) { 750 mod_min = mod; 751 n_best = n_target; 752 m_best = m_target; 753 } 754 } 755 if (m) *m = (m_best - 2) & 0x3FF; 756 if (n) *n = (n_best - 2) & 0x3FF; 757 if (p) *p = (p_target << 4); 758} 759 760/************************************************************* 761 * Hardware Cursor Routines * 762 *************************************************************/ 763 764/** 765 * i810_enable_cursor - show or hide the hardware cursor 766 * @mmio: address of register space 767 * @mode: show (1) or hide (0) 768 * 769 * Description: 770 * Shows or hides the hardware cursor 771 */ 772static void i810_enable_cursor(u8 __iomem *mmio, int mode) 773{ 774 u32 temp; 775 776 temp = i810_readl(PIXCONF, mmio); 777 temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK : 778 temp & ~CURSOR_ENABLE_MASK; 779 780 i810_writel(PIXCONF, mmio, temp); 781} 782 783static void i810_reset_cursor_image(struct i810fb_par *par) 784{ 785 u8 __iomem *addr = par->cursor_heap.virtual; 786 int i, j; 787 788 for (i = 64; i--; ) { 789 for (j = 0; j < 8; j++) { 790 i810_writeb(j, addr, 0xff); 791 i810_writeb(j+8, addr, 0x00); 792 } 793 addr +=16; 794 } 795} 796 797static void i810_load_cursor_image(int width, int height, u8 *data, 798 struct i810fb_par *par) 799{ 800 u8 __iomem *addr = par->cursor_heap.virtual; 801 int i, j, w = width/8; 802 int mod = width % 8, t_mask, d_mask; 803 804 t_mask = 0xff >> mod; 805 d_mask = ~(0xff >> mod); 806 for (i = height; i--; ) { 807 for (j = 0; j < w; j++) { 808 i810_writeb(j+0, addr, 0x00); 809 i810_writeb(j+8, addr, *data++); 810 } 811 if (mod) { 812 i810_writeb(j+0, addr, t_mask); 813 i810_writeb(j+8, addr, *data++ & d_mask); 814 } 815 addr += 16; 816 } 817} 818 819static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info) 820{ 821 struct i810fb_par *par = info->par; 822 u8 __iomem *mmio = par->mmio_start_virtual; 823 u8 red, green, blue, trans, temp; 824 825 i810fb_getcolreg(bg, &red, &green, &blue, &trans, info); 826 827 temp = i810_readb(PIXCONF1, mmio); 828 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); 829 830 i810_write_dac(4, red, green, blue, mmio); 831 832 i810_writeb(PIXCONF1, mmio, temp); 833 834 i810fb_getcolreg(fg, &red, &green, &blue, &trans, info); 835 temp = i810_readb(PIXCONF1, mmio); 836 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE); 837 838 i810_write_dac(5, red, green, blue, mmio); 839 840 i810_writeb(PIXCONF1, mmio, temp); 841} 842 843/** 844 * i810_init_cursor - initializes the cursor 845 * @par: pointer to i810fb_par structure 846 * 847 * DESCRIPTION: 848 * Initializes the cursor registers 849 */ 850static void i810_init_cursor(struct i810fb_par *par) 851{ 852 u8 __iomem *mmio = par->mmio_start_virtual; 853 854 i810_enable_cursor(mmio, OFF); 855 i810_writel(CURBASE, mmio, par->cursor_heap.physical); 856 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR); 857} 858 859/********************************************************************* 860 * Framebuffer hook helpers * 861 *********************************************************************/ 862/** 863 * i810_round_off - Round off values to capability of hardware 864 * @var: pointer to fb_var_screeninfo structure 865 * 866 * DESCRIPTION: 867 * @var contains user-defined information for the mode to be set. 868 * This will try modify those values to ones nearest the 869 * capability of the hardware 870 */ 871static void i810_round_off(struct fb_var_screeninfo *var) 872{ 873 u32 xres, yres, vxres, vyres; 874 875 /* 876 * Presently supports only these configurations 877 */ 878 879 xres = var->xres; 880 yres = var->yres; 881 vxres = var->xres_virtual; 882 vyres = var->yres_virtual; 883 884 var->bits_per_pixel += 7; 885 var->bits_per_pixel &= ~7; 886 887 if (var->bits_per_pixel < 8) 888 var->bits_per_pixel = 8; 889 if (var->bits_per_pixel > 32) 890 var->bits_per_pixel = 32; 891 892 round_off_xres(&xres); 893 if (xres < 40) 894 xres = 40; 895 if (xres > 2048) 896 xres = 2048; 897 xres = (xres + 7) & ~7; 898 899 if (vxres < xres) 900 vxres = xres; 901 902 round_off_yres(&xres, &yres); 903 if (yres < 1) 904 yres = 1; 905 if (yres >= 2048) 906 yres = 2048; 907 908 if (vyres < yres) 909 vyres = yres; 910 911 if (var->bits_per_pixel == 32) 912 var->accel_flags = 0; 913 914 /* round of horizontal timings to nearest 8 pixels */ 915 var->left_margin = (var->left_margin + 4) & ~7; 916 var->right_margin = (var->right_margin + 4) & ~7; 917 var->hsync_len = (var->hsync_len + 4) & ~7; 918 919 if (var->vmode & FB_VMODE_INTERLACED) { 920 if (!((yres + var->upper_margin + var->vsync_len + 921 var->lower_margin) & 1)) 922 var->upper_margin++; 923 } 924 925 var->xres = xres; 926 var->yres = yres; 927 var->xres_virtual = vxres; 928 var->yres_virtual = vyres; 929} 930 931/** 932 * set_color_bitfields - sets rgba fields 933 * @var: pointer to fb_var_screeninfo 934 * 935 * DESCRIPTION: 936 * The length, offset and ordering for each color field 937 * (red, green, blue) will be set as specified 938 * by the hardware 939 */ 940static void set_color_bitfields(struct fb_var_screeninfo *var) 941{ 942 switch (var->bits_per_pixel) { 943 case 8: 944 var->red.offset = 0; 945 var->red.length = 8; 946 var->green.offset = 0; 947 var->green.length = 8; 948 var->blue.offset = 0; 949 var->blue.length = 8; 950 var->transp.offset = 0; 951 var->transp.length = 0; 952 break; 953 case 16: 954 var->green.length = (var->green.length == 5) ? 5 : 6; 955 var->red.length = 5; 956 var->blue.length = 5; 957 var->transp.length = 6 - var->green.length; 958 var->blue.offset = 0; 959 var->green.offset = 5; 960 var->red.offset = 5 + var->green.length; 961 var->transp.offset = (5 + var->red.offset) & 15; 962 break; 963 case 24: /* RGB 888 */ 964 case 32: /* RGBA 8888 */ 965 var->red.offset = 16; 966 var->red.length = 8; 967 var->green.offset = 8; 968 var->green.length = 8; 969 var->blue.offset = 0; 970 var->blue.length = 8; 971 var->transp.length = var->bits_per_pixel - 24; 972 var->transp.offset = (var->transp.length) ? 24 : 0; 973 break; 974 } 975 var->red.msb_right = 0; 976 var->green.msb_right = 0; 977 var->blue.msb_right = 0; 978 var->transp.msb_right = 0; 979} 980 981/** 982 * i810_check_params - check if contents in var are valid 983 * @var: pointer to fb_var_screeninfo 984 * @info: pointer to fb_info 985 * 986 * DESCRIPTION: 987 * This will check if the framebuffer size is sufficient 988 * for the current mode and if the user's monitor has the 989 * required specifications to display the current mode. 990 */ 991static int i810_check_params(struct fb_var_screeninfo *var, 992 struct fb_info *info) 993{ 994 struct i810fb_par *par = info->par; 995 int line_length, vidmem, mode_valid = 0, retval = 0; 996 u32 vyres = var->yres_virtual, vxres = var->xres_virtual; 997 998 /* 999 * Memory limit 1000 */ 1001 line_length = get_line_length(par, vxres, var->bits_per_pixel); 1002 vidmem = line_length*vyres; 1003 1004 if (vidmem > par->fb.size) { 1005 vyres = par->fb.size/line_length; 1006 if (vyres < var->yres) { 1007 vyres = info->var.yres; 1008 vxres = par->fb.size/vyres; 1009 vxres /= var->bits_per_pixel >> 3; 1010 line_length = get_line_length(par, vxres, 1011 var->bits_per_pixel); 1012 vidmem = line_length * info->var.yres; 1013 if (vxres < var->xres) { 1014 printk("i810fb: required video memory, " 1015 "%d bytes, for %dx%d-%d (virtual) " 1016 "is out of range\n", 1017 vidmem, vxres, vyres, 1018 var->bits_per_pixel); 1019 return -ENOMEM; 1020 } 1021 } 1022 } 1023 1024 var->xres_virtual = vxres; 1025 var->yres_virtual = vyres; 1026 1027 /* 1028 * Monitor limit 1029 */ 1030 switch (var->bits_per_pixel) { 1031 case 8: 1032 info->monspecs.dclkmax = 234000000; 1033 break; 1034 case 16: 1035 info->monspecs.dclkmax = 229000000; 1036 break; 1037 case 24: 1038 case 32: 1039 info->monspecs.dclkmax = 204000000; 1040 break; 1041 } 1042 1043 info->monspecs.dclkmin = 15000000; 1044 1045 if (!fb_validate_mode(var, info)) 1046 mode_valid = 1; 1047 1048#ifdef CONFIG_FB_I810_I2C 1049 if (!mode_valid && info->monspecs.gtf && 1050 !fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1051 mode_valid = 1; 1052 1053 if (!mode_valid && info->monspecs.modedb_len) { 1054 const struct fb_videomode *mode; 1055 1056 mode = fb_find_best_mode(var, &info->modelist); 1057 if (mode) { 1058 fb_videomode_to_var(var, mode); 1059 mode_valid = 1; 1060 } 1061 } 1062#endif 1063 if (!mode_valid && info->monspecs.modedb_len == 0) { 1064 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) { 1065 int default_sync = (info->monspecs.hfmin-HFMIN) 1066 |(info->monspecs.hfmax-HFMAX) 1067 |(info->monspecs.vfmin-VFMIN) 1068 |(info->monspecs.vfmax-VFMAX); 1069 printk("i810fb: invalid video mode%s\n", 1070 default_sync ? "" : ". Specifying " 1071 "vsyncN/hsyncN parameters may help"); 1072 retval = -EINVAL; 1073 } 1074 } 1075 1076 return retval; 1077} 1078 1079/** 1080 * encode_fix - fill up fb_fix_screeninfo structure 1081 * @fix: pointer to fb_fix_screeninfo 1082 * @info: pointer to fb_info 1083 * 1084 * DESCRIPTION: 1085 * This will set up parameters that are unmodifiable by the user. 1086 */ 1087static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info) 1088{ 1089 struct i810fb_par *par = info->par; 1090 1091 memset(fix, 0, sizeof(struct fb_fix_screeninfo)); 1092 1093 strcpy(fix->id, "I810"); 1094 mutex_lock(&info->mm_lock); 1095 fix->smem_start = par->fb.physical; 1096 fix->smem_len = par->fb.size; 1097 mutex_unlock(&info->mm_lock); 1098 fix->type = FB_TYPE_PACKED_PIXELS; 1099 fix->type_aux = 0; 1100 fix->xpanstep = 8; 1101 fix->ypanstep = 1; 1102 1103 switch (info->var.bits_per_pixel) { 1104 case 8: 1105 fix->visual = FB_VISUAL_PSEUDOCOLOR; 1106 break; 1107 case 16: 1108 case 24: 1109 case 32: 1110 if (info->var.nonstd) 1111 fix->visual = FB_VISUAL_DIRECTCOLOR; 1112 else 1113 fix->visual = FB_VISUAL_TRUECOLOR; 1114 break; 1115 default: 1116 return -EINVAL; 1117 } 1118 fix->ywrapstep = 0; 1119 fix->line_length = par->pitch; 1120 fix->mmio_start = par->mmio_start_phys; 1121 fix->mmio_len = MMIO_SIZE; 1122 fix->accel = FB_ACCEL_I810; 1123 1124 return 0; 1125} 1126 1127/** 1128 * decode_var - modify par according to contents of var 1129 * @var: pointer to fb_var_screeninfo 1130 * @par: pointer to i810fb_par 1131 * 1132 * DESCRIPTION: 1133 * Based on the contents of @var, @par will be dynamically filled up. 1134 * @par contains all information necessary to modify the hardware. 1135*/ 1136static void decode_var(const struct fb_var_screeninfo *var, 1137 struct i810fb_par *par) 1138{ 1139 u32 xres, yres, vxres, vyres; 1140 1141 xres = var->xres; 1142 yres = var->yres; 1143 vxres = var->xres_virtual; 1144 vyres = var->yres_virtual; 1145 1146 switch (var->bits_per_pixel) { 1147 case 8: 1148 par->pixconf = PIXCONF8; 1149 par->bltcntl = 0; 1150 par->depth = 1; 1151 par->blit_bpp = BPP8; 1152 break; 1153 case 16: 1154 if (var->green.length == 5) 1155 par->pixconf = PIXCONF15; 1156 else 1157 par->pixconf = PIXCONF16; 1158 par->bltcntl = 16; 1159 par->depth = 2; 1160 par->blit_bpp = BPP16; 1161 break; 1162 case 24: 1163 par->pixconf = PIXCONF24; 1164 par->bltcntl = 32; 1165 par->depth = 3; 1166 par->blit_bpp = BPP24; 1167 break; 1168 case 32: 1169 par->pixconf = PIXCONF32; 1170 par->bltcntl = 0; 1171 par->depth = 4; 1172 par->blit_bpp = 3 << 24; 1173 break; 1174 } 1175 if (var->nonstd && var->bits_per_pixel != 8) 1176 par->pixconf |= 1 << 27; 1177 1178 i810_calc_dclk(var->pixclock, &par->regs.M, 1179 &par->regs.N, &par->regs.P); 1180 i810fb_encode_registers(var, par, xres, yres); 1181 1182 par->watermark = i810_get_watermark(var, par); 1183 par->pitch = get_line_length(par, vxres, var->bits_per_pixel); 1184} 1185 1186/** 1187 * i810fb_getcolreg - gets red, green and blue values of the hardware DAC 1188 * @regno: DAC index 1189 * @red: red 1190 * @green: green 1191 * @blue: blue 1192 * @transp: transparency (alpha) 1193 * @info: pointer to fb_info 1194 * 1195 * DESCRIPTION: 1196 * Gets the red, green and blue values of the hardware DAC as pointed by @regno 1197 * and writes them to @red, @green and @blue respectively 1198 */ 1199static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue, 1200 u8 *transp, struct fb_info *info) 1201{ 1202 struct i810fb_par *par = info->par; 1203 u8 __iomem *mmio = par->mmio_start_virtual; 1204 u8 temp; 1205 1206 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1207 if ((info->var.green.length == 5 && regno > 31) || 1208 (info->var.green.length == 6 && regno > 63)) 1209 return 1; 1210 } 1211 1212 temp = i810_readb(PIXCONF1, mmio); 1213 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); 1214 1215 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && 1216 info->var.green.length == 5) 1217 i810_read_dac(regno * 8, red, green, blue, mmio); 1218 1219 else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && 1220 info->var.green.length == 6) { 1221 u8 tmp; 1222 1223 i810_read_dac(regno * 8, red, &tmp, blue, mmio); 1224 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio); 1225 } 1226 else 1227 i810_read_dac(regno, red, green, blue, mmio); 1228 1229 *transp = 0; 1230 i810_writeb(PIXCONF1, mmio, temp); 1231 1232 return 0; 1233} 1234 1235/****************************************************************** 1236 * Framebuffer device-specific hooks * 1237 ******************************************************************/ 1238 1239static int i810fb_open(struct fb_info *info, int user) 1240{ 1241 struct i810fb_par *par = info->par; 1242 1243 mutex_lock(&par->open_lock); 1244 if (par->use_count == 0) { 1245 memset(&par->state, 0, sizeof(struct vgastate)); 1246 par->state.flags = VGA_SAVE_CMAP; 1247 par->state.vgabase = par->mmio_start_virtual; 1248 save_vga(&par->state); 1249 1250 i810_save_vga_state(par); 1251 } 1252 1253 par->use_count++; 1254 mutex_unlock(&par->open_lock); 1255 1256 return 0; 1257} 1258 1259static int i810fb_release(struct fb_info *info, int user) 1260{ 1261 struct i810fb_par *par = info->par; 1262 1263 mutex_lock(&par->open_lock); 1264 if (par->use_count == 0) { 1265 mutex_unlock(&par->open_lock); 1266 return -EINVAL; 1267 } 1268 1269 if (par->use_count == 1) { 1270 i810_restore_vga_state(par); 1271 restore_vga(&par->state); 1272 } 1273 1274 par->use_count--; 1275 mutex_unlock(&par->open_lock); 1276 1277 return 0; 1278} 1279 1280 1281static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green, 1282 unsigned blue, unsigned transp, 1283 struct fb_info *info) 1284{ 1285 struct i810fb_par *par = info->par; 1286 u8 __iomem *mmio = par->mmio_start_virtual; 1287 u8 temp; 1288 int i; 1289 1290 if (regno > 255) return 1; 1291 1292 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1293 if ((info->var.green.length == 5 && regno > 31) || 1294 (info->var.green.length == 6 && regno > 63)) 1295 return 1; 1296 } 1297 1298 if (info->var.grayscale) 1299 red = green = blue = (19595 * red + 38470 * green + 1300 7471 * blue) >> 16; 1301 1302 temp = i810_readb(PIXCONF1, mmio); 1303 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE); 1304 1305 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && 1306 info->var.green.length == 5) { 1307 for (i = 0; i < 8; i++) 1308 i810_write_dac((u8) (regno * 8) + i, (u8) red, 1309 (u8) green, (u8) blue, mmio); 1310 } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR && 1311 info->var.green.length == 6) { 1312 u8 r, g, b; 1313 1314 if (regno < 32) { 1315 for (i = 0; i < 8; i++) 1316 i810_write_dac((u8) (regno * 8) + i, 1317 (u8) red, (u8) green, 1318 (u8) blue, mmio); 1319 } 1320 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio); 1321 for (i = 0; i < 4; i++) 1322 i810_write_dac((u8) (regno*4) + i, r, (u8) green, 1323 b, mmio); 1324 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { 1325 i810_write_dac((u8) regno, (u8) red, (u8) green, 1326 (u8) blue, mmio); 1327 } 1328 1329 i810_writeb(PIXCONF1, mmio, temp); 1330 1331 if (regno < 16) { 1332 switch (info->var.bits_per_pixel) { 1333 case 16: 1334 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1335 if (info->var.green.length == 5) 1336 ((u32 *)info->pseudo_palette)[regno] = 1337 (regno << 10) | (regno << 5) | 1338 regno; 1339 else 1340 ((u32 *)info->pseudo_palette)[regno] = 1341 (regno << 11) | (regno << 5) | 1342 regno; 1343 } else { 1344 if (info->var.green.length == 5) { 1345 /* RGB 555 */ 1346 ((u32 *)info->pseudo_palette)[regno] = 1347 ((red & 0xf800) >> 1) | 1348 ((green & 0xf800) >> 6) | 1349 ((blue & 0xf800) >> 11); 1350 } else { 1351 /* RGB 565 */ 1352 ((u32 *)info->pseudo_palette)[regno] = 1353 (red & 0xf800) | 1354 ((green & 0xf800) >> 5) | 1355 ((blue & 0xf800) >> 11); 1356 } 1357 } 1358 break; 1359 case 24: /* RGB 888 */ 1360 case 32: /* RGBA 8888 */ 1361 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) 1362 ((u32 *)info->pseudo_palette)[regno] = 1363 (regno << 16) | (regno << 8) | 1364 regno; 1365 else 1366 ((u32 *)info->pseudo_palette)[regno] = 1367 ((red & 0xff00) << 8) | 1368 (green & 0xff00) | 1369 ((blue & 0xff00) >> 8); 1370 break; 1371 } 1372 } 1373 return 0; 1374} 1375 1376static int i810fb_pan_display(struct fb_var_screeninfo *var, 1377 struct fb_info *info) 1378{ 1379 struct i810fb_par *par = info->par; 1380 u32 total; 1381 1382 total = var->xoffset * par->depth + 1383 var->yoffset * info->fix.line_length; 1384 i810fb_load_front(total, info); 1385 1386 return 0; 1387} 1388 1389static int i810fb_blank (int blank_mode, struct fb_info *info) 1390{ 1391 struct i810fb_par *par = info->par; 1392 u8 __iomem *mmio = par->mmio_start_virtual; 1393 int mode = 0, pwr, scr_off = 0; 1394 1395 pwr = i810_readl(PWR_CLKC, mmio); 1396 1397 switch (blank_mode) { 1398 case FB_BLANK_UNBLANK: 1399 mode = POWERON; 1400 pwr |= 1; 1401 scr_off = ON; 1402 break; 1403 case FB_BLANK_NORMAL: 1404 mode = POWERON; 1405 pwr |= 1; 1406 scr_off = OFF; 1407 break; 1408 case FB_BLANK_VSYNC_SUSPEND: 1409 mode = STANDBY; 1410 pwr |= 1; 1411 scr_off = OFF; 1412 break; 1413 case FB_BLANK_HSYNC_SUSPEND: 1414 mode = SUSPEND; 1415 pwr |= 1; 1416 scr_off = OFF; 1417 break; 1418 case FB_BLANK_POWERDOWN: 1419 mode = POWERDOWN; 1420 pwr &= ~1; 1421 scr_off = OFF; 1422 break; 1423 default: 1424 return -EINVAL; 1425 } 1426 1427 i810_screen_off(mmio, scr_off); 1428 i810_writel(HVSYNC, mmio, mode); 1429 i810_writel(PWR_CLKC, mmio, pwr); 1430 1431 return 0; 1432} 1433 1434static int i810fb_set_par(struct fb_info *info) 1435{ 1436 struct i810fb_par *par = info->par; 1437 1438 decode_var(&info->var, par); 1439 i810_load_regs(par); 1440 i810_init_cursor(par); 1441 encode_fix(&info->fix, info); 1442 1443 if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) { 1444 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN | 1445 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | 1446 FBINFO_HWACCEL_IMAGEBLIT; 1447 info->pixmap.scan_align = 2; 1448 } else { 1449 info->pixmap.scan_align = 1; 1450 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1451 } 1452 return 0; 1453} 1454 1455static int i810fb_check_var(struct fb_var_screeninfo *var, 1456 struct fb_info *info) 1457{ 1458 int err; 1459 1460 if (IS_DVT) { 1461 var->vmode &= ~FB_VMODE_MASK; 1462 var->vmode |= FB_VMODE_NONINTERLACED; 1463 } 1464 if (var->vmode & FB_VMODE_DOUBLE) { 1465 var->vmode &= ~FB_VMODE_MASK; 1466 var->vmode |= FB_VMODE_NONINTERLACED; 1467 } 1468 1469 i810_round_off(var); 1470 if ((err = i810_check_params(var, info))) 1471 return err; 1472 1473 i810fb_fill_var_timings(var); 1474 set_color_bitfields(var); 1475 return 0; 1476} 1477 1478static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1479{ 1480 struct i810fb_par *par = info->par; 1481 u8 __iomem *mmio = par->mmio_start_virtual; 1482 1483 if (par->dev_flags & LOCKUP) 1484 return -ENXIO; 1485 1486 if (cursor->image.width > 64 || cursor->image.height > 64) 1487 return -ENXIO; 1488 1489 if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) { 1490 i810_init_cursor(par); 1491 cursor->set |= FB_CUR_SETALL; 1492 } 1493 1494 i810_enable_cursor(mmio, OFF); 1495 1496 if (cursor->set & FB_CUR_SETPOS) { 1497 u32 tmp; 1498 1499 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff; 1500 tmp |= (cursor->image.dy - info->var.yoffset) << 16; 1501 i810_writel(CURPOS, mmio, tmp); 1502 } 1503 1504 if (cursor->set & FB_CUR_SETSIZE) 1505 i810_reset_cursor_image(par); 1506 1507 if (cursor->set & FB_CUR_SETCMAP) 1508 i810_load_cursor_colors(cursor->image.fg_color, 1509 cursor->image.bg_color, 1510 info); 1511 1512 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { 1513 int size = ((cursor->image.width + 7) >> 3) * 1514 cursor->image.height; 1515 int i; 1516 u8 *data = kmalloc(64 * 8, GFP_ATOMIC); 1517 1518 if (data == NULL) 1519 return -ENOMEM; 1520 1521 switch (cursor->rop) { 1522 case ROP_XOR: 1523 for (i = 0; i < size; i++) 1524 data[i] = cursor->image.data[i] ^ cursor->mask[i]; 1525 break; 1526 case ROP_COPY: 1527 default: 1528 for (i = 0; i < size; i++) 1529 data[i] = cursor->image.data[i] & cursor->mask[i]; 1530 break; 1531 } 1532 1533 i810_load_cursor_image(cursor->image.width, 1534 cursor->image.height, data, 1535 par); 1536 kfree(data); 1537 } 1538 1539 if (cursor->enable) 1540 i810_enable_cursor(mmio, ON); 1541 1542 return 0; 1543} 1544 1545static const struct fb_ops i810fb_ops = { 1546 .owner = THIS_MODULE, 1547 .fb_open = i810fb_open, 1548 .fb_release = i810fb_release, 1549 .fb_check_var = i810fb_check_var, 1550 .fb_set_par = i810fb_set_par, 1551 .fb_setcolreg = i810fb_setcolreg, 1552 .fb_blank = i810fb_blank, 1553 .fb_pan_display = i810fb_pan_display, 1554 .fb_fillrect = i810fb_fillrect, 1555 .fb_copyarea = i810fb_copyarea, 1556 .fb_imageblit = i810fb_imageblit, 1557 .fb_cursor = i810fb_cursor, 1558 .fb_sync = i810fb_sync, 1559}; 1560 1561/*********************************************************************** 1562 * Power Management * 1563 ***********************************************************************/ 1564static int i810fb_suspend(struct pci_dev *dev, pm_message_t mesg) 1565{ 1566 struct fb_info *info = pci_get_drvdata(dev); 1567 struct i810fb_par *par = info->par; 1568 1569 par->cur_state = mesg.event; 1570 1571 switch (mesg.event) { 1572 case PM_EVENT_FREEZE: 1573 case PM_EVENT_PRETHAW: 1574 dev->dev.power.power_state = mesg; 1575 return 0; 1576 } 1577 1578 console_lock(); 1579 fb_set_suspend(info, 1); 1580 1581 if (info->fbops->fb_sync) 1582 info->fbops->fb_sync(info); 1583 1584 i810fb_blank(FB_BLANK_POWERDOWN, info); 1585 agp_unbind_memory(par->i810_gtt.i810_fb_memory); 1586 agp_unbind_memory(par->i810_gtt.i810_cursor_memory); 1587 1588 pci_save_state(dev); 1589 pci_disable_device(dev); 1590 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1591 console_unlock(); 1592 1593 return 0; 1594} 1595 1596static int i810fb_resume(struct pci_dev *dev) 1597{ 1598 struct fb_info *info = pci_get_drvdata(dev); 1599 struct i810fb_par *par = info->par; 1600 int cur_state = par->cur_state; 1601 1602 par->cur_state = PM_EVENT_ON; 1603 1604 if (cur_state == PM_EVENT_FREEZE) { 1605 pci_set_power_state(dev, PCI_D0); 1606 return 0; 1607 } 1608 1609 console_lock(); 1610 pci_set_power_state(dev, PCI_D0); 1611 pci_restore_state(dev); 1612 1613 if (pci_enable_device(dev)) 1614 goto fail; 1615 1616 pci_set_master(dev); 1617 agp_bind_memory(par->i810_gtt.i810_fb_memory, 1618 par->fb.offset); 1619 agp_bind_memory(par->i810_gtt.i810_cursor_memory, 1620 par->cursor_heap.offset); 1621 i810fb_set_par(info); 1622 fb_set_suspend (info, 0); 1623 info->fbops->fb_blank(VESA_NO_BLANKING, info); 1624fail: 1625 console_unlock(); 1626 return 0; 1627} 1628/*********************************************************************** 1629 * AGP resource allocation * 1630 ***********************************************************************/ 1631 1632static void i810_fix_pointers(struct i810fb_par *par) 1633{ 1634 par->fb.physical = par->aperture.physical+(par->fb.offset << 12); 1635 par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12); 1636 par->iring.physical = par->aperture.physical + 1637 (par->iring.offset << 12); 1638 par->iring.virtual = par->aperture.virtual + 1639 (par->iring.offset << 12); 1640 par->cursor_heap.virtual = par->aperture.virtual+ 1641 (par->cursor_heap.offset << 12); 1642} 1643 1644static void i810_fix_offsets(struct i810fb_par *par) 1645{ 1646 if (vram + 1 > par->aperture.size >> 20) 1647 vram = (par->aperture.size >> 20) - 1; 1648 if (v_offset_default > (par->aperture.size >> 20)) 1649 v_offset_default = (par->aperture.size >> 20); 1650 if (vram + v_offset_default + 1 > par->aperture.size >> 20) 1651 v_offset_default = (par->aperture.size >> 20) - (vram + 1); 1652 1653 par->fb.size = vram << 20; 1654 par->fb.offset = v_offset_default << 20; 1655 par->fb.offset >>= 12; 1656 1657 par->iring.offset = par->fb.offset + (par->fb.size >> 12); 1658 par->iring.size = RINGBUFFER_SIZE; 1659 1660 par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12); 1661 par->cursor_heap.size = 4096; 1662} 1663 1664static int i810_alloc_agp_mem(struct fb_info *info) 1665{ 1666 struct i810fb_par *par = info->par; 1667 int size; 1668 struct agp_bridge_data *bridge; 1669 1670 i810_fix_offsets(par); 1671 size = par->fb.size + par->iring.size; 1672 1673 if (!(bridge = agp_backend_acquire(par->dev))) { 1674 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n"); 1675 return -ENODEV; 1676 } 1677 if (!(par->i810_gtt.i810_fb_memory = 1678 agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) { 1679 printk("i810fb_alloc_fbmem: can't allocate framebuffer " 1680 "memory\n"); 1681 agp_backend_release(bridge); 1682 return -ENOMEM; 1683 } 1684 if (agp_bind_memory(par->i810_gtt.i810_fb_memory, 1685 par->fb.offset)) { 1686 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n"); 1687 agp_backend_release(bridge); 1688 return -EBUSY; 1689 } 1690 1691 if (!(par->i810_gtt.i810_cursor_memory = 1692 agp_allocate_memory(bridge, par->cursor_heap.size >> 12, 1693 AGP_PHYSICAL_MEMORY))) { 1694 printk("i810fb_alloc_cursormem: can't allocate " 1695 "cursor memory\n"); 1696 agp_backend_release(bridge); 1697 return -ENOMEM; 1698 } 1699 if (agp_bind_memory(par->i810_gtt.i810_cursor_memory, 1700 par->cursor_heap.offset)) { 1701 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n"); 1702 agp_backend_release(bridge); 1703 return -EBUSY; 1704 } 1705 1706 par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical; 1707 1708 i810_fix_pointers(par); 1709 1710 agp_backend_release(bridge); 1711 1712 return 0; 1713} 1714 1715/*************************************************************** 1716 * Initialization * 1717 ***************************************************************/ 1718 1719/** 1720 * i810_init_monspecs 1721 * @info: pointer to device specific info structure 1722 * 1723 * DESCRIPTION: 1724 * Sets the user monitor's horizontal and vertical 1725 * frequency limits 1726 */ 1727static void i810_init_monspecs(struct fb_info *info) 1728{ 1729 if (!hsync1) 1730 hsync1 = HFMIN; 1731 if (!hsync2) 1732 hsync2 = HFMAX; 1733 if (!info->monspecs.hfmax) 1734 info->monspecs.hfmax = hsync2; 1735 if (!info->monspecs.hfmin) 1736 info->monspecs.hfmin = hsync1; 1737 if (hsync2 < hsync1) 1738 info->monspecs.hfmin = hsync2; 1739 1740 if (!vsync1) 1741 vsync1 = VFMIN; 1742 if (!vsync2) 1743 vsync2 = VFMAX; 1744 if (IS_DVT && vsync1 < 60) 1745 vsync1 = 60; 1746 if (!info->monspecs.vfmax) 1747 info->monspecs.vfmax = vsync2; 1748 if (!info->monspecs.vfmin) 1749 info->monspecs.vfmin = vsync1; 1750 if (vsync2 < vsync1) 1751 info->monspecs.vfmin = vsync2; 1752} 1753 1754/** 1755 * i810_init_defaults - initializes default values to use 1756 * @par: pointer to i810fb_par structure 1757 * @info: pointer to current fb_info structure 1758 */ 1759static void i810_init_defaults(struct i810fb_par *par, struct fb_info *info) 1760{ 1761 mutex_init(&par->open_lock); 1762 1763 if (voffset) 1764 v_offset_default = voffset; 1765 else if (par->aperture.size > 32 * 1024 * 1024) 1766 v_offset_default = 16; 1767 else 1768 v_offset_default = 8; 1769 1770 if (!vram) 1771 vram = 1; 1772 1773 if (accel) 1774 par->dev_flags |= HAS_ACCELERATION; 1775 1776 if (sync) 1777 par->dev_flags |= ALWAYS_SYNC; 1778 1779 par->ddc_num = (ddc3 ? 3 : 2); 1780 1781 if (bpp < 8) 1782 bpp = 8; 1783 1784 par->i810fb_ops = i810fb_ops; 1785 1786 if (xres) 1787 info->var.xres = xres; 1788 else 1789 info->var.xres = 640; 1790 1791 if (yres) 1792 info->var.yres = yres; 1793 else 1794 info->var.yres = 480; 1795 1796 if (!vyres) 1797 vyres = (vram << 20)/(info->var.xres*bpp >> 3); 1798 1799 info->var.yres_virtual = vyres; 1800 info->var.bits_per_pixel = bpp; 1801 1802 if (dcolor) 1803 info->var.nonstd = 1; 1804 1805 if (par->dev_flags & HAS_ACCELERATION) 1806 info->var.accel_flags = 1; 1807 1808 i810_init_monspecs(info); 1809} 1810 1811/** 1812 * i810_init_device - initialize device 1813 * @par: pointer to i810fb_par structure 1814 */ 1815static void i810_init_device(struct i810fb_par *par) 1816{ 1817 u8 reg; 1818 u8 __iomem *mmio = par->mmio_start_virtual; 1819 1820 if (mtrr) 1821 par->wc_cookie= arch_phys_wc_add((u32) par->aperture.physical, 1822 par->aperture.size); 1823 1824 i810_init_cursor(par); 1825 1826 /* mvo: enable external vga-connector (for laptops) */ 1827 if (extvga) { 1828 i810_writel(HVSYNC, mmio, 0); 1829 i810_writel(PWR_CLKC, mmio, 3); 1830 } 1831 1832 pci_read_config_byte(par->dev, 0x50, ®); 1833 reg &= FREQ_MASK; 1834 par->mem_freq = (reg) ? 133 : 100; 1835 1836} 1837 1838static int i810_allocate_pci_resource(struct i810fb_par *par, 1839 const struct pci_device_id *entry) 1840{ 1841 int err; 1842 1843 if ((err = pci_enable_device(par->dev))) { 1844 printk("i810fb_init: cannot enable device\n"); 1845 return err; 1846 } 1847 par->res_flags |= PCI_DEVICE_ENABLED; 1848 1849 if (pci_resource_len(par->dev, 0) > 512 * 1024) { 1850 par->aperture.physical = pci_resource_start(par->dev, 0); 1851 par->aperture.size = pci_resource_len(par->dev, 0); 1852 par->mmio_start_phys = pci_resource_start(par->dev, 1); 1853 } else { 1854 par->aperture.physical = pci_resource_start(par->dev, 1); 1855 par->aperture.size = pci_resource_len(par->dev, 1); 1856 par->mmio_start_phys = pci_resource_start(par->dev, 0); 1857 } 1858 if (!par->aperture.size) { 1859 printk("i810fb_init: device is disabled\n"); 1860 return -ENOMEM; 1861 } 1862 1863 if (!request_mem_region(par->aperture.physical, 1864 par->aperture.size, 1865 i810_pci_list[entry->driver_data])) { 1866 printk("i810fb_init: cannot request framebuffer region\n"); 1867 return -ENODEV; 1868 } 1869 par->res_flags |= FRAMEBUFFER_REQ; 1870 1871 par->aperture.virtual = ioremap_wc(par->aperture.physical, 1872 par->aperture.size); 1873 if (!par->aperture.virtual) { 1874 printk("i810fb_init: cannot remap framebuffer region\n"); 1875 return -ENODEV; 1876 } 1877 1878 if (!request_mem_region(par->mmio_start_phys, 1879 MMIO_SIZE, 1880 i810_pci_list[entry->driver_data])) { 1881 printk("i810fb_init: cannot request mmio region\n"); 1882 return -ENODEV; 1883 } 1884 par->res_flags |= MMIO_REQ; 1885 1886 par->mmio_start_virtual = ioremap(par->mmio_start_phys, 1887 MMIO_SIZE); 1888 if (!par->mmio_start_virtual) { 1889 printk("i810fb_init: cannot remap mmio region\n"); 1890 return -ENODEV; 1891 } 1892 1893 return 0; 1894} 1895 1896static void i810fb_find_init_mode(struct fb_info *info) 1897{ 1898 struct fb_videomode mode; 1899 struct fb_var_screeninfo var; 1900 struct fb_monspecs *specs = &info->monspecs; 1901 int found = 0; 1902#ifdef CONFIG_FB_I810_I2C 1903 int i; 1904 int err = 1; 1905 struct i810fb_par *par = info->par; 1906#endif 1907 1908 INIT_LIST_HEAD(&info->modelist); 1909 memset(&mode, 0, sizeof(struct fb_videomode)); 1910 var = info->var; 1911#ifdef CONFIG_FB_I810_I2C 1912 i810_create_i2c_busses(par); 1913 1914 for (i = 0; i < par->ddc_num + 1; i++) { 1915 err = i810_probe_i2c_connector(info, &par->edid, i); 1916 if (!err) 1917 break; 1918 } 1919 1920 if (!err) 1921 printk("i810fb_init_pci: DDC probe successful\n"); 1922 1923 fb_edid_to_monspecs(par->edid, specs); 1924 1925 if (specs->modedb == NULL) 1926 printk("i810fb_init_pci: Unable to get Mode Database\n"); 1927 1928 fb_videomode_to_modelist(specs->modedb, specs->modedb_len, 1929 &info->modelist); 1930 if (specs->modedb != NULL) { 1931 const struct fb_videomode *m; 1932 1933 if (xres && yres) { 1934 if ((m = fb_find_best_mode(&var, &info->modelist))) { 1935 mode = *m; 1936 found = 1; 1937 } 1938 } 1939 1940 if (!found) { 1941 m = fb_find_best_display(&info->monspecs, &info->modelist); 1942 mode = *m; 1943 found = 1; 1944 } 1945 1946 fb_videomode_to_var(&var, &mode); 1947 } 1948#endif 1949 if (mode_option) 1950 fb_find_mode(&var, info, mode_option, specs->modedb, 1951 specs->modedb_len, (found) ? &mode : NULL, 1952 info->var.bits_per_pixel); 1953 1954 info->var = var; 1955 fb_destroy_modedb(specs->modedb); 1956 specs->modedb = NULL; 1957} 1958 1959#ifndef MODULE 1960static int i810fb_setup(char *options) 1961{ 1962 char *this_opt, *suffix = NULL; 1963 1964 if (!options || !*options) 1965 return 0; 1966 1967 while ((this_opt = strsep(&options, ",")) != NULL) { 1968 if (!strncmp(this_opt, "mtrr", 4)) 1969 mtrr = true; 1970 else if (!strncmp(this_opt, "accel", 5)) 1971 accel = true; 1972 else if (!strncmp(this_opt, "extvga", 6)) 1973 extvga = true; 1974 else if (!strncmp(this_opt, "sync", 4)) 1975 sync = true; 1976 else if (!strncmp(this_opt, "vram:", 5)) 1977 vram = (simple_strtoul(this_opt+5, NULL, 0)); 1978 else if (!strncmp(this_opt, "voffset:", 8)) 1979 voffset = (simple_strtoul(this_opt+8, NULL, 0)); 1980 else if (!strncmp(this_opt, "xres:", 5)) 1981 xres = simple_strtoul(this_opt+5, NULL, 0); 1982 else if (!strncmp(this_opt, "yres:", 5)) 1983 yres = simple_strtoul(this_opt+5, NULL, 0); 1984 else if (!strncmp(this_opt, "vyres:", 6)) 1985 vyres = simple_strtoul(this_opt+6, NULL, 0); 1986 else if (!strncmp(this_opt, "bpp:", 4)) 1987 bpp = simple_strtoul(this_opt+4, NULL, 0); 1988 else if (!strncmp(this_opt, "hsync1:", 7)) { 1989 hsync1 = simple_strtoul(this_opt+7, &suffix, 0); 1990 if (strncmp(suffix, "H", 1)) 1991 hsync1 *= 1000; 1992 } else if (!strncmp(this_opt, "hsync2:", 7)) { 1993 hsync2 = simple_strtoul(this_opt+7, &suffix, 0); 1994 if (strncmp(suffix, "H", 1)) 1995 hsync2 *= 1000; 1996 } else if (!strncmp(this_opt, "vsync1:", 7)) 1997 vsync1 = simple_strtoul(this_opt+7, NULL, 0); 1998 else if (!strncmp(this_opt, "vsync2:", 7)) 1999 vsync2 = simple_strtoul(this_opt+7, NULL, 0); 2000 else if (!strncmp(this_opt, "dcolor", 6)) 2001 dcolor = true; 2002 else if (!strncmp(this_opt, "ddc3", 4)) 2003 ddc3 = true; 2004 else 2005 mode_option = this_opt; 2006 } 2007 return 0; 2008} 2009#endif 2010 2011static int i810fb_init_pci(struct pci_dev *dev, 2012 const struct pci_device_id *entry) 2013{ 2014 struct fb_info *info; 2015 struct i810fb_par *par = NULL; 2016 struct fb_videomode mode; 2017 int err = -1, vfreq, hfreq, pixclock; 2018 2019 info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev); 2020 if (!info) 2021 return -ENOMEM; 2022 2023 par = info->par; 2024 par->dev = dev; 2025 2026 if (!(info->pixmap.addr = kzalloc(8*1024, GFP_KERNEL))) { 2027 i810fb_release_resource(info, par); 2028 return -ENOMEM; 2029 } 2030 info->pixmap.size = 8*1024; 2031 info->pixmap.buf_align = 8; 2032 info->pixmap.access_align = 32; 2033 info->pixmap.flags = FB_PIXMAP_SYSTEM; 2034 2035 if ((err = i810_allocate_pci_resource(par, entry))) { 2036 i810fb_release_resource(info, par); 2037 return err; 2038 } 2039 2040 i810_init_defaults(par, info); 2041 2042 if ((err = i810_alloc_agp_mem(info))) { 2043 i810fb_release_resource(info, par); 2044 return err; 2045 } 2046 2047 i810_init_device(par); 2048 2049 info->screen_base = par->fb.virtual; 2050 info->fbops = &par->i810fb_ops; 2051 info->pseudo_palette = par->pseudo_palette; 2052 fb_alloc_cmap(&info->cmap, 256, 0); 2053 i810fb_find_init_mode(info); 2054 2055 if ((err = info->fbops->fb_check_var(&info->var, info))) { 2056 i810fb_release_resource(info, par); 2057 return err; 2058 } 2059 2060 fb_var_to_videomode(&mode, &info->var); 2061 fb_add_videomode(&mode, &info->modelist); 2062 2063 i810fb_init_ringbuffer(info); 2064 err = register_framebuffer(info); 2065 2066 if (err < 0) { 2067 i810fb_release_resource(info, par); 2068 printk("i810fb_init: cannot register framebuffer device\n"); 2069 return err; 2070 } 2071 2072 pci_set_drvdata(dev, info); 2073 pixclock = 1000000000/(info->var.pixclock); 2074 pixclock *= 1000; 2075 hfreq = pixclock/(info->var.xres + info->var.left_margin + 2076 info->var.hsync_len + info->var.right_margin); 2077 vfreq = hfreq/(info->var.yres + info->var.upper_margin + 2078 info->var.vsync_len + info->var.lower_margin); 2079 2080 printk("I810FB: fb%d : %s v%d.%d.%d%s\n" 2081 "I810FB: Video RAM : %dK\n" 2082 "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n" 2083 "I810FB: Mode : %dx%d-%dbpp@%dHz\n", 2084 info->node, 2085 i810_pci_list[entry->driver_data], 2086 VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION, 2087 (int) par->fb.size>>10, info->monspecs.hfmin/1000, 2088 info->monspecs.hfmax/1000, info->monspecs.vfmin, 2089 info->monspecs.vfmax, info->var.xres, 2090 info->var.yres, info->var.bits_per_pixel, vfreq); 2091 return 0; 2092} 2093 2094/*************************************************************** 2095 * De-initialization * 2096 ***************************************************************/ 2097 2098static void i810fb_release_resource(struct fb_info *info, 2099 struct i810fb_par *par) 2100{ 2101 struct gtt_data *gtt = &par->i810_gtt; 2102 arch_phys_wc_del(par->wc_cookie); 2103 2104 i810_delete_i2c_busses(par); 2105 2106 if (par->i810_gtt.i810_cursor_memory) 2107 agp_free_memory(gtt->i810_cursor_memory); 2108 if (par->i810_gtt.i810_fb_memory) 2109 agp_free_memory(gtt->i810_fb_memory); 2110 2111 if (par->mmio_start_virtual) 2112 iounmap(par->mmio_start_virtual); 2113 if (par->aperture.virtual) 2114 iounmap(par->aperture.virtual); 2115 kfree(par->edid); 2116 if (par->res_flags & FRAMEBUFFER_REQ) 2117 release_mem_region(par->aperture.physical, 2118 par->aperture.size); 2119 if (par->res_flags & MMIO_REQ) 2120 release_mem_region(par->mmio_start_phys, MMIO_SIZE); 2121 2122 framebuffer_release(info); 2123 2124} 2125 2126static void i810fb_remove_pci(struct pci_dev *dev) 2127{ 2128 struct fb_info *info = pci_get_drvdata(dev); 2129 struct i810fb_par *par = info->par; 2130 2131 unregister_framebuffer(info); 2132 i810fb_release_resource(info, par); 2133 printk("cleanup_module: unloaded i810 framebuffer device\n"); 2134} 2135 2136#ifndef MODULE 2137static int i810fb_init(void) 2138{ 2139 char *option = NULL; 2140 2141 if (fb_get_options("i810fb", &option)) 2142 return -ENODEV; 2143 i810fb_setup(option); 2144 2145 return pci_register_driver(&i810fb_driver); 2146} 2147#endif 2148 2149/********************************************************************* 2150 * Modularization * 2151 *********************************************************************/ 2152 2153#ifdef MODULE 2154 2155static int i810fb_init(void) 2156{ 2157 hsync1 *= 1000; 2158 hsync2 *= 1000; 2159 2160 return pci_register_driver(&i810fb_driver); 2161} 2162 2163module_param(vram, int, 0); 2164MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB" 2165 " (default=4)"); 2166module_param(voffset, int, 0); 2167MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer " 2168 "memory (0 to maximum aperture size), in MiB (default = 48)"); 2169module_param(bpp, int, 0); 2170MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel" 2171 " (default = 8)"); 2172module_param(xres, int, 0); 2173MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)"); 2174module_param(yres, int, 0); 2175MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)"); 2176module_param(vyres,int, 0); 2177MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines" 2178 " (default = 480)"); 2179module_param(hsync1, int, 0); 2180MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz" 2181 " (default = 29)"); 2182module_param(hsync2, int, 0); 2183MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz" 2184 " (default = 30)"); 2185module_param(vsync1, int, 0); 2186MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz" 2187 " (default = 50)"); 2188module_param(vsync2, int, 0); 2189MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz" 2190 " (default = 60)"); 2191module_param(accel, bool, 0); 2192MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)"); 2193module_param(mtrr, bool, 0); 2194MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)"); 2195module_param(extvga, bool, 0); 2196MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)"); 2197module_param(sync, bool, 0); 2198MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing" 2199 " (default = 0)"); 2200module_param(dcolor, bool, 0); 2201MODULE_PARM_DESC(dcolor, "use DirectColor visuals" 2202 " (default = 0 = TrueColor)"); 2203module_param(ddc3, bool, 0); 2204MODULE_PARM_DESC(ddc3, "Probe DDC bus 3 (default = 0 = no)"); 2205module_param(mode_option, charp, 0); 2206MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 2207 2208MODULE_AUTHOR("Tony A. Daplas"); 2209MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and" 2210 " compatible cards"); 2211MODULE_LICENSE("GPL"); 2212 2213static void __exit i810fb_exit(void) 2214{ 2215 pci_unregister_driver(&i810fb_driver); 2216} 2217module_exit(i810fb_exit); 2218 2219#endif /* MODULE */ 2220 2221module_init(i810fb_init); 2222