1// SPDX-License-Identifier: GPL-2.0-only 2/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ 3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 4 * 5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 6 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 7 * 8 * Ani Joshi / Jeff Garzik 9 * - Code cleanup 10 * 11 * Michel Danzer <michdaen@iiic.ethz.ch> 12 * - 15/16 bit cleanup 13 * - fix panning 14 * 15 * Benjamin Herrenschmidt 16 * - pmac-specific PM stuff 17 * - various fixes & cleanups 18 * 19 * Andreas Hundt <andi@convergence.de> 20 * - FB_ACTIVATE fixes 21 * 22 * Paul Mackerras <paulus@samba.org> 23 * - Convert to new framebuffer API, 24 * fix colormap setting at 16 bits/pixel (565) 25 * 26 * Paul Mundt 27 * - PCI hotplug 28 * 29 * Jon Smirl <jonsmirl@yahoo.com> 30 * - PCI ID update 31 * - replace ROM BIOS search 32 * 33 * Based off of Geert's atyfb.c and vfb.c. 34 * 35 * TODO: 36 * - monitor sensing (DDC) 37 * - virtual display 38 * - other platform support (only ppc/x86 supported) 39 * - hardware cursor support 40 * 41 * Please cc: your patches to brad@neruo.com. 42 */ 43 44/* 45 * A special note of gratitude to ATI's devrel for providing documentation, 46 * example code and hardware. Thanks Nitya. -atong and brad 47 */ 48 49 50#include <linux/module.h> 51#include <linux/moduleparam.h> 52#include <linux/kernel.h> 53#include <linux/errno.h> 54#include <linux/string.h> 55#include <linux/mm.h> 56#include <linux/vmalloc.h> 57#include <linux/delay.h> 58#include <linux/interrupt.h> 59#include <linux/uaccess.h> 60#include <linux/fb.h> 61#include <linux/init.h> 62#include <linux/pci.h> 63#include <linux/ioport.h> 64#include <linux/console.h> 65#include <linux/backlight.h> 66#include <asm/io.h> 67 68#ifdef CONFIG_PPC_PMAC 69#include <asm/machdep.h> 70#include <asm/pmac_feature.h> 71#include <asm/prom.h> 72#include "../macmodes.h" 73#endif 74 75#ifdef CONFIG_PMAC_BACKLIGHT 76#include <asm/backlight.h> 77#endif 78 79#ifdef CONFIG_BOOTX_TEXT 80#include <asm/btext.h> 81#endif /* CONFIG_BOOTX_TEXT */ 82 83#include <video/aty128.h> 84 85/* Debug flag */ 86#undef DEBUG 87 88#ifdef DEBUG 89#define DBG(fmt, args...) \ 90 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); 91#else 92#define DBG(fmt, args...) 93#endif 94 95#ifndef CONFIG_PPC_PMAC 96/* default mode */ 97static const struct fb_var_screeninfo default_var = { 98 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 99 640, 480, 640, 480, 0, 0, 8, 0, 100 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 101 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 102 0, FB_VMODE_NONINTERLACED 103}; 104 105#else /* CONFIG_PPC_PMAC */ 106/* default to 1024x768 at 75Hz on PPC - this will work 107 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 108static const struct fb_var_screeninfo default_var = { 109 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 110 1024, 768, 1024, 768, 0, 0, 8, 0, 111 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 112 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 113 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 114 FB_VMODE_NONINTERLACED 115}; 116#endif /* CONFIG_PPC_PMAC */ 117 118/* default modedb mode */ 119/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 120static const struct fb_videomode defaultmode = { 121 .refresh = 60, 122 .xres = 640, 123 .yres = 480, 124 .pixclock = 39722, 125 .left_margin = 48, 126 .right_margin = 16, 127 .upper_margin = 33, 128 .lower_margin = 10, 129 .hsync_len = 96, 130 .vsync_len = 2, 131 .sync = 0, 132 .vmode = FB_VMODE_NONINTERLACED 133}; 134 135/* Chip generations */ 136enum { 137 rage_128, 138 rage_128_pci, 139 rage_128_pro, 140 rage_128_pro_pci, 141 rage_M3, 142 rage_M3_pci, 143 rage_M4, 144 rage_128_ultra, 145}; 146 147/* Must match above enum */ 148static char * const r128_family[] = { 149 "AGP", 150 "PCI", 151 "PRO AGP", 152 "PRO PCI", 153 "M3 AGP", 154 "M3 PCI", 155 "M4 AGP", 156 "Ultra AGP", 157}; 158 159/* 160 * PCI driver prototypes 161 */ 162static int aty128_probe(struct pci_dev *pdev, 163 const struct pci_device_id *ent); 164static void aty128_remove(struct pci_dev *pdev); 165static int aty128_pci_suspend_late(struct device *dev, pm_message_t state); 166static int __maybe_unused aty128_pci_suspend(struct device *dev); 167static int __maybe_unused aty128_pci_hibernate(struct device *dev); 168static int __maybe_unused aty128_pci_freeze(struct device *dev); 169static int __maybe_unused aty128_pci_resume(struct device *dev); 170static int aty128_do_resume(struct pci_dev *pdev); 171 172static const struct dev_pm_ops aty128_pci_pm_ops = { 173 .suspend = aty128_pci_suspend, 174 .resume = aty128_pci_resume, 175 .freeze = aty128_pci_freeze, 176 .thaw = aty128_pci_resume, 177 .poweroff = aty128_pci_hibernate, 178 .restore = aty128_pci_resume, 179}; 180 181/* supported Rage128 chipsets */ 182static const struct pci_device_id aty128_pci_tbl[] = { 183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 269 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 271 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 273 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 275 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 277 { 0, } 278}; 279 280MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 281 282static struct pci_driver aty128fb_driver = { 283 .name = "aty128fb", 284 .id_table = aty128_pci_tbl, 285 .probe = aty128_probe, 286 .remove = aty128_remove, 287 .driver.pm = &aty128_pci_pm_ops, 288}; 289 290/* packed BIOS settings */ 291#ifndef CONFIG_PPC 292typedef struct { 293 u8 clock_chip_type; 294 u8 struct_size; 295 u8 accelerator_entry; 296 u8 VGA_entry; 297 u16 VGA_table_offset; 298 u16 POST_table_offset; 299 u16 XCLK; 300 u16 MCLK; 301 u8 num_PLL_blocks; 302 u8 size_PLL_blocks; 303 u16 PCLK_ref_freq; 304 u16 PCLK_ref_divider; 305 u32 PCLK_min_freq; 306 u32 PCLK_max_freq; 307 u16 MCLK_ref_freq; 308 u16 MCLK_ref_divider; 309 u32 MCLK_min_freq; 310 u32 MCLK_max_freq; 311 u16 XCLK_ref_freq; 312 u16 XCLK_ref_divider; 313 u32 XCLK_min_freq; 314 u32 XCLK_max_freq; 315} __attribute__ ((packed)) PLL_BLOCK; 316#endif /* !CONFIG_PPC */ 317 318/* onboard memory information */ 319struct aty128_meminfo { 320 u8 ML; 321 u8 MB; 322 u8 Trcd; 323 u8 Trp; 324 u8 Twr; 325 u8 CL; 326 u8 Tr2w; 327 u8 LoopLatency; 328 u8 DspOn; 329 u8 Rloop; 330 const char *name; 331}; 332 333/* various memory configurations */ 334static const struct aty128_meminfo sdr_128 = { 335 .ML = 4, 336 .MB = 4, 337 .Trcd = 3, 338 .Trp = 3, 339 .Twr = 1, 340 .CL = 3, 341 .Tr2w = 1, 342 .LoopLatency = 16, 343 .DspOn = 30, 344 .Rloop = 16, 345 .name = "128-bit SDR SGRAM (1:1)", 346}; 347 348static const struct aty128_meminfo sdr_sgram = { 349 .ML = 4, 350 .MB = 4, 351 .Trcd = 1, 352 .Trp = 2, 353 .Twr = 1, 354 .CL = 2, 355 .Tr2w = 1, 356 .LoopLatency = 16, 357 .DspOn = 24, 358 .Rloop = 16, 359 .name = "64-bit SDR SGRAM (2:1)", 360}; 361 362static const struct aty128_meminfo ddr_sgram = { 363 .ML = 4, 364 .MB = 4, 365 .Trcd = 3, 366 .Trp = 3, 367 .Twr = 2, 368 .CL = 3, 369 .Tr2w = 1, 370 .LoopLatency = 16, 371 .DspOn = 31, 372 .Rloop = 16, 373 .name = "64-bit DDR SGRAM", 374}; 375 376static const struct fb_fix_screeninfo aty128fb_fix = { 377 .id = "ATY Rage128", 378 .type = FB_TYPE_PACKED_PIXELS, 379 .visual = FB_VISUAL_PSEUDOCOLOR, 380 .xpanstep = 8, 381 .ypanstep = 1, 382 .mmio_len = 0x2000, 383 .accel = FB_ACCEL_ATI_RAGE128, 384}; 385 386static char *mode_option = NULL; 387 388#ifdef CONFIG_PPC_PMAC 389static int default_vmode = VMODE_1024_768_60; 390static int default_cmode = CMODE_8; 391#endif 392 393static int default_crt_on = 0; 394static int default_lcd_on = 1; 395static bool mtrr = true; 396 397#ifdef CONFIG_FB_ATY128_BACKLIGHT 398static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 399#endif 400 401/* PLL constants */ 402struct aty128_constants { 403 u32 ref_clk; 404 u32 ppll_min; 405 u32 ppll_max; 406 u32 ref_divider; 407 u32 xclk; 408 u32 fifo_width; 409 u32 fifo_depth; 410}; 411 412struct aty128_crtc { 413 u32 gen_cntl; 414 u32 h_total, h_sync_strt_wid; 415 u32 v_total, v_sync_strt_wid; 416 u32 pitch; 417 u32 offset, offset_cntl; 418 u32 xoffset, yoffset; 419 u32 vxres, vyres; 420 u32 depth, bpp; 421}; 422 423struct aty128_pll { 424 u32 post_divider; 425 u32 feedback_divider; 426 u32 vclk; 427}; 428 429struct aty128_ddafifo { 430 u32 dda_config; 431 u32 dda_on_off; 432}; 433 434/* register values for a specific mode */ 435struct aty128fb_par { 436 struct aty128_crtc crtc; 437 struct aty128_pll pll; 438 struct aty128_ddafifo fifo_reg; 439 u32 accel_flags; 440 struct aty128_constants constants; /* PLL and others */ 441 void __iomem *regbase; /* remapped mmio */ 442 u32 vram_size; /* onboard video ram */ 443 int chip_gen; 444 const struct aty128_meminfo *mem; /* onboard mem info */ 445 int wc_cookie; 446 int blitter_may_be_busy; 447 int fifo_slots; /* free slots in FIFO (64 max) */ 448 449 int crt_on, lcd_on; 450 struct pci_dev *pdev; 451 struct fb_info *next; 452 int asleep; 453 int lock_blank; 454 455 u8 red[32]; /* see aty128fb_setcolreg */ 456 u8 green[64]; 457 u8 blue[32]; 458 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 459}; 460 461 462#define round_div(n, d) ((n+(d/2))/d) 463 464static int aty128fb_check_var(struct fb_var_screeninfo *var, 465 struct fb_info *info); 466static int aty128fb_set_par(struct fb_info *info); 467static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 468 u_int transp, struct fb_info *info); 469static int aty128fb_pan_display(struct fb_var_screeninfo *var, 470 struct fb_info *fb); 471static int aty128fb_blank(int blank, struct fb_info *fb); 472static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 473static int aty128fb_sync(struct fb_info *info); 474 475 /* 476 * Internal routines 477 */ 478 479static int aty128_encode_var(struct fb_var_screeninfo *var, 480 const struct aty128fb_par *par); 481static int aty128_decode_var(struct fb_var_screeninfo *var, 482 struct aty128fb_par *par); 483static void aty128_timings(struct aty128fb_par *par); 484static void aty128_init_engine(struct aty128fb_par *par); 485static void aty128_reset_engine(const struct aty128fb_par *par); 486static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 487static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 488static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 489static void wait_for_idle(struct aty128fb_par *par); 490static u32 depth_to_dst(u32 depth); 491 492#ifdef CONFIG_FB_ATY128_BACKLIGHT 493static void aty128_bl_set_power(struct fb_info *info, int power); 494#endif 495 496#define BIOS_IN8(v) (readb(bios + (v))) 497#define BIOS_IN16(v) (readb(bios + (v)) | \ 498 (readb(bios + (v) + 1) << 8)) 499#define BIOS_IN32(v) (readb(bios + (v)) | \ 500 (readb(bios + (v) + 1) << 8) | \ 501 (readb(bios + (v) + 2) << 16) | \ 502 (readb(bios + (v) + 3) << 24)) 503 504 505static const struct fb_ops aty128fb_ops = { 506 .owner = THIS_MODULE, 507 .fb_check_var = aty128fb_check_var, 508 .fb_set_par = aty128fb_set_par, 509 .fb_setcolreg = aty128fb_setcolreg, 510 .fb_pan_display = aty128fb_pan_display, 511 .fb_blank = aty128fb_blank, 512 .fb_ioctl = aty128fb_ioctl, 513 .fb_sync = aty128fb_sync, 514 .fb_fillrect = cfb_fillrect, 515 .fb_copyarea = cfb_copyarea, 516 .fb_imageblit = cfb_imageblit, 517}; 518 519 /* 520 * Functions to read from/write to the mmio registers 521 * - endian conversions may possibly be avoided by 522 * using the other register aperture. TODO. 523 */ 524static inline u32 _aty_ld_le32(volatile unsigned int regindex, 525 const struct aty128fb_par *par) 526{ 527 return readl (par->regbase + regindex); 528} 529 530static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 531 const struct aty128fb_par *par) 532{ 533 writel (val, par->regbase + regindex); 534} 535 536static inline u8 _aty_ld_8(unsigned int regindex, 537 const struct aty128fb_par *par) 538{ 539 return readb (par->regbase + regindex); 540} 541 542static inline void _aty_st_8(unsigned int regindex, u8 val, 543 const struct aty128fb_par *par) 544{ 545 writeb (val, par->regbase + regindex); 546} 547 548#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 549#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 550#define aty_ld_8(regindex) _aty_ld_8(regindex, par) 551#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 552 553 /* 554 * Functions to read from/write to the pll registers 555 */ 556 557#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 558#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 559 560 561static u32 _aty_ld_pll(unsigned int pll_index, 562 const struct aty128fb_par *par) 563{ 564 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 565 return aty_ld_le32(CLOCK_CNTL_DATA); 566} 567 568 569static void _aty_st_pll(unsigned int pll_index, u32 val, 570 const struct aty128fb_par *par) 571{ 572 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 573 aty_st_le32(CLOCK_CNTL_DATA, val); 574} 575 576 577/* return true when the PLL has completed an atomic update */ 578static int aty_pll_readupdate(const struct aty128fb_par *par) 579{ 580 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 581} 582 583 584static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 585{ 586 unsigned long timeout = jiffies + HZ/100; // should be more than enough 587 int reset = 1; 588 589 while (time_before(jiffies, timeout)) 590 if (aty_pll_readupdate(par)) { 591 reset = 0; 592 break; 593 } 594 595 if (reset) /* reset engine?? */ 596 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 597} 598 599 600/* tell PLL to update */ 601static void aty_pll_writeupdate(const struct aty128fb_par *par) 602{ 603 aty_pll_wait_readupdate(par); 604 605 aty_st_pll(PPLL_REF_DIV, 606 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 607} 608 609 610/* write to the scratch register to test r/w functionality */ 611static int register_test(const struct aty128fb_par *par) 612{ 613 u32 val; 614 int flag = 0; 615 616 val = aty_ld_le32(BIOS_0_SCRATCH); 617 618 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 619 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 620 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 621 622 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 623 flag = 1; 624 } 625 626 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 627 return flag; 628} 629 630 631/* 632 * Accelerator engine functions 633 */ 634static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 635{ 636 int i; 637 638 for (;;) { 639 for (i = 0; i < 2000000; i++) { 640 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 641 if (par->fifo_slots >= entries) 642 return; 643 } 644 aty128_reset_engine(par); 645 } 646} 647 648 649static void wait_for_idle(struct aty128fb_par *par) 650{ 651 int i; 652 653 do_wait_for_fifo(64, par); 654 655 for (;;) { 656 for (i = 0; i < 2000000; i++) { 657 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 658 aty128_flush_pixel_cache(par); 659 par->blitter_may_be_busy = 0; 660 return; 661 } 662 } 663 aty128_reset_engine(par); 664 } 665} 666 667 668static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 669{ 670 if (par->fifo_slots < entries) 671 do_wait_for_fifo(64, par); 672 par->fifo_slots -= entries; 673} 674 675 676static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 677{ 678 int i; 679 u32 tmp; 680 681 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 682 tmp &= ~(0x00ff); 683 tmp |= 0x00ff; 684 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 685 686 for (i = 0; i < 2000000; i++) 687 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 688 break; 689} 690 691 692static void aty128_reset_engine(const struct aty128fb_par *par) 693{ 694 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 695 696 aty128_flush_pixel_cache(par); 697 698 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 699 mclk_cntl = aty_ld_pll(MCLK_CNTL); 700 701 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 702 703 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 704 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 705 aty_ld_le32(GEN_RESET_CNTL); 706 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 707 aty_ld_le32(GEN_RESET_CNTL); 708 709 aty_st_pll(MCLK_CNTL, mclk_cntl); 710 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 711 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 712 713 /* use old pio mode */ 714 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 715 716 DBG("engine reset"); 717} 718 719 720static void aty128_init_engine(struct aty128fb_par *par) 721{ 722 u32 pitch_value; 723 724 wait_for_idle(par); 725 726 /* 3D scaler not spoken here */ 727 wait_for_fifo(1, par); 728 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 729 730 aty128_reset_engine(par); 731 732 pitch_value = par->crtc.pitch; 733 if (par->crtc.bpp == 24) { 734 pitch_value = pitch_value * 3; 735 } 736 737 wait_for_fifo(4, par); 738 /* setup engine offset registers */ 739 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 740 741 /* setup engine pitch registers */ 742 aty_st_le32(DEFAULT_PITCH, pitch_value); 743 744 /* set the default scissor register to max dimensions */ 745 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 746 747 /* set the drawing controls registers */ 748 aty_st_le32(DP_GUI_MASTER_CNTL, 749 GMC_SRC_PITCH_OFFSET_DEFAULT | 750 GMC_DST_PITCH_OFFSET_DEFAULT | 751 GMC_SRC_CLIP_DEFAULT | 752 GMC_DST_CLIP_DEFAULT | 753 GMC_BRUSH_SOLIDCOLOR | 754 (depth_to_dst(par->crtc.depth) << 8) | 755 GMC_SRC_DSTCOLOR | 756 GMC_BYTE_ORDER_MSB_TO_LSB | 757 GMC_DP_CONVERSION_TEMP_6500 | 758 ROP3_PATCOPY | 759 GMC_DP_SRC_RECT | 760 GMC_3D_FCN_EN_CLR | 761 GMC_DST_CLR_CMP_FCN_CLEAR | 762 GMC_AUX_CLIP_CLEAR | 763 GMC_WRITE_MASK_SET); 764 765 wait_for_fifo(8, par); 766 /* clear the line drawing registers */ 767 aty_st_le32(DST_BRES_ERR, 0); 768 aty_st_le32(DST_BRES_INC, 0); 769 aty_st_le32(DST_BRES_DEC, 0); 770 771 /* set brush color registers */ 772 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 773 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 774 775 /* set source color registers */ 776 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 777 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 778 779 /* default write mask */ 780 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 781 782 /* Wait for all the writes to be completed before returning */ 783 wait_for_idle(par); 784} 785 786 787/* convert depth values to their register representation */ 788static u32 depth_to_dst(u32 depth) 789{ 790 if (depth <= 8) 791 return DST_8BPP; 792 else if (depth <= 15) 793 return DST_15BPP; 794 else if (depth == 16) 795 return DST_16BPP; 796 else if (depth <= 24) 797 return DST_24BPP; 798 else if (depth <= 32) 799 return DST_32BPP; 800 801 return -EINVAL; 802} 803 804/* 805 * PLL informations retreival 806 */ 807 808 809#ifndef __sparc__ 810static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, 811 struct pci_dev *dev) 812{ 813 u16 dptr; 814 u8 rom_type; 815 void __iomem *bios; 816 size_t rom_size; 817 818 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 819 unsigned int temp; 820 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 821 temp &= 0x00ffffffu; 822 temp |= 0x04 << 24; 823 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 824 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 825 826 bios = pci_map_rom(dev, &rom_size); 827 828 if (!bios) { 829 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 830 return NULL; 831 } 832 833 /* Very simple test to make sure it appeared */ 834 if (BIOS_IN16(0) != 0xaa55) { 835 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 836 " be 0xaa55\n", BIOS_IN16(0)); 837 goto failed; 838 } 839 840 /* Look for the PCI data to check the ROM type */ 841 dptr = BIOS_IN16(0x18); 842 843 /* Check the PCI data signature. If it's wrong, we still assume a normal 844 * x86 ROM for now, until I've verified this works everywhere. 845 * The goal here is more to phase out Open Firmware images. 846 * 847 * Currently, we only look at the first PCI data, we could iteratre and 848 * deal with them all, and we should use fb_bios_start relative to start 849 * of image and not relative start of ROM, but so far, I never found a 850 * dual-image ATI card. 851 * 852 * typedef struct { 853 * u32 signature; + 0x00 854 * u16 vendor; + 0x04 855 * u16 device; + 0x06 856 * u16 reserved_1; + 0x08 857 * u16 dlen; + 0x0a 858 * u8 drevision; + 0x0c 859 * u8 class_hi; + 0x0d 860 * u16 class_lo; + 0x0e 861 * u16 ilen; + 0x10 862 * u16 irevision; + 0x12 863 * u8 type; + 0x14 864 * u8 indicator; + 0x15 865 * u16 reserved_2; + 0x16 866 * } pci_data_t; 867 */ 868 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 869 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 870 BIOS_IN32(dptr)); 871 goto anyway; 872 } 873 rom_type = BIOS_IN8(dptr + 0x14); 874 switch(rom_type) { 875 case 0: 876 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 877 break; 878 case 1: 879 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 880 goto failed; 881 case 2: 882 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 883 goto failed; 884 default: 885 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", 886 rom_type); 887 goto failed; 888 } 889 anyway: 890 return bios; 891 892 failed: 893 pci_unmap_rom(dev, bios); 894 return NULL; 895} 896 897static void aty128_get_pllinfo(struct aty128fb_par *par, 898 unsigned char __iomem *bios) 899{ 900 unsigned int bios_hdr; 901 unsigned int bios_pll; 902 903 bios_hdr = BIOS_IN16(0x48); 904 bios_pll = BIOS_IN16(bios_hdr + 0x30); 905 906 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 907 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 908 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 909 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 910 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 911 912 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 913 par->constants.ppll_max, par->constants.ppll_min, 914 par->constants.xclk, par->constants.ref_divider, 915 par->constants.ref_clk); 916 917} 918 919#ifdef CONFIG_X86 920static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) 921{ 922 /* I simplified this code as we used to miss the signatures in 923 * a lot of case. It's now closer to XFree, we just don't check 924 * for signatures at all... Something better will have to be done 925 * if we end up having conflicts 926 */ 927 u32 segstart; 928 unsigned char __iomem *rom_base = NULL; 929 930 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 931 rom_base = ioremap(segstart, 0x10000); 932 if (rom_base == NULL) 933 return NULL; 934 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 935 break; 936 iounmap(rom_base); 937 rom_base = NULL; 938 } 939 return rom_base; 940} 941#endif 942#endif /* ndef(__sparc__) */ 943 944/* fill in known card constants if pll_block is not available */ 945static void aty128_timings(struct aty128fb_par *par) 946{ 947#ifdef CONFIG_PPC 948 /* instead of a table lookup, assume OF has properly 949 * setup the PLL registers and use their values 950 * to set the XCLK values and reference divider values */ 951 952 u32 x_mpll_ref_fb_div; 953 u32 xclk_cntl; 954 u32 Nx, M; 955 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 956#endif 957 958 if (!par->constants.ref_clk) 959 par->constants.ref_clk = 2950; 960 961#ifdef CONFIG_PPC 962 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 963 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 964 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 965 M = x_mpll_ref_fb_div & 0x0000ff; 966 967 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 968 (M * PostDivSet[xclk_cntl])); 969 970 par->constants.ref_divider = 971 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 972#endif 973 974 if (!par->constants.ref_divider) { 975 par->constants.ref_divider = 0x3b; 976 977 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 978 aty_pll_writeupdate(par); 979 } 980 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 981 aty_pll_writeupdate(par); 982 983 /* from documentation */ 984 if (!par->constants.ppll_min) 985 par->constants.ppll_min = 12500; 986 if (!par->constants.ppll_max) 987 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 988 if (!par->constants.xclk) 989 par->constants.xclk = 0x1d4d; /* same as mclk */ 990 991 par->constants.fifo_width = 128; 992 par->constants.fifo_depth = 32; 993 994 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 995 case 0: 996 par->mem = &sdr_128; 997 break; 998 case 1: 999 par->mem = &sdr_sgram; 1000 break; 1001 case 2: 1002 par->mem = &ddr_sgram; 1003 break; 1004 default: 1005 par->mem = &sdr_sgram; 1006 } 1007} 1008 1009 1010 1011/* 1012 * CRTC programming 1013 */ 1014 1015/* Program the CRTC registers */ 1016static void aty128_set_crtc(const struct aty128_crtc *crtc, 1017 const struct aty128fb_par *par) 1018{ 1019 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 1020 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 1021 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1022 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 1023 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1024 aty_st_le32(CRTC_PITCH, crtc->pitch); 1025 aty_st_le32(CRTC_OFFSET, crtc->offset); 1026 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 1027 /* Disable ATOMIC updating. Is this the right place? */ 1028 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 1029} 1030 1031 1032static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 1033 struct aty128_crtc *crtc, 1034 const struct aty128fb_par *par) 1035{ 1036 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1037 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1038 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1039 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1040 u32 depth, bytpp; 1041 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1042 1043 /* input */ 1044 xres = var->xres; 1045 yres = var->yres; 1046 vxres = var->xres_virtual; 1047 vyres = var->yres_virtual; 1048 xoffset = var->xoffset; 1049 yoffset = var->yoffset; 1050 bpp = var->bits_per_pixel; 1051 left = var->left_margin; 1052 right = var->right_margin; 1053 upper = var->upper_margin; 1054 lower = var->lower_margin; 1055 hslen = var->hsync_len; 1056 vslen = var->vsync_len; 1057 sync = var->sync; 1058 vmode = var->vmode; 1059 1060 if (bpp != 16) 1061 depth = bpp; 1062 else 1063 depth = (var->green.length == 6) ? 16 : 15; 1064 1065 /* check for mode eligibility 1066 * accept only non interlaced modes */ 1067 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1068 return -EINVAL; 1069 1070 /* convert (and round up) and validate */ 1071 xres = (xres + 7) & ~7; 1072 xoffset = (xoffset + 7) & ~7; 1073 1074 if (vxres < xres + xoffset) 1075 vxres = xres + xoffset; 1076 1077 if (vyres < yres + yoffset) 1078 vyres = yres + yoffset; 1079 1080 /* convert depth into ATI register depth */ 1081 dst = depth_to_dst(depth); 1082 1083 if (dst == -EINVAL) { 1084 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1085 return -EINVAL; 1086 } 1087 1088 /* convert register depth to bytes per pixel */ 1089 bytpp = mode_bytpp[dst]; 1090 1091 /* make sure there is enough video ram for the mode */ 1092 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1093 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1094 return -EINVAL; 1095 } 1096 1097 h_disp = (xres >> 3) - 1; 1098 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1099 1100 v_disp = yres - 1; 1101 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1102 1103 /* check to make sure h_total and v_total are in range */ 1104 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1105 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1106 return -EINVAL; 1107 } 1108 1109 h_sync_wid = (hslen + 7) >> 3; 1110 if (h_sync_wid == 0) 1111 h_sync_wid = 1; 1112 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1113 h_sync_wid = 0x3f; 1114 1115 h_sync_strt = (h_disp << 3) + right; 1116 1117 v_sync_wid = vslen; 1118 if (v_sync_wid == 0) 1119 v_sync_wid = 1; 1120 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1121 v_sync_wid = 0x1f; 1122 1123 v_sync_strt = v_disp + lower; 1124 1125 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1126 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1127 1128 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1129 1130 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1131 1132 crtc->h_total = h_total | (h_disp << 16); 1133 crtc->v_total = v_total | (v_disp << 16); 1134 1135 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1136 (h_sync_pol << 23); 1137 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1138 (v_sync_pol << 23); 1139 1140 crtc->pitch = vxres >> 3; 1141 1142 crtc->offset = 0; 1143 1144 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1145 crtc->offset_cntl = 0x00010000; 1146 else 1147 crtc->offset_cntl = 0; 1148 1149 crtc->vxres = vxres; 1150 crtc->vyres = vyres; 1151 crtc->xoffset = xoffset; 1152 crtc->yoffset = yoffset; 1153 crtc->depth = depth; 1154 crtc->bpp = bpp; 1155 1156 return 0; 1157} 1158 1159 1160static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1161{ 1162 1163 /* fill in pixel info */ 1164 var->red.msb_right = 0; 1165 var->green.msb_right = 0; 1166 var->blue.offset = 0; 1167 var->blue.msb_right = 0; 1168 var->transp.offset = 0; 1169 var->transp.length = 0; 1170 var->transp.msb_right = 0; 1171 switch (pix_width) { 1172 case CRTC_PIX_WIDTH_8BPP: 1173 var->bits_per_pixel = 8; 1174 var->red.offset = 0; 1175 var->red.length = 8; 1176 var->green.offset = 0; 1177 var->green.length = 8; 1178 var->blue.length = 8; 1179 break; 1180 case CRTC_PIX_WIDTH_15BPP: 1181 var->bits_per_pixel = 16; 1182 var->red.offset = 10; 1183 var->red.length = 5; 1184 var->green.offset = 5; 1185 var->green.length = 5; 1186 var->blue.length = 5; 1187 break; 1188 case CRTC_PIX_WIDTH_16BPP: 1189 var->bits_per_pixel = 16; 1190 var->red.offset = 11; 1191 var->red.length = 5; 1192 var->green.offset = 5; 1193 var->green.length = 6; 1194 var->blue.length = 5; 1195 break; 1196 case CRTC_PIX_WIDTH_24BPP: 1197 var->bits_per_pixel = 24; 1198 var->red.offset = 16; 1199 var->red.length = 8; 1200 var->green.offset = 8; 1201 var->green.length = 8; 1202 var->blue.length = 8; 1203 break; 1204 case CRTC_PIX_WIDTH_32BPP: 1205 var->bits_per_pixel = 32; 1206 var->red.offset = 16; 1207 var->red.length = 8; 1208 var->green.offset = 8; 1209 var->green.length = 8; 1210 var->blue.length = 8; 1211 var->transp.offset = 24; 1212 var->transp.length = 8; 1213 break; 1214 default: 1215 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1216 return -EINVAL; 1217 } 1218 1219 return 0; 1220} 1221 1222 1223static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1224 struct fb_var_screeninfo *var) 1225{ 1226 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1227 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1228 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1229 u32 pix_width; 1230 1231 /* fun with masking */ 1232 h_total = crtc->h_total & 0x1ff; 1233 h_disp = (crtc->h_total >> 16) & 0xff; 1234 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1235 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1236 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1237 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1238 v_total = crtc->v_total & 0x7ff; 1239 v_disp = (crtc->v_total >> 16) & 0x7ff; 1240 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1241 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1242 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1243 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1244 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1245 1246 /* do conversions */ 1247 xres = (h_disp + 1) << 3; 1248 yres = v_disp + 1; 1249 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1250 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1251 hslen = h_sync_wid << 3; 1252 upper = v_total - v_sync_strt - v_sync_wid; 1253 lower = v_sync_strt - v_disp; 1254 vslen = v_sync_wid; 1255 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1256 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1257 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1258 1259 aty128_pix_width_to_var(pix_width, var); 1260 1261 var->xres = xres; 1262 var->yres = yres; 1263 var->xres_virtual = crtc->vxres; 1264 var->yres_virtual = crtc->vyres; 1265 var->xoffset = crtc->xoffset; 1266 var->yoffset = crtc->yoffset; 1267 var->left_margin = left; 1268 var->right_margin = right; 1269 var->upper_margin = upper; 1270 var->lower_margin = lower; 1271 var->hsync_len = hslen; 1272 var->vsync_len = vslen; 1273 var->sync = sync; 1274 var->vmode = FB_VMODE_NONINTERLACED; 1275 1276 return 0; 1277} 1278 1279static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1280{ 1281 if (on) { 1282 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | 1283 CRT_CRTC_ON); 1284 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | 1285 DAC_PALETTE2_SNOOP_EN)); 1286 } else 1287 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & 1288 ~CRT_CRTC_ON); 1289} 1290 1291static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1292{ 1293 u32 reg; 1294#ifdef CONFIG_FB_ATY128_BACKLIGHT 1295 struct fb_info *info = pci_get_drvdata(par->pdev); 1296#endif 1297 1298 if (on) { 1299 reg = aty_ld_le32(LVDS_GEN_CNTL); 1300 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1301 reg &= ~LVDS_DISPLAY_DIS; 1302 aty_st_le32(LVDS_GEN_CNTL, reg); 1303#ifdef CONFIG_FB_ATY128_BACKLIGHT 1304 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1305#endif 1306 } else { 1307#ifdef CONFIG_FB_ATY128_BACKLIGHT 1308 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1309#endif 1310 reg = aty_ld_le32(LVDS_GEN_CNTL); 1311 reg |= LVDS_DISPLAY_DIS; 1312 aty_st_le32(LVDS_GEN_CNTL, reg); 1313 mdelay(100); 1314 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1315 aty_st_le32(LVDS_GEN_CNTL, reg); 1316 } 1317} 1318 1319static void aty128_set_pll(struct aty128_pll *pll, 1320 const struct aty128fb_par *par) 1321{ 1322 u32 div3; 1323 1324 unsigned char post_conv[] = /* register values for post dividers */ 1325 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1326 1327 /* select PPLL_DIV_3 */ 1328 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1329 1330 /* reset PLL */ 1331 aty_st_pll(PPLL_CNTL, 1332 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1333 1334 /* write the reference divider */ 1335 aty_pll_wait_readupdate(par); 1336 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1337 aty_pll_writeupdate(par); 1338 1339 div3 = aty_ld_pll(PPLL_DIV_3); 1340 div3 &= ~PPLL_FB3_DIV_MASK; 1341 div3 |= pll->feedback_divider; 1342 div3 &= ~PPLL_POST3_DIV_MASK; 1343 div3 |= post_conv[pll->post_divider] << 16; 1344 1345 /* write feedback and post dividers */ 1346 aty_pll_wait_readupdate(par); 1347 aty_st_pll(PPLL_DIV_3, div3); 1348 aty_pll_writeupdate(par); 1349 1350 aty_pll_wait_readupdate(par); 1351 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1352 aty_pll_writeupdate(par); 1353 1354 /* clear the reset, just in case */ 1355 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1356} 1357 1358 1359static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1360 const struct aty128fb_par *par) 1361{ 1362 const struct aty128_constants c = par->constants; 1363 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1364 u32 output_freq; 1365 u32 vclk; /* in .01 MHz */ 1366 int i = 0; 1367 u32 n, d; 1368 1369 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1370 1371 /* adjust pixel clock if necessary */ 1372 if (vclk > c.ppll_max) 1373 vclk = c.ppll_max; 1374 if (vclk * 12 < c.ppll_min) 1375 vclk = c.ppll_min/12; 1376 1377 /* now, find an acceptable divider */ 1378 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { 1379 output_freq = post_dividers[i] * vclk; 1380 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1381 pll->post_divider = post_dividers[i]; 1382 break; 1383 } 1384 } 1385 1386 if (i == ARRAY_SIZE(post_dividers)) 1387 return -EINVAL; 1388 1389 /* calculate feedback divider */ 1390 n = c.ref_divider * output_freq; 1391 d = c.ref_clk; 1392 1393 pll->feedback_divider = round_div(n, d); 1394 pll->vclk = vclk; 1395 1396 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1397 "vclk_per: %d\n", pll->post_divider, 1398 pll->feedback_divider, vclk, output_freq, 1399 c.ref_divider, period_in_ps); 1400 1401 return 0; 1402} 1403 1404 1405static int aty128_pll_to_var(const struct aty128_pll *pll, 1406 struct fb_var_screeninfo *var) 1407{ 1408 var->pixclock = 100000000 / pll->vclk; 1409 1410 return 0; 1411} 1412 1413 1414static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1415 const struct aty128fb_par *par) 1416{ 1417 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1418 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1419} 1420 1421 1422static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1423 const struct aty128_pll *pll, 1424 u32 depth, 1425 const struct aty128fb_par *par) 1426{ 1427 const struct aty128_meminfo *m = par->mem; 1428 u32 xclk = par->constants.xclk; 1429 u32 fifo_width = par->constants.fifo_width; 1430 u32 fifo_depth = par->constants.fifo_depth; 1431 s32 x, b, p, ron, roff; 1432 u32 n, d, bpp; 1433 1434 /* round up to multiple of 8 */ 1435 bpp = (depth+7) & ~7; 1436 1437 n = xclk * fifo_width; 1438 d = pll->vclk * bpp; 1439 x = round_div(n, d); 1440 1441 ron = 4 * m->MB + 1442 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1443 2 * m->Trp + 1444 m->Twr + 1445 m->CL + 1446 m->Tr2w + 1447 x; 1448 1449 DBG("x %x\n", x); 1450 1451 b = 0; 1452 while (x) { 1453 x >>= 1; 1454 b++; 1455 } 1456 p = b + 1; 1457 1458 ron <<= (11 - p); 1459 1460 n <<= (11 - p); 1461 x = round_div(n, d); 1462 roff = x * (fifo_depth - 4); 1463 1464 if ((ron + m->Rloop) >= roff) { 1465 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1466 return -EINVAL; 1467 } 1468 1469 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1470 p, m->Rloop, x, ron, roff); 1471 1472 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1473 dsp->dda_on_off = ron << 16 | roff; 1474 1475 return 0; 1476} 1477 1478 1479/* 1480 * This actually sets the video mode. 1481 */ 1482static int aty128fb_set_par(struct fb_info *info) 1483{ 1484 struct aty128fb_par *par = info->par; 1485 u32 config; 1486 int err; 1487 1488 if ((err = aty128_decode_var(&info->var, par)) != 0) 1489 return err; 1490 1491 if (par->blitter_may_be_busy) 1492 wait_for_idle(par); 1493 1494 /* clear all registers that may interfere with mode setting */ 1495 aty_st_le32(OVR_CLR, 0); 1496 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1497 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1498 aty_st_le32(OV0_SCALE_CNTL, 0); 1499 aty_st_le32(MPP_TB_CONFIG, 0); 1500 aty_st_le32(MPP_GP_CONFIG, 0); 1501 aty_st_le32(SUBPIC_CNTL, 0); 1502 aty_st_le32(VIPH_CONTROL, 0); 1503 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1504 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1505 aty_st_le32(CAP0_TRIG_CNTL, 0); 1506 aty_st_le32(CAP1_TRIG_CNTL, 0); 1507 1508 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1509 1510 aty128_set_crtc(&par->crtc, par); 1511 aty128_set_pll(&par->pll, par); 1512 aty128_set_fifo(&par->fifo_reg, par); 1513 1514 config = aty_ld_le32(CNFG_CNTL) & ~3; 1515 1516#if defined(__BIG_ENDIAN) 1517 if (par->crtc.bpp == 32) 1518 config |= 2; /* make aperture do 32 bit swapping */ 1519 else if (par->crtc.bpp == 16) 1520 config |= 1; /* make aperture do 16 bit swapping */ 1521#endif 1522 1523 aty_st_le32(CNFG_CNTL, config); 1524 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1525 1526 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1527 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1528 : FB_VISUAL_DIRECTCOLOR; 1529 1530 if (par->chip_gen == rage_M3) { 1531 aty128_set_crt_enable(par, par->crt_on); 1532 aty128_set_lcd_enable(par, par->lcd_on); 1533 } 1534 if (par->accel_flags & FB_ACCELF_TEXT) 1535 aty128_init_engine(par); 1536 1537#ifdef CONFIG_BOOTX_TEXT 1538 btext_update_display(info->fix.smem_start, 1539 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1540 ((par->crtc.v_total>>16) & 0x7ff)+1, 1541 par->crtc.bpp, 1542 par->crtc.vxres*par->crtc.bpp/8); 1543#endif /* CONFIG_BOOTX_TEXT */ 1544 1545 return 0; 1546} 1547 1548/* 1549 * encode/decode the User Defined Part of the Display 1550 */ 1551 1552static int aty128_decode_var(struct fb_var_screeninfo *var, 1553 struct aty128fb_par *par) 1554{ 1555 int err; 1556 struct aty128_crtc crtc; 1557 struct aty128_pll pll; 1558 struct aty128_ddafifo fifo_reg; 1559 1560 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1561 return err; 1562 1563 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1564 return err; 1565 1566 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1567 return err; 1568 1569 par->crtc = crtc; 1570 par->pll = pll; 1571 par->fifo_reg = fifo_reg; 1572 par->accel_flags = var->accel_flags; 1573 1574 return 0; 1575} 1576 1577 1578static int aty128_encode_var(struct fb_var_screeninfo *var, 1579 const struct aty128fb_par *par) 1580{ 1581 int err; 1582 1583 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1584 return err; 1585 1586 if ((err = aty128_pll_to_var(&par->pll, var))) 1587 return err; 1588 1589 var->nonstd = 0; 1590 var->activate = 0; 1591 1592 var->height = -1; 1593 var->width = -1; 1594 var->accel_flags = par->accel_flags; 1595 1596 return 0; 1597} 1598 1599 1600static int aty128fb_check_var(struct fb_var_screeninfo *var, 1601 struct fb_info *info) 1602{ 1603 struct aty128fb_par par; 1604 int err; 1605 1606 par = *(struct aty128fb_par *)info->par; 1607 if ((err = aty128_decode_var(var, &par)) != 0) 1608 return err; 1609 aty128_encode_var(var, &par); 1610 return 0; 1611} 1612 1613 1614/* 1615 * Pan or Wrap the Display 1616 */ 1617static int aty128fb_pan_display(struct fb_var_screeninfo *var, 1618 struct fb_info *fb) 1619{ 1620 struct aty128fb_par *par = fb->par; 1621 u32 xoffset, yoffset; 1622 u32 offset; 1623 u32 xres, yres; 1624 1625 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1626 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1627 1628 xoffset = (var->xoffset +7) & ~7; 1629 yoffset = var->yoffset; 1630 1631 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1632 return -EINVAL; 1633 1634 par->crtc.xoffset = xoffset; 1635 par->crtc.yoffset = yoffset; 1636 1637 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) 1638 & ~7; 1639 1640 if (par->crtc.bpp == 24) 1641 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1642 1643 aty_st_le32(CRTC_OFFSET, offset); 1644 1645 return 0; 1646} 1647 1648 1649/* 1650 * Helper function to store a single palette register 1651 */ 1652static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1653 struct aty128fb_par *par) 1654{ 1655 if (par->chip_gen == rage_M3) { 1656 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & 1657 ~DAC_PALETTE_ACCESS_CNTL); 1658 } 1659 1660 aty_st_8(PALETTE_INDEX, regno); 1661 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1662} 1663 1664static int aty128fb_sync(struct fb_info *info) 1665{ 1666 struct aty128fb_par *par = info->par; 1667 1668 if (par->blitter_may_be_busy) 1669 wait_for_idle(par); 1670 return 0; 1671} 1672 1673#ifndef MODULE 1674static int aty128fb_setup(char *options) 1675{ 1676 char *this_opt; 1677 1678 if (!options || !*options) 1679 return 0; 1680 1681 while ((this_opt = strsep(&options, ",")) != NULL) { 1682 if (!strncmp(this_opt, "lcd:", 4)) { 1683 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1684 continue; 1685 } else if (!strncmp(this_opt, "crt:", 4)) { 1686 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1687 continue; 1688 } else if (!strncmp(this_opt, "backlight:", 10)) { 1689#ifdef CONFIG_FB_ATY128_BACKLIGHT 1690 backlight = simple_strtoul(this_opt+10, NULL, 0); 1691#endif 1692 continue; 1693 } 1694 if(!strncmp(this_opt, "nomtrr", 6)) { 1695 mtrr = false; 1696 continue; 1697 } 1698#ifdef CONFIG_PPC_PMAC 1699 /* vmode and cmode deprecated */ 1700 if (!strncmp(this_opt, "vmode:", 6)) { 1701 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1702 if (vmode > 0 && vmode <= VMODE_MAX) 1703 default_vmode = vmode; 1704 continue; 1705 } else if (!strncmp(this_opt, "cmode:", 6)) { 1706 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1707 switch (cmode) { 1708 case 0: 1709 case 8: 1710 default_cmode = CMODE_8; 1711 break; 1712 case 15: 1713 case 16: 1714 default_cmode = CMODE_16; 1715 break; 1716 case 24: 1717 case 32: 1718 default_cmode = CMODE_32; 1719 break; 1720 } 1721 continue; 1722 } 1723#endif /* CONFIG_PPC_PMAC */ 1724 mode_option = this_opt; 1725 } 1726 return 0; 1727} 1728#endif /* MODULE */ 1729 1730/* Backlight */ 1731#ifdef CONFIG_FB_ATY128_BACKLIGHT 1732#define MAX_LEVEL 0xFF 1733 1734static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1735 int level) 1736{ 1737 struct fb_info *info = pci_get_drvdata(par->pdev); 1738 int atylevel; 1739 1740 /* Get and convert the value */ 1741 /* No locking of bl_curve since we read a single value */ 1742 atylevel = MAX_LEVEL - 1743 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1744 1745 if (atylevel < 0) 1746 atylevel = 0; 1747 else if (atylevel > MAX_LEVEL) 1748 atylevel = MAX_LEVEL; 1749 1750 return atylevel; 1751} 1752 1753/* We turn off the LCD completely instead of just dimming the backlight. 1754 * This provides greater power saving and the display is useless without 1755 * backlight anyway 1756 */ 1757#define BACKLIGHT_LVDS_OFF 1758/* That one prevents proper CRT output with LCD off */ 1759#undef BACKLIGHT_DAC_OFF 1760 1761static int aty128_bl_update_status(struct backlight_device *bd) 1762{ 1763 struct aty128fb_par *par = bl_get_data(bd); 1764 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1765 int level; 1766 1767 if (bd->props.power != FB_BLANK_UNBLANK || 1768 bd->props.fb_blank != FB_BLANK_UNBLANK || 1769 !par->lcd_on) 1770 level = 0; 1771 else 1772 level = bd->props.brightness; 1773 1774 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1775 if (level > 0) { 1776 reg |= LVDS_DIGION; 1777 if (!(reg & LVDS_ON)) { 1778 reg &= ~LVDS_BLON; 1779 aty_st_le32(LVDS_GEN_CNTL, reg); 1780 aty_ld_le32(LVDS_GEN_CNTL); 1781 mdelay(10); 1782 reg |= LVDS_BLON; 1783 aty_st_le32(LVDS_GEN_CNTL, reg); 1784 } 1785 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1786 reg |= (aty128_bl_get_level_brightness(par, level) << 1787 LVDS_BL_MOD_LEVEL_SHIFT); 1788#ifdef BACKLIGHT_LVDS_OFF 1789 reg |= LVDS_ON | LVDS_EN; 1790 reg &= ~LVDS_DISPLAY_DIS; 1791#endif 1792 aty_st_le32(LVDS_GEN_CNTL, reg); 1793#ifdef BACKLIGHT_DAC_OFF 1794 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1795#endif 1796 } else { 1797 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1798 reg |= (aty128_bl_get_level_brightness(par, 0) << 1799 LVDS_BL_MOD_LEVEL_SHIFT); 1800#ifdef BACKLIGHT_LVDS_OFF 1801 reg |= LVDS_DISPLAY_DIS; 1802 aty_st_le32(LVDS_GEN_CNTL, reg); 1803 aty_ld_le32(LVDS_GEN_CNTL); 1804 udelay(10); 1805 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1806#endif 1807 aty_st_le32(LVDS_GEN_CNTL, reg); 1808#ifdef BACKLIGHT_DAC_OFF 1809 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1810#endif 1811 } 1812 1813 return 0; 1814} 1815 1816static const struct backlight_ops aty128_bl_data = { 1817 .update_status = aty128_bl_update_status, 1818}; 1819 1820static void aty128_bl_set_power(struct fb_info *info, int power) 1821{ 1822 if (info->bl_dev) { 1823 info->bl_dev->props.power = power; 1824 backlight_update_status(info->bl_dev); 1825 } 1826} 1827 1828static void aty128_bl_init(struct aty128fb_par *par) 1829{ 1830 struct backlight_properties props; 1831 struct fb_info *info = pci_get_drvdata(par->pdev); 1832 struct backlight_device *bd; 1833 char name[12]; 1834 1835 /* Could be extended to Rage128Pro LVDS output too */ 1836 if (par->chip_gen != rage_M3) 1837 return; 1838 1839#ifdef CONFIG_PMAC_BACKLIGHT 1840 if (!pmac_has_backlight_type("ati")) 1841 return; 1842#endif 1843 1844 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1845 1846 memset(&props, 0, sizeof(struct backlight_properties)); 1847 props.type = BACKLIGHT_RAW; 1848 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1849 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, 1850 &props); 1851 if (IS_ERR(bd)) { 1852 info->bl_dev = NULL; 1853 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1854 goto error; 1855 } 1856 1857 info->bl_dev = bd; 1858 fb_bl_default_curve(info, 0, 1859 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1860 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1861 1862 bd->props.brightness = bd->props.max_brightness; 1863 bd->props.power = FB_BLANK_UNBLANK; 1864 backlight_update_status(bd); 1865 1866 printk("aty128: Backlight initialized (%s)\n", name); 1867 1868 return; 1869 1870error: 1871 return; 1872} 1873 1874static void aty128_bl_exit(struct backlight_device *bd) 1875{ 1876 backlight_device_unregister(bd); 1877 printk("aty128: Backlight unloaded\n"); 1878} 1879#endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1880 1881/* 1882 * Initialisation 1883 */ 1884 1885#ifdef CONFIG_PPC_PMAC__disabled 1886static void aty128_early_resume(void *data) 1887{ 1888 struct aty128fb_par *par = data; 1889 1890 if (!console_trylock()) 1891 return; 1892 pci_restore_state(par->pdev); 1893 aty128_do_resume(par->pdev); 1894 console_unlock(); 1895} 1896#endif /* CONFIG_PPC_PMAC */ 1897 1898static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1899{ 1900 struct fb_info *info = pci_get_drvdata(pdev); 1901 struct aty128fb_par *par = info->par; 1902 struct fb_var_screeninfo var; 1903 char video_card[50]; 1904 u8 chip_rev; 1905 u32 dac; 1906 1907 /* Get the chip revision */ 1908 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; 1909 1910 strcpy(video_card, "Rage128 XX "); 1911 video_card[8] = ent->device >> 8; 1912 video_card[9] = ent->device & 0xFF; 1913 1914 /* range check to make sure */ 1915 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1916 strlcat(video_card, r128_family[ent->driver_data], 1917 sizeof(video_card)); 1918 1919 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1920 1921 if (par->vram_size % (1024 * 1024) == 0) 1922 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1923 else 1924 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1925 1926 par->chip_gen = ent->driver_data; 1927 1928 /* fill in info */ 1929 info->fbops = &aty128fb_ops; 1930 info->flags = FBINFO_FLAG_DEFAULT; 1931 1932 par->lcd_on = default_lcd_on; 1933 par->crt_on = default_crt_on; 1934 1935 var = default_var; 1936#ifdef CONFIG_PPC_PMAC 1937 if (machine_is(powermac)) { 1938 /* Indicate sleep capability */ 1939 if (par->chip_gen == rage_M3) { 1940 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1941#if 0 /* Disable the early video resume hack for now as it's causing problems, 1942 * among others we now rely on the PCI core restoring the config space 1943 * for us, which isn't the case with that hack, and that code path causes 1944 * various things to be called with interrupts off while they shouldn't. 1945 * I'm leaving the code in as it can be useful for debugging purposes 1946 */ 1947 pmac_set_early_video_resume(aty128_early_resume, par); 1948#endif 1949 } 1950 1951 /* Find default mode */ 1952 if (mode_option) { 1953 if (!mac_find_mode(&var, info, mode_option, 8)) 1954 var = default_var; 1955 } else { 1956 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1957 default_vmode = VMODE_1024_768_60; 1958 1959 /* iMacs need that resolution 1960 * PowerMac2,1 first r128 iMacs 1961 * PowerMac2,2 summer 2000 iMacs 1962 * PowerMac4,1 january 2001 iMacs "flower power" 1963 */ 1964 if (of_machine_is_compatible("PowerMac2,1") || 1965 of_machine_is_compatible("PowerMac2,2") || 1966 of_machine_is_compatible("PowerMac4,1")) 1967 default_vmode = VMODE_1024_768_75; 1968 1969 /* iBook SE */ 1970 if (of_machine_is_compatible("PowerBook2,2")) 1971 default_vmode = VMODE_800_600_60; 1972 1973 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1974 if (of_machine_is_compatible("PowerBook3,1") || 1975 of_machine_is_compatible("PowerBook4,1")) 1976 default_vmode = VMODE_1024_768_60; 1977 1978 /* PowerBook Titanium */ 1979 if (of_machine_is_compatible("PowerBook3,2")) 1980 default_vmode = VMODE_1152_768_60; 1981 1982 if (default_cmode > 16) 1983 default_cmode = CMODE_32; 1984 else if (default_cmode > 8) 1985 default_cmode = CMODE_16; 1986 else 1987 default_cmode = CMODE_8; 1988 1989 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1990 var = default_var; 1991 } 1992 } else 1993#endif /* CONFIG_PPC_PMAC */ 1994 { 1995 if (mode_option) 1996 if (fb_find_mode(&var, info, mode_option, NULL, 1997 0, &defaultmode, 8) == 0) 1998 var = default_var; 1999 } 2000 2001 var.accel_flags &= ~FB_ACCELF_TEXT; 2002// var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ 2003 2004 if (aty128fb_check_var(&var, info)) { 2005 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 2006 return 0; 2007 } 2008 2009 /* setup the DAC the way we like it */ 2010 dac = aty_ld_le32(DAC_CNTL); 2011 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 2012 dac |= DAC_MASK; 2013 if (par->chip_gen == rage_M3) 2014 dac |= DAC_PALETTE2_SNOOP_EN; 2015 aty_st_le32(DAC_CNTL, dac); 2016 2017 /* turn off bus mastering, just in case */ 2018 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 2019 2020 info->var = var; 2021 fb_alloc_cmap(&info->cmap, 256, 0); 2022 2023 var.activate = FB_ACTIVATE_NOW; 2024 2025 aty128_init_engine(par); 2026 2027 par->pdev = pdev; 2028 par->asleep = 0; 2029 par->lock_blank = 0; 2030 2031#ifdef CONFIG_FB_ATY128_BACKLIGHT 2032 if (backlight) 2033 aty128_bl_init(par); 2034#endif 2035 2036 if (register_framebuffer(info) < 0) 2037 return 0; 2038 2039 fb_info(info, "%s frame buffer device on %s\n", 2040 info->fix.id, video_card); 2041 2042 return 1; /* success! */ 2043} 2044 2045#ifdef CONFIG_PCI 2046/* register a card ++ajoshi */ 2047static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2048{ 2049 unsigned long fb_addr, reg_addr; 2050 struct aty128fb_par *par; 2051 struct fb_info *info; 2052 int err; 2053#ifndef __sparc__ 2054 void __iomem *bios = NULL; 2055#endif 2056 2057 /* Enable device in PCI config */ 2058 if ((err = pci_enable_device(pdev))) { 2059 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2060 err); 2061 return -ENODEV; 2062 } 2063 2064 fb_addr = pci_resource_start(pdev, 0); 2065 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2066 "aty128fb FB")) { 2067 printk(KERN_ERR "aty128fb: cannot reserve frame " 2068 "buffer memory\n"); 2069 return -ENODEV; 2070 } 2071 2072 reg_addr = pci_resource_start(pdev, 2); 2073 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2074 "aty128fb MMIO")) { 2075 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2076 goto err_free_fb; 2077 } 2078 2079 /* We have the resources. Now virtualize them */ 2080 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2081 if (!info) 2082 goto err_free_mmio; 2083 2084 par = info->par; 2085 2086 info->pseudo_palette = par->pseudo_palette; 2087 2088 /* Virtualize mmio region */ 2089 info->fix.mmio_start = reg_addr; 2090 par->regbase = pci_ioremap_bar(pdev, 2); 2091 if (!par->regbase) 2092 goto err_free_info; 2093 2094 /* Grab memory size from the card */ 2095 // How does this relate to the resource length from the PCI hardware? 2096 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; 2097 2098 /* Virtualize the framebuffer */ 2099 info->screen_base = ioremap_wc(fb_addr, par->vram_size); 2100 if (!info->screen_base) 2101 goto err_unmap_out; 2102 2103 /* Set up info->fix */ 2104 info->fix = aty128fb_fix; 2105 info->fix.smem_start = fb_addr; 2106 info->fix.smem_len = par->vram_size; 2107 info->fix.mmio_start = reg_addr; 2108 2109 /* If we can't test scratch registers, something is seriously wrong */ 2110 if (!register_test(par)) { 2111 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2112 goto err_out; 2113 } 2114 2115#ifndef __sparc__ 2116 bios = aty128_map_ROM(par, pdev); 2117#ifdef CONFIG_X86 2118 if (bios == NULL) 2119 bios = aty128_find_mem_vbios(par); 2120#endif 2121 if (bios == NULL) 2122 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2123 else { 2124 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2125 aty128_get_pllinfo(par, bios); 2126 pci_unmap_rom(pdev, bios); 2127 } 2128#endif /* __sparc__ */ 2129 2130 aty128_timings(par); 2131 pci_set_drvdata(pdev, info); 2132 2133 if (!aty128_init(pdev, ent)) 2134 goto err_out; 2135 2136 if (mtrr) 2137 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 2138 par->vram_size); 2139 return 0; 2140 2141err_out: 2142 iounmap(info->screen_base); 2143err_unmap_out: 2144 iounmap(par->regbase); 2145err_free_info: 2146 framebuffer_release(info); 2147err_free_mmio: 2148 release_mem_region(pci_resource_start(pdev, 2), 2149 pci_resource_len(pdev, 2)); 2150err_free_fb: 2151 release_mem_region(pci_resource_start(pdev, 0), 2152 pci_resource_len(pdev, 0)); 2153 return -ENODEV; 2154} 2155 2156static void aty128_remove(struct pci_dev *pdev) 2157{ 2158 struct fb_info *info = pci_get_drvdata(pdev); 2159 struct aty128fb_par *par; 2160 2161 if (!info) 2162 return; 2163 2164 par = info->par; 2165 2166 unregister_framebuffer(info); 2167 2168#ifdef CONFIG_FB_ATY128_BACKLIGHT 2169 aty128_bl_exit(info->bl_dev); 2170#endif 2171 2172 arch_phys_wc_del(par->wc_cookie); 2173 iounmap(par->regbase); 2174 iounmap(info->screen_base); 2175 2176 release_mem_region(pci_resource_start(pdev, 0), 2177 pci_resource_len(pdev, 0)); 2178 release_mem_region(pci_resource_start(pdev, 2), 2179 pci_resource_len(pdev, 2)); 2180 framebuffer_release(info); 2181} 2182#endif /* CONFIG_PCI */ 2183 2184 2185 2186 /* 2187 * Blank the display. 2188 */ 2189static int aty128fb_blank(int blank, struct fb_info *fb) 2190{ 2191 struct aty128fb_par *par = fb->par; 2192 u8 state; 2193 2194 if (par->lock_blank || par->asleep) 2195 return 0; 2196 2197 switch (blank) { 2198 case FB_BLANK_NORMAL: 2199 state = 4; 2200 break; 2201 case FB_BLANK_VSYNC_SUSPEND: 2202 state = 6; 2203 break; 2204 case FB_BLANK_HSYNC_SUSPEND: 2205 state = 5; 2206 break; 2207 case FB_BLANK_POWERDOWN: 2208 state = 7; 2209 break; 2210 case FB_BLANK_UNBLANK: 2211 default: 2212 state = 0; 2213 break; 2214 } 2215 aty_st_8(CRTC_EXT_CNTL+1, state); 2216 2217 if (par->chip_gen == rage_M3) { 2218 aty128_set_crt_enable(par, par->crt_on && !blank); 2219 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2220 } 2221 2222 return 0; 2223} 2224 2225/* 2226 * Set a single color register. The values supplied are already 2227 * rounded down to the hardware's capabilities (according to the 2228 * entries in the var structure). Return != 0 for invalid regno. 2229 */ 2230static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2231 u_int transp, struct fb_info *info) 2232{ 2233 struct aty128fb_par *par = info->par; 2234 2235 if (regno > 255 2236 || (par->crtc.depth == 16 && regno > 63) 2237 || (par->crtc.depth == 15 && regno > 31)) 2238 return 1; 2239 2240 red >>= 8; 2241 green >>= 8; 2242 blue >>= 8; 2243 2244 if (regno < 16) { 2245 int i; 2246 u32 *pal = info->pseudo_palette; 2247 2248 switch (par->crtc.depth) { 2249 case 15: 2250 pal[regno] = (regno << 10) | (regno << 5) | regno; 2251 break; 2252 case 16: 2253 pal[regno] = (regno << 11) | (regno << 6) | regno; 2254 break; 2255 case 24: 2256 pal[regno] = (regno << 16) | (regno << 8) | regno; 2257 break; 2258 case 32: 2259 i = (regno << 8) | regno; 2260 pal[regno] = (i << 16) | i; 2261 break; 2262 } 2263 } 2264 2265 if (par->crtc.depth == 16 && regno > 0) { 2266 /* 2267 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2268 * have 32 slots for R and B values but 64 slots for G values. 2269 * Thus the R and B values go in one slot but the G value 2270 * goes in a different slot, and we have to avoid disturbing 2271 * the other fields in the slots we touch. 2272 */ 2273 par->green[regno] = green; 2274 if (regno < 32) { 2275 par->red[regno] = red; 2276 par->blue[regno] = blue; 2277 aty128_st_pal(regno * 8, red, par->green[regno*2], 2278 blue, par); 2279 } 2280 red = par->red[regno/2]; 2281 blue = par->blue[regno/2]; 2282 regno <<= 2; 2283 } else if (par->crtc.bpp == 16) 2284 regno <<= 3; 2285 aty128_st_pal(regno, red, green, blue, par); 2286 2287 return 0; 2288} 2289 2290#define ATY_MIRROR_LCD_ON 0x00000001 2291#define ATY_MIRROR_CRT_ON 0x00000002 2292 2293/* out param: u32* backlight value: 0 to 15 */ 2294#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2295/* in param: u32* backlight value: 0 to 15 */ 2296#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2297 2298static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2299{ 2300 struct aty128fb_par *par = info->par; 2301 u32 value; 2302 int rc; 2303 2304 switch (cmd) { 2305 case FBIO_ATY128_SET_MIRROR: 2306 if (par->chip_gen != rage_M3) 2307 return -EINVAL; 2308 rc = get_user(value, (__u32 __user *)arg); 2309 if (rc) 2310 return rc; 2311 par->lcd_on = (value & 0x01) != 0; 2312 par->crt_on = (value & 0x02) != 0; 2313 if (!par->crt_on && !par->lcd_on) 2314 par->lcd_on = 1; 2315 aty128_set_crt_enable(par, par->crt_on); 2316 aty128_set_lcd_enable(par, par->lcd_on); 2317 return 0; 2318 case FBIO_ATY128_GET_MIRROR: 2319 if (par->chip_gen != rage_M3) 2320 return -EINVAL; 2321 value = (par->crt_on << 1) | par->lcd_on; 2322 return put_user(value, (__u32 __user *)arg); 2323 } 2324 return -EINVAL; 2325} 2326 2327static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2328{ 2329 u32 pmgt; 2330 2331 if (!par->pdev->pm_cap) 2332 return; 2333 2334 /* Set the chip into the appropriate suspend mode (we use D2, 2335 * D3 would require a complete re-initialisation of the chip, 2336 * including PCI config registers, clocks, AGP configuration, ...) 2337 * 2338 * For resume, the core will have already brought us back to D0 2339 */ 2340 if (suspend) { 2341 /* Make sure CRTC2 is reset. Remove that the day we decide to 2342 * actually use CRTC2 and replace it with real code for disabling 2343 * the CRTC2 output during sleep 2344 */ 2345 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2346 ~(CRTC2_EN)); 2347 2348 /* Set the power management mode to be PCI based */ 2349 /* Use this magic value for now */ 2350 pmgt = 0x0c005407; 2351 aty_st_pll(POWER_MANAGEMENT, pmgt); 2352 (void)aty_ld_pll(POWER_MANAGEMENT); 2353 aty_st_le32(BUS_CNTL1, 0x00000010); 2354 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2355 msleep(100); 2356 } 2357} 2358 2359static int aty128_pci_suspend_late(struct device *dev, pm_message_t state) 2360{ 2361 struct pci_dev *pdev = to_pci_dev(dev); 2362 struct fb_info *info = pci_get_drvdata(pdev); 2363 struct aty128fb_par *par = info->par; 2364 2365 /* We don't do anything but D2, for now we return 0, but 2366 * we may want to change that. How do we know if the BIOS 2367 * can properly take care of D3 ? Also, with swsusp, we 2368 * know we'll be rebooted, ... 2369 */ 2370#ifndef CONFIG_PPC_PMAC 2371 /* HACK ALERT ! Once I find a proper way to say to each driver 2372 * individually what will happen with it's PCI slot, I'll change 2373 * that. On laptops, the AGP slot is just unclocked, so D2 is 2374 * expected, while on desktops, the card is powered off 2375 */ 2376 return 0; 2377#endif /* CONFIG_PPC_PMAC */ 2378 2379 if (state.event == pdev->dev.power.power_state.event) 2380 return 0; 2381 2382 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2383 2384 console_lock(); 2385 2386 fb_set_suspend(info, 1); 2387 2388 /* Make sure engine is reset */ 2389 wait_for_idle(par); 2390 aty128_reset_engine(par); 2391 wait_for_idle(par); 2392 2393 /* Blank display and LCD */ 2394 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2395 2396 /* Sleep */ 2397 par->asleep = 1; 2398 par->lock_blank = 1; 2399 2400#ifdef CONFIG_PPC_PMAC 2401 /* On powermac, we have hooks to properly suspend/resume AGP now, 2402 * use them here. We'll ultimately need some generic support here, 2403 * but the generic code isn't quite ready for that yet 2404 */ 2405 pmac_suspend_agp_for_card(pdev); 2406#endif /* CONFIG_PPC_PMAC */ 2407 2408 /* We need a way to make sure the fbdev layer will _not_ touch the 2409 * framebuffer before we put the chip to suspend state. On 2.4, I 2410 * used dummy fb ops, 2.5 need proper support for this at the 2411 * fbdev level 2412 */ 2413 if (state.event != PM_EVENT_ON) 2414 aty128_set_suspend(par, 1); 2415 2416 console_unlock(); 2417 2418 pdev->dev.power.power_state = state; 2419 2420 return 0; 2421} 2422 2423static int __maybe_unused aty128_pci_suspend(struct device *dev) 2424{ 2425 return aty128_pci_suspend_late(dev, PMSG_SUSPEND); 2426} 2427 2428static int __maybe_unused aty128_pci_hibernate(struct device *dev) 2429{ 2430 return aty128_pci_suspend_late(dev, PMSG_HIBERNATE); 2431} 2432 2433static int __maybe_unused aty128_pci_freeze(struct device *dev) 2434{ 2435 return aty128_pci_suspend_late(dev, PMSG_FREEZE); 2436} 2437 2438static int aty128_do_resume(struct pci_dev *pdev) 2439{ 2440 struct fb_info *info = pci_get_drvdata(pdev); 2441 struct aty128fb_par *par = info->par; 2442 2443 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2444 return 0; 2445 2446 /* PCI state will have been restored by the core, so 2447 * we should be in D0 now with our config space fully 2448 * restored 2449 */ 2450 2451 /* Wakeup chip */ 2452 aty128_set_suspend(par, 0); 2453 par->asleep = 0; 2454 2455 /* Restore display & engine */ 2456 aty128_reset_engine(par); 2457 wait_for_idle(par); 2458 aty128fb_set_par(info); 2459 fb_pan_display(info, &info->var); 2460 fb_set_cmap(&info->cmap, info); 2461 2462 /* Refresh */ 2463 fb_set_suspend(info, 0); 2464 2465 /* Unblank */ 2466 par->lock_blank = 0; 2467 aty128fb_blank(0, info); 2468 2469#ifdef CONFIG_PPC_PMAC 2470 /* On powermac, we have hooks to properly suspend/resume AGP now, 2471 * use them here. We'll ultimately need some generic support here, 2472 * but the generic code isn't quite ready for that yet 2473 */ 2474 pmac_resume_agp_for_card(pdev); 2475#endif /* CONFIG_PPC_PMAC */ 2476 2477 pdev->dev.power.power_state = PMSG_ON; 2478 2479 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2480 2481 return 0; 2482} 2483 2484static int __maybe_unused aty128_pci_resume(struct device *dev) 2485{ 2486 int rc; 2487 2488 console_lock(); 2489 rc = aty128_do_resume(to_pci_dev(dev)); 2490 console_unlock(); 2491 2492 return rc; 2493} 2494 2495 2496static int aty128fb_init(void) 2497{ 2498#ifndef MODULE 2499 char *option = NULL; 2500 2501 if (fb_get_options("aty128fb", &option)) 2502 return -ENODEV; 2503 aty128fb_setup(option); 2504#endif 2505 2506 return pci_register_driver(&aty128fb_driver); 2507} 2508 2509static void __exit aty128fb_exit(void) 2510{ 2511 pci_unregister_driver(&aty128fb_driver); 2512} 2513 2514module_init(aty128fb_init); 2515 2516module_exit(aty128fb_exit); 2517 2518MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2519MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2520MODULE_LICENSE("GPL"); 2521module_param(mode_option, charp, 0); 2522MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2523module_param_named(nomtrr, mtrr, invbool, 0); 2524MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2525