18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * (C) Copyright 2008 48c2ecf20Sopenharmony_ci * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This driver implements a lcd device for the ILITEK 922x display 78c2ecf20Sopenharmony_ci * controller. The interface to the display is SPI and the display's 88c2ecf20Sopenharmony_ci * memory is cyclically updated over the RGB interface. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <linux/fb.h> 128c2ecf20Sopenharmony_ci#include <linux/delay.h> 138c2ecf20Sopenharmony_ci#include <linux/errno.h> 148c2ecf20Sopenharmony_ci#include <linux/init.h> 158c2ecf20Sopenharmony_ci#include <linux/kernel.h> 168c2ecf20Sopenharmony_ci#include <linux/lcd.h> 178c2ecf20Sopenharmony_ci#include <linux/module.h> 188c2ecf20Sopenharmony_ci#include <linux/of.h> 198c2ecf20Sopenharmony_ci#include <linux/slab.h> 208c2ecf20Sopenharmony_ci#include <linux/spi/spi.h> 218c2ecf20Sopenharmony_ci#include <linux/string.h> 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci/* Register offset, see manual section 8.2 */ 248c2ecf20Sopenharmony_ci#define REG_START_OSCILLATION 0x00 258c2ecf20Sopenharmony_ci#define REG_DRIVER_CODE_READ 0x00 268c2ecf20Sopenharmony_ci#define REG_DRIVER_OUTPUT_CONTROL 0x01 278c2ecf20Sopenharmony_ci#define REG_LCD_AC_DRIVEING_CONTROL 0x02 288c2ecf20Sopenharmony_ci#define REG_ENTRY_MODE 0x03 298c2ecf20Sopenharmony_ci#define REG_COMPARE_1 0x04 308c2ecf20Sopenharmony_ci#define REG_COMPARE_2 0x05 318c2ecf20Sopenharmony_ci#define REG_DISPLAY_CONTROL_1 0x07 328c2ecf20Sopenharmony_ci#define REG_DISPLAY_CONTROL_2 0x08 338c2ecf20Sopenharmony_ci#define REG_DISPLAY_CONTROL_3 0x09 348c2ecf20Sopenharmony_ci#define REG_FRAME_CYCLE_CONTROL 0x0B 358c2ecf20Sopenharmony_ci#define REG_EXT_INTF_CONTROL 0x0C 368c2ecf20Sopenharmony_ci#define REG_POWER_CONTROL_1 0x10 378c2ecf20Sopenharmony_ci#define REG_POWER_CONTROL_2 0x11 388c2ecf20Sopenharmony_ci#define REG_POWER_CONTROL_3 0x12 398c2ecf20Sopenharmony_ci#define REG_POWER_CONTROL_4 0x13 408c2ecf20Sopenharmony_ci#define REG_RAM_ADDRESS_SET 0x21 418c2ecf20Sopenharmony_ci#define REG_WRITE_DATA_TO_GRAM 0x22 428c2ecf20Sopenharmony_ci#define REG_RAM_WRITE_MASK1 0x23 438c2ecf20Sopenharmony_ci#define REG_RAM_WRITE_MASK2 0x24 448c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_1 0x30 458c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_2 0x31 468c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_3 0x32 478c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_4 0x33 488c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_5 0x34 498c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_6 0x35 508c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_7 0x36 518c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_8 0x37 528c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_9 0x38 538c2ecf20Sopenharmony_ci#define REG_GAMMA_CONTROL_10 0x39 548c2ecf20Sopenharmony_ci#define REG_GATE_SCAN_CONTROL 0x40 558c2ecf20Sopenharmony_ci#define REG_VERT_SCROLL_CONTROL 0x41 568c2ecf20Sopenharmony_ci#define REG_FIRST_SCREEN_DRIVE_POS 0x42 578c2ecf20Sopenharmony_ci#define REG_SECOND_SCREEN_DRIVE_POS 0x43 588c2ecf20Sopenharmony_ci#define REG_RAM_ADDR_POS_H 0x44 598c2ecf20Sopenharmony_ci#define REG_RAM_ADDR_POS_V 0x45 608c2ecf20Sopenharmony_ci#define REG_OSCILLATOR_CONTROL 0x4F 618c2ecf20Sopenharmony_ci#define REG_GPIO 0x60 628c2ecf20Sopenharmony_ci#define REG_OTP_VCM_PROGRAMMING 0x61 638c2ecf20Sopenharmony_ci#define REG_OTP_VCM_STATUS_ENABLE 0x62 648c2ecf20Sopenharmony_ci#define REG_OTP_PROGRAMMING_ID_KEY 0x65 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci/* 678c2ecf20Sopenharmony_ci * maximum frequency for register access 688c2ecf20Sopenharmony_ci * (not for the GRAM access) 698c2ecf20Sopenharmony_ci */ 708c2ecf20Sopenharmony_ci#define ILITEK_MAX_FREQ_REG 4000000 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci/* 738c2ecf20Sopenharmony_ci * Device ID as found in the datasheet (supports 9221 and 9222) 748c2ecf20Sopenharmony_ci */ 758c2ecf20Sopenharmony_ci#define ILITEK_DEVICE_ID 0x9220 768c2ecf20Sopenharmony_ci#define ILITEK_DEVICE_ID_MASK 0xFFF0 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci/* Last two bits in the START BYTE */ 798c2ecf20Sopenharmony_ci#define START_RS_INDEX 0 808c2ecf20Sopenharmony_ci#define START_RS_REG 1 818c2ecf20Sopenharmony_ci#define START_RW_WRITE 0 828c2ecf20Sopenharmony_ci#define START_RW_READ 1 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci/** 858c2ecf20Sopenharmony_ci * START_BYTE(id, rs, rw) 868c2ecf20Sopenharmony_ci * 878c2ecf20Sopenharmony_ci * Set the start byte according to the required operation. 888c2ecf20Sopenharmony_ci * The start byte is defined as: 898c2ecf20Sopenharmony_ci * ---------------------------------- 908c2ecf20Sopenharmony_ci * | 0 | 1 | 1 | 1 | 0 | ID | RS | RW | 918c2ecf20Sopenharmony_ci * ---------------------------------- 928c2ecf20Sopenharmony_ci * @id: display's id as set by the manufacturer 938c2ecf20Sopenharmony_ci * @rs: operation type bit, one of: 948c2ecf20Sopenharmony_ci * - START_RS_INDEX set the index register 958c2ecf20Sopenharmony_ci * - START_RS_REG write/read registers/GRAM 968c2ecf20Sopenharmony_ci * @rw: read/write operation 978c2ecf20Sopenharmony_ci * - START_RW_WRITE write 988c2ecf20Sopenharmony_ci * - START_RW_READ read 998c2ecf20Sopenharmony_ci */ 1008c2ecf20Sopenharmony_ci#define START_BYTE(id, rs, rw) \ 1018c2ecf20Sopenharmony_ci (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01)) 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci/** 1048c2ecf20Sopenharmony_ci * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency 1058c2ecf20Sopenharmony_ci * for the SPI transfer. According to the datasheet, the controller 1068c2ecf20Sopenharmony_ci * accept higher frequency for the GRAM transfer, but it requires 1078c2ecf20Sopenharmony_ci * lower frequency when the registers are read/written. 1088c2ecf20Sopenharmony_ci * The macro sets the frequency in the spi_transfer structure if 1098c2ecf20Sopenharmony_ci * the frequency exceeds the maximum value. 1108c2ecf20Sopenharmony_ci * @s: pointer to an SPI device 1118c2ecf20Sopenharmony_ci * @x: pointer to the read/write buffer pair 1128c2ecf20Sopenharmony_ci */ 1138c2ecf20Sopenharmony_ci#define CHECK_FREQ_REG(s, x) \ 1148c2ecf20Sopenharmony_ci do { \ 1158c2ecf20Sopenharmony_ci if (s->max_speed_hz > ILITEK_MAX_FREQ_REG) \ 1168c2ecf20Sopenharmony_ci ((struct spi_transfer *)x)->speed_hz = \ 1178c2ecf20Sopenharmony_ci ILITEK_MAX_FREQ_REG; \ 1188c2ecf20Sopenharmony_ci } while (0) 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci#define CMD_BUFSIZE 16 1218c2ecf20Sopenharmony_ci 1228c2ecf20Sopenharmony_ci#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL) 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ci#define set_tx_byte(b) (tx_invert ? ~(b) : b) 1258c2ecf20Sopenharmony_ci 1268c2ecf20Sopenharmony_ci/* 1278c2ecf20Sopenharmony_ci * ili922x_id - id as set by manufacturer 1288c2ecf20Sopenharmony_ci */ 1298c2ecf20Sopenharmony_cistatic int ili922x_id = 1; 1308c2ecf20Sopenharmony_cimodule_param(ili922x_id, int, 0); 1318c2ecf20Sopenharmony_ci 1328c2ecf20Sopenharmony_cistatic int tx_invert; 1338c2ecf20Sopenharmony_cimodule_param(tx_invert, int, 0); 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_ci/* 1368c2ecf20Sopenharmony_ci * driver's private structure 1378c2ecf20Sopenharmony_ci */ 1388c2ecf20Sopenharmony_cistruct ili922x { 1398c2ecf20Sopenharmony_ci struct spi_device *spi; 1408c2ecf20Sopenharmony_ci struct lcd_device *ld; 1418c2ecf20Sopenharmony_ci int power; 1428c2ecf20Sopenharmony_ci}; 1438c2ecf20Sopenharmony_ci 1448c2ecf20Sopenharmony_ci/** 1458c2ecf20Sopenharmony_ci * ili922x_read_status - read status register from display 1468c2ecf20Sopenharmony_ci * @spi: spi device 1478c2ecf20Sopenharmony_ci * @rs: output value 1488c2ecf20Sopenharmony_ci */ 1498c2ecf20Sopenharmony_cistatic int ili922x_read_status(struct spi_device *spi, u16 *rs) 1508c2ecf20Sopenharmony_ci{ 1518c2ecf20Sopenharmony_ci struct spi_message msg; 1528c2ecf20Sopenharmony_ci struct spi_transfer xfer; 1538c2ecf20Sopenharmony_ci unsigned char tbuf[CMD_BUFSIZE]; 1548c2ecf20Sopenharmony_ci unsigned char rbuf[CMD_BUFSIZE]; 1558c2ecf20Sopenharmony_ci int ret, i; 1568c2ecf20Sopenharmony_ci 1578c2ecf20Sopenharmony_ci memset(&xfer, 0, sizeof(struct spi_transfer)); 1588c2ecf20Sopenharmony_ci spi_message_init(&msg); 1598c2ecf20Sopenharmony_ci xfer.tx_buf = tbuf; 1608c2ecf20Sopenharmony_ci xfer.rx_buf = rbuf; 1618c2ecf20Sopenharmony_ci xfer.cs_change = 1; 1628c2ecf20Sopenharmony_ci CHECK_FREQ_REG(spi, &xfer); 1638c2ecf20Sopenharmony_ci 1648c2ecf20Sopenharmony_ci tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX, 1658c2ecf20Sopenharmony_ci START_RW_READ)); 1668c2ecf20Sopenharmony_ci /* 1678c2ecf20Sopenharmony_ci * we need 4-byte xfer here due to invalid dummy byte 1688c2ecf20Sopenharmony_ci * received after start byte 1698c2ecf20Sopenharmony_ci */ 1708c2ecf20Sopenharmony_ci for (i = 1; i < 4; i++) 1718c2ecf20Sopenharmony_ci tbuf[i] = set_tx_byte(0); /* dummy */ 1728c2ecf20Sopenharmony_ci 1738c2ecf20Sopenharmony_ci xfer.bits_per_word = 8; 1748c2ecf20Sopenharmony_ci xfer.len = 4; 1758c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer, &msg); 1768c2ecf20Sopenharmony_ci ret = spi_sync(spi, &msg); 1778c2ecf20Sopenharmony_ci if (ret < 0) { 1788c2ecf20Sopenharmony_ci dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret); 1798c2ecf20Sopenharmony_ci return ret; 1808c2ecf20Sopenharmony_ci } 1818c2ecf20Sopenharmony_ci 1828c2ecf20Sopenharmony_ci *rs = (rbuf[2] << 8) + rbuf[3]; 1838c2ecf20Sopenharmony_ci return 0; 1848c2ecf20Sopenharmony_ci} 1858c2ecf20Sopenharmony_ci 1868c2ecf20Sopenharmony_ci/** 1878c2ecf20Sopenharmony_ci * ili922x_read - read register from display 1888c2ecf20Sopenharmony_ci * @spi: spi device 1898c2ecf20Sopenharmony_ci * @reg: offset of the register to be read 1908c2ecf20Sopenharmony_ci * @rx: output value 1918c2ecf20Sopenharmony_ci */ 1928c2ecf20Sopenharmony_cistatic int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx) 1938c2ecf20Sopenharmony_ci{ 1948c2ecf20Sopenharmony_ci struct spi_message msg; 1958c2ecf20Sopenharmony_ci struct spi_transfer xfer_regindex, xfer_regvalue; 1968c2ecf20Sopenharmony_ci unsigned char tbuf[CMD_BUFSIZE]; 1978c2ecf20Sopenharmony_ci unsigned char rbuf[CMD_BUFSIZE]; 1988c2ecf20Sopenharmony_ci int ret, len = 0, send_bytes; 1998c2ecf20Sopenharmony_ci 2008c2ecf20Sopenharmony_ci memset(&xfer_regindex, 0, sizeof(struct spi_transfer)); 2018c2ecf20Sopenharmony_ci memset(&xfer_regvalue, 0, sizeof(struct spi_transfer)); 2028c2ecf20Sopenharmony_ci spi_message_init(&msg); 2038c2ecf20Sopenharmony_ci xfer_regindex.tx_buf = tbuf; 2048c2ecf20Sopenharmony_ci xfer_regindex.rx_buf = rbuf; 2058c2ecf20Sopenharmony_ci xfer_regindex.cs_change = 1; 2068c2ecf20Sopenharmony_ci CHECK_FREQ_REG(spi, &xfer_regindex); 2078c2ecf20Sopenharmony_ci 2088c2ecf20Sopenharmony_ci tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX, 2098c2ecf20Sopenharmony_ci START_RW_WRITE)); 2108c2ecf20Sopenharmony_ci tbuf[1] = set_tx_byte(0); 2118c2ecf20Sopenharmony_ci tbuf[2] = set_tx_byte(reg); 2128c2ecf20Sopenharmony_ci xfer_regindex.bits_per_word = 8; 2138c2ecf20Sopenharmony_ci len = xfer_regindex.len = 3; 2148c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer_regindex, &msg); 2158c2ecf20Sopenharmony_ci 2168c2ecf20Sopenharmony_ci send_bytes = len; 2178c2ecf20Sopenharmony_ci 2188c2ecf20Sopenharmony_ci tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG, 2198c2ecf20Sopenharmony_ci START_RW_READ)); 2208c2ecf20Sopenharmony_ci tbuf[len++] = set_tx_byte(0); 2218c2ecf20Sopenharmony_ci tbuf[len] = set_tx_byte(0); 2228c2ecf20Sopenharmony_ci 2238c2ecf20Sopenharmony_ci xfer_regvalue.cs_change = 1; 2248c2ecf20Sopenharmony_ci xfer_regvalue.len = 3; 2258c2ecf20Sopenharmony_ci xfer_regvalue.tx_buf = &tbuf[send_bytes]; 2268c2ecf20Sopenharmony_ci xfer_regvalue.rx_buf = &rbuf[send_bytes]; 2278c2ecf20Sopenharmony_ci CHECK_FREQ_REG(spi, &xfer_regvalue); 2288c2ecf20Sopenharmony_ci 2298c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer_regvalue, &msg); 2308c2ecf20Sopenharmony_ci ret = spi_sync(spi, &msg); 2318c2ecf20Sopenharmony_ci if (ret < 0) { 2328c2ecf20Sopenharmony_ci dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret); 2338c2ecf20Sopenharmony_ci return ret; 2348c2ecf20Sopenharmony_ci } 2358c2ecf20Sopenharmony_ci 2368c2ecf20Sopenharmony_ci *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes]; 2378c2ecf20Sopenharmony_ci return 0; 2388c2ecf20Sopenharmony_ci} 2398c2ecf20Sopenharmony_ci 2408c2ecf20Sopenharmony_ci/** 2418c2ecf20Sopenharmony_ci * ili922x_write - write a controller register 2428c2ecf20Sopenharmony_ci * @spi: struct spi_device * 2438c2ecf20Sopenharmony_ci * @reg: offset of the register to be written 2448c2ecf20Sopenharmony_ci * @value: value to be written 2458c2ecf20Sopenharmony_ci */ 2468c2ecf20Sopenharmony_cistatic int ili922x_write(struct spi_device *spi, u8 reg, u16 value) 2478c2ecf20Sopenharmony_ci{ 2488c2ecf20Sopenharmony_ci struct spi_message msg; 2498c2ecf20Sopenharmony_ci struct spi_transfer xfer_regindex, xfer_regvalue; 2508c2ecf20Sopenharmony_ci unsigned char tbuf[CMD_BUFSIZE]; 2518c2ecf20Sopenharmony_ci unsigned char rbuf[CMD_BUFSIZE]; 2528c2ecf20Sopenharmony_ci int ret; 2538c2ecf20Sopenharmony_ci 2548c2ecf20Sopenharmony_ci memset(&xfer_regindex, 0, sizeof(struct spi_transfer)); 2558c2ecf20Sopenharmony_ci memset(&xfer_regvalue, 0, sizeof(struct spi_transfer)); 2568c2ecf20Sopenharmony_ci 2578c2ecf20Sopenharmony_ci spi_message_init(&msg); 2588c2ecf20Sopenharmony_ci xfer_regindex.tx_buf = tbuf; 2598c2ecf20Sopenharmony_ci xfer_regindex.rx_buf = rbuf; 2608c2ecf20Sopenharmony_ci xfer_regindex.cs_change = 1; 2618c2ecf20Sopenharmony_ci CHECK_FREQ_REG(spi, &xfer_regindex); 2628c2ecf20Sopenharmony_ci 2638c2ecf20Sopenharmony_ci tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX, 2648c2ecf20Sopenharmony_ci START_RW_WRITE)); 2658c2ecf20Sopenharmony_ci tbuf[1] = set_tx_byte(0); 2668c2ecf20Sopenharmony_ci tbuf[2] = set_tx_byte(reg); 2678c2ecf20Sopenharmony_ci xfer_regindex.bits_per_word = 8; 2688c2ecf20Sopenharmony_ci xfer_regindex.len = 3; 2698c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer_regindex, &msg); 2708c2ecf20Sopenharmony_ci 2718c2ecf20Sopenharmony_ci ret = spi_sync(spi, &msg); 2728c2ecf20Sopenharmony_ci 2738c2ecf20Sopenharmony_ci spi_message_init(&msg); 2748c2ecf20Sopenharmony_ci tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG, 2758c2ecf20Sopenharmony_ci START_RW_WRITE)); 2768c2ecf20Sopenharmony_ci tbuf[1] = set_tx_byte((value & 0xFF00) >> 8); 2778c2ecf20Sopenharmony_ci tbuf[2] = set_tx_byte(value & 0x00FF); 2788c2ecf20Sopenharmony_ci 2798c2ecf20Sopenharmony_ci xfer_regvalue.cs_change = 1; 2808c2ecf20Sopenharmony_ci xfer_regvalue.len = 3; 2818c2ecf20Sopenharmony_ci xfer_regvalue.tx_buf = tbuf; 2828c2ecf20Sopenharmony_ci xfer_regvalue.rx_buf = rbuf; 2838c2ecf20Sopenharmony_ci CHECK_FREQ_REG(spi, &xfer_regvalue); 2848c2ecf20Sopenharmony_ci 2858c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer_regvalue, &msg); 2868c2ecf20Sopenharmony_ci 2878c2ecf20Sopenharmony_ci ret = spi_sync(spi, &msg); 2888c2ecf20Sopenharmony_ci if (ret < 0) { 2898c2ecf20Sopenharmony_ci dev_err(&spi->dev, "Error sending SPI message 0x%x", ret); 2908c2ecf20Sopenharmony_ci return ret; 2918c2ecf20Sopenharmony_ci } 2928c2ecf20Sopenharmony_ci return 0; 2938c2ecf20Sopenharmony_ci} 2948c2ecf20Sopenharmony_ci 2958c2ecf20Sopenharmony_ci#ifdef DEBUG 2968c2ecf20Sopenharmony_ci/** 2978c2ecf20Sopenharmony_ci * ili922x_reg_dump - dump all registers 2988c2ecf20Sopenharmony_ci * 2998c2ecf20Sopenharmony_ci * @spi: pointer to an SPI device 3008c2ecf20Sopenharmony_ci */ 3018c2ecf20Sopenharmony_cistatic void ili922x_reg_dump(struct spi_device *spi) 3028c2ecf20Sopenharmony_ci{ 3038c2ecf20Sopenharmony_ci u8 reg; 3048c2ecf20Sopenharmony_ci u16 rx; 3058c2ecf20Sopenharmony_ci 3068c2ecf20Sopenharmony_ci dev_dbg(&spi->dev, "ILI922x configuration registers:\n"); 3078c2ecf20Sopenharmony_ci for (reg = REG_START_OSCILLATION; 3088c2ecf20Sopenharmony_ci reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) { 3098c2ecf20Sopenharmony_ci ili922x_read(spi, reg, &rx); 3108c2ecf20Sopenharmony_ci dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx); 3118c2ecf20Sopenharmony_ci } 3128c2ecf20Sopenharmony_ci} 3138c2ecf20Sopenharmony_ci#else 3148c2ecf20Sopenharmony_cistatic inline void ili922x_reg_dump(struct spi_device *spi) {} 3158c2ecf20Sopenharmony_ci#endif 3168c2ecf20Sopenharmony_ci 3178c2ecf20Sopenharmony_ci/** 3188c2ecf20Sopenharmony_ci * set_write_to_gram_reg - initialize the display to write the GRAM 3198c2ecf20Sopenharmony_ci * @spi: spi device 3208c2ecf20Sopenharmony_ci */ 3218c2ecf20Sopenharmony_cistatic void set_write_to_gram_reg(struct spi_device *spi) 3228c2ecf20Sopenharmony_ci{ 3238c2ecf20Sopenharmony_ci struct spi_message msg; 3248c2ecf20Sopenharmony_ci struct spi_transfer xfer; 3258c2ecf20Sopenharmony_ci unsigned char tbuf[CMD_BUFSIZE]; 3268c2ecf20Sopenharmony_ci 3278c2ecf20Sopenharmony_ci memset(&xfer, 0, sizeof(struct spi_transfer)); 3288c2ecf20Sopenharmony_ci 3298c2ecf20Sopenharmony_ci spi_message_init(&msg); 3308c2ecf20Sopenharmony_ci xfer.tx_buf = tbuf; 3318c2ecf20Sopenharmony_ci xfer.rx_buf = NULL; 3328c2ecf20Sopenharmony_ci xfer.cs_change = 1; 3338c2ecf20Sopenharmony_ci 3348c2ecf20Sopenharmony_ci tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE); 3358c2ecf20Sopenharmony_ci tbuf[1] = 0; 3368c2ecf20Sopenharmony_ci tbuf[2] = REG_WRITE_DATA_TO_GRAM; 3378c2ecf20Sopenharmony_ci 3388c2ecf20Sopenharmony_ci xfer.bits_per_word = 8; 3398c2ecf20Sopenharmony_ci xfer.len = 3; 3408c2ecf20Sopenharmony_ci spi_message_add_tail(&xfer, &msg); 3418c2ecf20Sopenharmony_ci spi_sync(spi, &msg); 3428c2ecf20Sopenharmony_ci} 3438c2ecf20Sopenharmony_ci 3448c2ecf20Sopenharmony_ci/** 3458c2ecf20Sopenharmony_ci * ili922x_poweron - turn the display on 3468c2ecf20Sopenharmony_ci * @spi: spi device 3478c2ecf20Sopenharmony_ci * 3488c2ecf20Sopenharmony_ci * The sequence to turn on the display is taken from 3498c2ecf20Sopenharmony_ci * the datasheet and/or the example code provided by the 3508c2ecf20Sopenharmony_ci * manufacturer. 3518c2ecf20Sopenharmony_ci */ 3528c2ecf20Sopenharmony_cistatic int ili922x_poweron(struct spi_device *spi) 3538c2ecf20Sopenharmony_ci{ 3548c2ecf20Sopenharmony_ci int ret; 3558c2ecf20Sopenharmony_ci 3568c2ecf20Sopenharmony_ci /* Power on */ 3578c2ecf20Sopenharmony_ci ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000); 3588c2ecf20Sopenharmony_ci usleep_range(10000, 10500); 3598c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000); 3608c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000); 3618c2ecf20Sopenharmony_ci msleep(40); 3628c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000); 3638c2ecf20Sopenharmony_ci msleep(40); 3648c2ecf20Sopenharmony_ci /* register 0x56 is not documented in the datasheet */ 3658c2ecf20Sopenharmony_ci ret += ili922x_write(spi, 0x56, 0x080F); 3668c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240); 3678c2ecf20Sopenharmony_ci usleep_range(10000, 10500); 3688c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000); 3698c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014); 3708c2ecf20Sopenharmony_ci msleep(40); 3718c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319); 3728c2ecf20Sopenharmony_ci msleep(40); 3738c2ecf20Sopenharmony_ci 3748c2ecf20Sopenharmony_ci return ret; 3758c2ecf20Sopenharmony_ci} 3768c2ecf20Sopenharmony_ci 3778c2ecf20Sopenharmony_ci/** 3788c2ecf20Sopenharmony_ci * ili922x_poweroff - turn the display off 3798c2ecf20Sopenharmony_ci * @spi: spi device 3808c2ecf20Sopenharmony_ci */ 3818c2ecf20Sopenharmony_cistatic int ili922x_poweroff(struct spi_device *spi) 3828c2ecf20Sopenharmony_ci{ 3838c2ecf20Sopenharmony_ci int ret; 3848c2ecf20Sopenharmony_ci 3858c2ecf20Sopenharmony_ci /* Power off */ 3868c2ecf20Sopenharmony_ci ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000); 3878c2ecf20Sopenharmony_ci usleep_range(10000, 10500); 3888c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000); 3898c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000); 3908c2ecf20Sopenharmony_ci msleep(40); 3918c2ecf20Sopenharmony_ci ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000); 3928c2ecf20Sopenharmony_ci msleep(40); 3938c2ecf20Sopenharmony_ci 3948c2ecf20Sopenharmony_ci return ret; 3958c2ecf20Sopenharmony_ci} 3968c2ecf20Sopenharmony_ci 3978c2ecf20Sopenharmony_ci/** 3988c2ecf20Sopenharmony_ci * ili922x_display_init - initialize the display by setting 3998c2ecf20Sopenharmony_ci * the configuration registers 4008c2ecf20Sopenharmony_ci * @spi: spi device 4018c2ecf20Sopenharmony_ci */ 4028c2ecf20Sopenharmony_cistatic void ili922x_display_init(struct spi_device *spi) 4038c2ecf20Sopenharmony_ci{ 4048c2ecf20Sopenharmony_ci ili922x_write(spi, REG_START_OSCILLATION, 1); 4058c2ecf20Sopenharmony_ci usleep_range(10000, 10500); 4068c2ecf20Sopenharmony_ci ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B); 4078c2ecf20Sopenharmony_ci ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700); 4088c2ecf20Sopenharmony_ci ili922x_write(spi, REG_ENTRY_MODE, 0x1030); 4098c2ecf20Sopenharmony_ci ili922x_write(spi, REG_COMPARE_1, 0x0000); 4108c2ecf20Sopenharmony_ci ili922x_write(spi, REG_COMPARE_2, 0x0000); 4118c2ecf20Sopenharmony_ci ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037); 4128c2ecf20Sopenharmony_ci ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202); 4138c2ecf20Sopenharmony_ci ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000); 4148c2ecf20Sopenharmony_ci ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000); 4158c2ecf20Sopenharmony_ci 4168c2ecf20Sopenharmony_ci /* Set RGB interface */ 4178c2ecf20Sopenharmony_ci ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110); 4188c2ecf20Sopenharmony_ci 4198c2ecf20Sopenharmony_ci ili922x_poweron(spi); 4208c2ecf20Sopenharmony_ci 4218c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302); 4228c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407); 4238c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304); 4248c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203); 4258c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706); 4268c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407); 4278c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706); 4288c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000); 4298c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06); 4308c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00); 4318c2ecf20Sopenharmony_ci ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000); 4328c2ecf20Sopenharmony_ci ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000); 4338c2ecf20Sopenharmony_ci ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000); 4348c2ecf20Sopenharmony_ci ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00); 4358c2ecf20Sopenharmony_ci ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00); 4368c2ecf20Sopenharmony_ci ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00); 4378c2ecf20Sopenharmony_ci ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00); 4388c2ecf20Sopenharmony_ci ili922x_reg_dump(spi); 4398c2ecf20Sopenharmony_ci set_write_to_gram_reg(spi); 4408c2ecf20Sopenharmony_ci} 4418c2ecf20Sopenharmony_ci 4428c2ecf20Sopenharmony_cistatic int ili922x_lcd_power(struct ili922x *lcd, int power) 4438c2ecf20Sopenharmony_ci{ 4448c2ecf20Sopenharmony_ci int ret = 0; 4458c2ecf20Sopenharmony_ci 4468c2ecf20Sopenharmony_ci if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power)) 4478c2ecf20Sopenharmony_ci ret = ili922x_poweron(lcd->spi); 4488c2ecf20Sopenharmony_ci else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power)) 4498c2ecf20Sopenharmony_ci ret = ili922x_poweroff(lcd->spi); 4508c2ecf20Sopenharmony_ci 4518c2ecf20Sopenharmony_ci if (!ret) 4528c2ecf20Sopenharmony_ci lcd->power = power; 4538c2ecf20Sopenharmony_ci 4548c2ecf20Sopenharmony_ci return ret; 4558c2ecf20Sopenharmony_ci} 4568c2ecf20Sopenharmony_ci 4578c2ecf20Sopenharmony_cistatic int ili922x_set_power(struct lcd_device *ld, int power) 4588c2ecf20Sopenharmony_ci{ 4598c2ecf20Sopenharmony_ci struct ili922x *ili = lcd_get_data(ld); 4608c2ecf20Sopenharmony_ci 4618c2ecf20Sopenharmony_ci return ili922x_lcd_power(ili, power); 4628c2ecf20Sopenharmony_ci} 4638c2ecf20Sopenharmony_ci 4648c2ecf20Sopenharmony_cistatic int ili922x_get_power(struct lcd_device *ld) 4658c2ecf20Sopenharmony_ci{ 4668c2ecf20Sopenharmony_ci struct ili922x *ili = lcd_get_data(ld); 4678c2ecf20Sopenharmony_ci 4688c2ecf20Sopenharmony_ci return ili->power; 4698c2ecf20Sopenharmony_ci} 4708c2ecf20Sopenharmony_ci 4718c2ecf20Sopenharmony_cistatic struct lcd_ops ili922x_ops = { 4728c2ecf20Sopenharmony_ci .get_power = ili922x_get_power, 4738c2ecf20Sopenharmony_ci .set_power = ili922x_set_power, 4748c2ecf20Sopenharmony_ci}; 4758c2ecf20Sopenharmony_ci 4768c2ecf20Sopenharmony_cistatic int ili922x_probe(struct spi_device *spi) 4778c2ecf20Sopenharmony_ci{ 4788c2ecf20Sopenharmony_ci struct ili922x *ili; 4798c2ecf20Sopenharmony_ci struct lcd_device *lcd; 4808c2ecf20Sopenharmony_ci int ret; 4818c2ecf20Sopenharmony_ci u16 reg = 0; 4828c2ecf20Sopenharmony_ci 4838c2ecf20Sopenharmony_ci ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL); 4848c2ecf20Sopenharmony_ci if (!ili) 4858c2ecf20Sopenharmony_ci return -ENOMEM; 4868c2ecf20Sopenharmony_ci 4878c2ecf20Sopenharmony_ci ili->spi = spi; 4888c2ecf20Sopenharmony_ci spi_set_drvdata(spi, ili); 4898c2ecf20Sopenharmony_ci 4908c2ecf20Sopenharmony_ci /* check if the device is connected */ 4918c2ecf20Sopenharmony_ci ret = ili922x_read(spi, REG_DRIVER_CODE_READ, ®); 4928c2ecf20Sopenharmony_ci if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) { 4938c2ecf20Sopenharmony_ci dev_err(&spi->dev, 4948c2ecf20Sopenharmony_ci "no LCD found: Chip ID 0x%x, ret %d\n", 4958c2ecf20Sopenharmony_ci reg, ret); 4968c2ecf20Sopenharmony_ci return -ENODEV; 4978c2ecf20Sopenharmony_ci } 4988c2ecf20Sopenharmony_ci 4998c2ecf20Sopenharmony_ci dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n", 5008c2ecf20Sopenharmony_ci reg, spi->max_speed_hz, spi->mode); 5018c2ecf20Sopenharmony_ci 5028c2ecf20Sopenharmony_ci ret = ili922x_read_status(spi, ®); 5038c2ecf20Sopenharmony_ci if (ret) { 5048c2ecf20Sopenharmony_ci dev_err(&spi->dev, "reading RS failed...\n"); 5058c2ecf20Sopenharmony_ci return ret; 5068c2ecf20Sopenharmony_ci } 5078c2ecf20Sopenharmony_ci 5088c2ecf20Sopenharmony_ci dev_dbg(&spi->dev, "status: 0x%x\n", reg); 5098c2ecf20Sopenharmony_ci 5108c2ecf20Sopenharmony_ci ili922x_display_init(spi); 5118c2ecf20Sopenharmony_ci 5128c2ecf20Sopenharmony_ci ili->power = FB_BLANK_POWERDOWN; 5138c2ecf20Sopenharmony_ci 5148c2ecf20Sopenharmony_ci lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili, 5158c2ecf20Sopenharmony_ci &ili922x_ops); 5168c2ecf20Sopenharmony_ci if (IS_ERR(lcd)) { 5178c2ecf20Sopenharmony_ci dev_err(&spi->dev, "cannot register LCD\n"); 5188c2ecf20Sopenharmony_ci return PTR_ERR(lcd); 5198c2ecf20Sopenharmony_ci } 5208c2ecf20Sopenharmony_ci 5218c2ecf20Sopenharmony_ci ili->ld = lcd; 5228c2ecf20Sopenharmony_ci spi_set_drvdata(spi, ili); 5238c2ecf20Sopenharmony_ci 5248c2ecf20Sopenharmony_ci ili922x_lcd_power(ili, FB_BLANK_UNBLANK); 5258c2ecf20Sopenharmony_ci 5268c2ecf20Sopenharmony_ci return 0; 5278c2ecf20Sopenharmony_ci} 5288c2ecf20Sopenharmony_ci 5298c2ecf20Sopenharmony_cistatic int ili922x_remove(struct spi_device *spi) 5308c2ecf20Sopenharmony_ci{ 5318c2ecf20Sopenharmony_ci ili922x_poweroff(spi); 5328c2ecf20Sopenharmony_ci return 0; 5338c2ecf20Sopenharmony_ci} 5348c2ecf20Sopenharmony_ci 5358c2ecf20Sopenharmony_cistatic struct spi_driver ili922x_driver = { 5368c2ecf20Sopenharmony_ci .driver = { 5378c2ecf20Sopenharmony_ci .name = "ili922x", 5388c2ecf20Sopenharmony_ci }, 5398c2ecf20Sopenharmony_ci .probe = ili922x_probe, 5408c2ecf20Sopenharmony_ci .remove = ili922x_remove, 5418c2ecf20Sopenharmony_ci}; 5428c2ecf20Sopenharmony_ci 5438c2ecf20Sopenharmony_cimodule_spi_driver(ili922x_driver); 5448c2ecf20Sopenharmony_ci 5458c2ecf20Sopenharmony_ciMODULE_AUTHOR("Stefano Babic <sbabic@denx.de>"); 5468c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("ILI9221/9222 LCD driver"); 5478c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 5488c2ecf20Sopenharmony_ciMODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)"); 5498c2ecf20Sopenharmony_ciMODULE_PARM_DESC(tx_invert, "invert bytes before sending"); 550