18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
28c2ecf20Sopenharmony_ci/*****************************************************************************
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci *	Copyright (C) 1997-2002 Inside Out Networks, Inc.
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci *	Feb-16-2001	DMI	Added I2C structure definitions
78c2ecf20Sopenharmony_ci *	May-29-2002	gkh	Ported to Linux
88c2ecf20Sopenharmony_ci *
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci ******************************************************************************/
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci#ifndef _IO_TI_H_
138c2ecf20Sopenharmony_ci#define _IO_TI_H_
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci/* Address Space */
168c2ecf20Sopenharmony_ci#define DTK_ADDR_SPACE_XDATA		0x03	/* Addr is placed in XDATA space */
178c2ecf20Sopenharmony_ci#define DTK_ADDR_SPACE_I2C_TYPE_II	0x82	/* Addr is placed in I2C area */
188c2ecf20Sopenharmony_ci#define DTK_ADDR_SPACE_I2C_TYPE_III	0x83	/* Addr is placed in I2C area */
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci/* UART Defines */
218c2ecf20Sopenharmony_ci#define UMPMEM_BASE_UART1		0xFFA0	/* UMP UART1 base address */
228c2ecf20Sopenharmony_ci#define UMPMEM_BASE_UART2		0xFFB0	/* UMP UART2 base address */
238c2ecf20Sopenharmony_ci#define UMPMEM_OFFS_UART_LSR		0x05	/* UMP UART LSR register offset */
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci/* Bits per character */
268c2ecf20Sopenharmony_ci#define UMP_UART_CHAR5BITS		0x00
278c2ecf20Sopenharmony_ci#define UMP_UART_CHAR6BITS		0x01
288c2ecf20Sopenharmony_ci#define UMP_UART_CHAR7BITS		0x02
298c2ecf20Sopenharmony_ci#define UMP_UART_CHAR8BITS		0x03
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ci/* Parity */
328c2ecf20Sopenharmony_ci#define UMP_UART_NOPARITY		0x00
338c2ecf20Sopenharmony_ci#define UMP_UART_ODDPARITY		0x01
348c2ecf20Sopenharmony_ci#define UMP_UART_EVENPARITY		0x02
358c2ecf20Sopenharmony_ci#define UMP_UART_MARKPARITY		0x03
368c2ecf20Sopenharmony_ci#define UMP_UART_SPACEPARITY		0x04
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci/* Stop bits */
398c2ecf20Sopenharmony_ci#define UMP_UART_STOPBIT1		0x00
408c2ecf20Sopenharmony_ci#define UMP_UART_STOPBIT15		0x01
418c2ecf20Sopenharmony_ci#define UMP_UART_STOPBIT2		0x02
428c2ecf20Sopenharmony_ci
438c2ecf20Sopenharmony_ci/* Line status register masks */
448c2ecf20Sopenharmony_ci#define UMP_UART_LSR_OV_MASK		0x01
458c2ecf20Sopenharmony_ci#define UMP_UART_LSR_PE_MASK		0x02
468c2ecf20Sopenharmony_ci#define UMP_UART_LSR_FE_MASK		0x04
478c2ecf20Sopenharmony_ci#define UMP_UART_LSR_BR_MASK		0x08
488c2ecf20Sopenharmony_ci#define UMP_UART_LSR_ER_MASK		0x0F
498c2ecf20Sopenharmony_ci#define UMP_UART_LSR_RX_MASK		0x10
508c2ecf20Sopenharmony_ci#define UMP_UART_LSR_TX_MASK		0x20
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci#define UMP_UART_LSR_DATA_MASK		(LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci/* Port Settings Constants) */
558c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RTS_FLOW		0x0001
568c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RTS_DISABLE		0x0002
578c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_PARITY		0x0008
588c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW	0x0010
598c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW	0x0020
608c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X		0x0040
618c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_XA		0x0080
628c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_IN_X		0x0100
638c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_DTR_FLOW		0x0800
648c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_DTR_DISABLE		0x1000
658c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT	0x2000
668c2ecf20Sopenharmony_ci#define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR	0x4000
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci#define UMP_DMA_MODE_CONTINOUS			0x01
698c2ecf20Sopenharmony_ci#define UMP_PIPE_TRANS_TIMEOUT_ENA		0x80
708c2ecf20Sopenharmony_ci#define UMP_PIPE_TRANSFER_MODE_MASK		0x03
718c2ecf20Sopenharmony_ci#define UMP_PIPE_TRANS_TIMEOUT_MASK		0x7C
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ci/* Purge port Direction Mask Bits */
748c2ecf20Sopenharmony_ci#define UMP_PORT_DIR_OUT			0x01
758c2ecf20Sopenharmony_ci#define UMP_PORT_DIR_IN				0x02
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci/* Address of Port 0 */
788c2ecf20Sopenharmony_ci#define UMPM_UART1_PORT				0x03
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ci/* Commands */
818c2ecf20Sopenharmony_ci#define	UMPC_SET_CONFIG			0x05
828c2ecf20Sopenharmony_ci#define	UMPC_OPEN_PORT			0x06
838c2ecf20Sopenharmony_ci#define	UMPC_CLOSE_PORT			0x07
848c2ecf20Sopenharmony_ci#define	UMPC_START_PORT			0x08
858c2ecf20Sopenharmony_ci#define	UMPC_STOP_PORT			0x09
868c2ecf20Sopenharmony_ci#define	UMPC_TEST_PORT			0x0A
878c2ecf20Sopenharmony_ci#define	UMPC_PURGE_PORT			0x0B
888c2ecf20Sopenharmony_ci
898c2ecf20Sopenharmony_ci/* Force the Firmware to complete the current Read */
908c2ecf20Sopenharmony_ci#define	UMPC_COMPLETE_READ		0x80
918c2ecf20Sopenharmony_ci/* Force UMP back into BOOT Mode */
928c2ecf20Sopenharmony_ci#define	UMPC_HARDWARE_RESET		0x81
938c2ecf20Sopenharmony_ci/*
948c2ecf20Sopenharmony_ci * Copy current download image to type 0xf2 record in 16k I2C
958c2ecf20Sopenharmony_ci * firmware will change 0xff record to type 2 record when complete
968c2ecf20Sopenharmony_ci */
978c2ecf20Sopenharmony_ci#define	UMPC_COPY_DNLD_TO_I2C		0x82
988c2ecf20Sopenharmony_ci
998c2ecf20Sopenharmony_ci/*
1008c2ecf20Sopenharmony_ci * Special function register commands
1018c2ecf20Sopenharmony_ci * wIndex is register address
1028c2ecf20Sopenharmony_ci * wValue is MSB/LSB mask/data
1038c2ecf20Sopenharmony_ci */
1048c2ecf20Sopenharmony_ci#define	UMPC_WRITE_SFR			0x83	/* Write SFR Register */
1058c2ecf20Sopenharmony_ci
1068c2ecf20Sopenharmony_ci/* wIndex is register address */
1078c2ecf20Sopenharmony_ci#define	UMPC_READ_SFR			0x84	/* Read SRF Register */
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_ci/* Set or Clear DTR (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
1108c2ecf20Sopenharmony_ci#define	UMPC_SET_CLR_DTR		0x85
1118c2ecf20Sopenharmony_ci
1128c2ecf20Sopenharmony_ci/* Set or Clear RTS (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
1138c2ecf20Sopenharmony_ci#define	UMPC_SET_CLR_RTS		0x86
1148c2ecf20Sopenharmony_ci
1158c2ecf20Sopenharmony_ci/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
1168c2ecf20Sopenharmony_ci#define	UMPC_SET_CLR_LOOPBACK		0x87
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_ci/* Set or Clear BREAK (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
1198c2ecf20Sopenharmony_ci#define	UMPC_SET_CLR_BREAK		0x88
1208c2ecf20Sopenharmony_ci
1218c2ecf20Sopenharmony_ci/* Read MSR wIndex ModuleID (port) */
1228c2ecf20Sopenharmony_ci#define	UMPC_READ_MSR			0x89
1238c2ecf20Sopenharmony_ci
1248c2ecf20Sopenharmony_ci/* Toolkit commands */
1258c2ecf20Sopenharmony_ci/* Read-write group */
1268c2ecf20Sopenharmony_ci#define	UMPC_MEMORY_READ		0x92
1278c2ecf20Sopenharmony_ci#define	UMPC_MEMORY_WRITE		0x93
1288c2ecf20Sopenharmony_ci
1298c2ecf20Sopenharmony_ci/*
1308c2ecf20Sopenharmony_ci *	UMP DMA Definitions
1318c2ecf20Sopenharmony_ci */
1328c2ecf20Sopenharmony_ci#define UMPD_OEDB1_ADDRESS		0xFF08
1338c2ecf20Sopenharmony_ci#define UMPD_OEDB2_ADDRESS		0xFF10
1348c2ecf20Sopenharmony_ci
1358c2ecf20Sopenharmony_cistruct out_endpoint_desc_block {
1368c2ecf20Sopenharmony_ci	__u8 Configuration;
1378c2ecf20Sopenharmony_ci	__u8 XBufAddr;
1388c2ecf20Sopenharmony_ci	__u8 XByteCount;
1398c2ecf20Sopenharmony_ci	__u8 Unused1;
1408c2ecf20Sopenharmony_ci	__u8 Unused2;
1418c2ecf20Sopenharmony_ci	__u8 YBufAddr;
1428c2ecf20Sopenharmony_ci	__u8 YByteCount;
1438c2ecf20Sopenharmony_ci	__u8 BufferSize;
1448c2ecf20Sopenharmony_ci} __attribute__((packed));
1458c2ecf20Sopenharmony_ci
1468c2ecf20Sopenharmony_ci
1478c2ecf20Sopenharmony_ci/*
1488c2ecf20Sopenharmony_ci * TYPE DEFINITIONS
1498c2ecf20Sopenharmony_ci * Structures for Firmware commands
1508c2ecf20Sopenharmony_ci */
1518c2ecf20Sopenharmony_ci/* UART settings */
1528c2ecf20Sopenharmony_cistruct ump_uart_config {
1538c2ecf20Sopenharmony_ci	__u16 wBaudRate;	/* Baud rate                        */
1548c2ecf20Sopenharmony_ci	__u16 wFlags;		/* Bitmap mask of flags             */
1558c2ecf20Sopenharmony_ci	__u8 bDataBits;		/* 5..8 - data bits per character   */
1568c2ecf20Sopenharmony_ci	__u8 bParity;		/* Parity settings                  */
1578c2ecf20Sopenharmony_ci	__u8 bStopBits;		/* Stop bits settings               */
1588c2ecf20Sopenharmony_ci	char cXon;		/* XON character                    */
1598c2ecf20Sopenharmony_ci	char cXoff;		/* XOFF character                   */
1608c2ecf20Sopenharmony_ci	__u8 bUartMode;		/* Will be updated when a user      */
1618c2ecf20Sopenharmony_ci				/* interface is defined             */
1628c2ecf20Sopenharmony_ci} __attribute__((packed));
1638c2ecf20Sopenharmony_ci
1648c2ecf20Sopenharmony_ci
1658c2ecf20Sopenharmony_ci/*
1668c2ecf20Sopenharmony_ci * TYPE DEFINITIONS
1678c2ecf20Sopenharmony_ci * Structures for USB interrupts
1688c2ecf20Sopenharmony_ci */
1698c2ecf20Sopenharmony_ci/* Interrupt packet structure */
1708c2ecf20Sopenharmony_cistruct ump_interrupt {
1718c2ecf20Sopenharmony_ci	__u8 bICode;			/* Interrupt code (interrupt num)   */
1728c2ecf20Sopenharmony_ci	__u8 bIInfo;			/* Interrupt information            */
1738c2ecf20Sopenharmony_ci}  __attribute__((packed));
1748c2ecf20Sopenharmony_ci
1758c2ecf20Sopenharmony_ci
1768c2ecf20Sopenharmony_ci#define TIUMP_GET_PORT_FROM_CODE(c)	(((c) >> 6) & 0x01)
1778c2ecf20Sopenharmony_ci#define TIUMP_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
1788c2ecf20Sopenharmony_ci#define TIUMP_INTERRUPT_CODE_LSR	0x03
1798c2ecf20Sopenharmony_ci#define TIUMP_INTERRUPT_CODE_MSR	0x04
1808c2ecf20Sopenharmony_ci
1818c2ecf20Sopenharmony_ci#endif
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