18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */ 28c2ecf20Sopenharmony_ci/************************************************************************ 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * IONSP.H Definitions for I/O Networks Serial Protocol 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * Copyright (C) 1997-1998 Inside Out Networks, Inc. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * These definitions are used by both kernel-mode driver and the 98c2ecf20Sopenharmony_ci * peripheral firmware and MUST be kept in sync. 108c2ecf20Sopenharmony_ci * 118c2ecf20Sopenharmony_ci ************************************************************************/ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/************************************************************************ 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciThe data to and from all ports on the peripheral is multiplexed 168c2ecf20Sopenharmony_cithrough a single endpoint pair (EP1 since it supports 64-byte 178c2ecf20Sopenharmony_ciMaxPacketSize). Therefore, the data, commands, and status for 188c2ecf20Sopenharmony_cieach port must be preceded by a short header identifying the 198c2ecf20Sopenharmony_cidestination port. The header also identifies the bytes that follow 208c2ecf20Sopenharmony_cias data or as command/status info. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciHeader format, first byte: 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci CLLLLPPP 258c2ecf20Sopenharmony_ci -------- 268c2ecf20Sopenharmony_ci | | |------ Port Number: 0-7 278c2ecf20Sopenharmony_ci | |--------- Length: MSB bits of length 288c2ecf20Sopenharmony_ci |----------- Data/Command: 0 = Data header 298c2ecf20Sopenharmony_ci 1 = Cmd / Status (Cmd if OUT, Status if IN) 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciThis gives 2 possible formats: 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci Data header: 0LLLLPPP LLLLLLLL 358c2ecf20Sopenharmony_ci ============ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci Where (LLLL,LLLLLLL) is 12-bit length of data that follows for 388c2ecf20Sopenharmony_ci port number (PPP). The length is 0-based (0-FFF means 0-4095 398c2ecf20Sopenharmony_ci bytes). The ~4K limit allows the host driver (which deals in 408c2ecf20Sopenharmony_ci transfer requests instead of individual packets) to write a 418c2ecf20Sopenharmony_ci large chunk of data in a single request. Note, however, that 428c2ecf20Sopenharmony_ci the length must always be <= the current TxCredits for a given 438c2ecf20Sopenharmony_ci port due to buffering limitations on the peripheral. 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci Cmd/Status header: 1ccccPPP [ CCCCCCCC, Params ]... 478c2ecf20Sopenharmony_ci ================== 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci Where (cccc) or (cccc,CCCCCCCC) is the cmd or status identifier. 508c2ecf20Sopenharmony_ci Frequently-used values are encoded as (cccc), longer ones using 518c2ecf20Sopenharmony_ci (cccc,CCCCCCCC). Subsequent bytes are optional parameters and are 528c2ecf20Sopenharmony_ci specific to the cmd or status code. This may include a length 538c2ecf20Sopenharmony_ci for command and status codes that need variable-length parameters. 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ciIn addition, we use another interrupt pipe (endpoint) which the host polls 578c2ecf20Sopenharmony_ciperiodically for flow control information. The peripheral, when there has 588c2ecf20Sopenharmony_cibeen a change, sends the following 10-byte packet: 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci RRRRRRRRRRRRRRRR 618c2ecf20Sopenharmony_ci T0T0T0T0T0T0T0T0 628c2ecf20Sopenharmony_ci T1T1T1T1T1T1T1T1 638c2ecf20Sopenharmony_ci T2T2T2T2T2T2T2T2 648c2ecf20Sopenharmony_ci T3T3T3T3T3T3T3T3 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ciThe first field is the 16-bit RxBytesAvail field, which indicates the 678c2ecf20Sopenharmony_cinumber of bytes which may be read by the host from EP1. This is necessary: 688c2ecf20Sopenharmony_ci(a) because OSR2.1 has a bug which causes data loss if the peripheral returns 698c2ecf20Sopenharmony_cifewer bytes than the host expects to read, and (b) because, on Microsoft 708c2ecf20Sopenharmony_ciplatforms at least, an outstanding read posted on EP1 consumes about 35% of 718c2ecf20Sopenharmony_cithe CPU just polling the device for data. 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ciThe next 4 fields are the 16-bit TxCredits for each port, which indicate how 748c2ecf20Sopenharmony_cimany bytes the host is allowed to send on EP1 for transmit to a given port. 758c2ecf20Sopenharmony_ciAfter an OPEN_PORT command, the Edgeport sends the initial TxCredits for that 768c2ecf20Sopenharmony_ciport. 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ciAll 16-bit fields are sent in little-endian (Intel) format. 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_ci************************************************************************/ 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci// 838c2ecf20Sopenharmony_ci// Define format of InterruptStatus packet returned from the 848c2ecf20Sopenharmony_ci// Interrupt pipe 858c2ecf20Sopenharmony_ci// 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_cistruct int_status_pkt { 888c2ecf20Sopenharmony_ci __u16 RxBytesAvail; // Additional bytes available to 898c2ecf20Sopenharmony_ci // be read from Bulk IN pipe 908c2ecf20Sopenharmony_ci __u16 TxCredits[MAX_RS232_PORTS]; // Additional space available in 918c2ecf20Sopenharmony_ci // given port's TxBuffer 928c2ecf20Sopenharmony_ci}; 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci#define GET_INT_STATUS_SIZE(NumPorts) (sizeof(__u16) + (sizeof(__u16) * (NumPorts))) 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ci// 1008c2ecf20Sopenharmony_ci// Define cmd/status header values and macros to extract them. 1018c2ecf20Sopenharmony_ci// 1028c2ecf20Sopenharmony_ci// Data: 0LLLLPPP LLLLLLLL 1038c2ecf20Sopenharmony_ci// Cmd/Stat: 1ccccPPP CCCCCCCC 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci#define IOSP_DATA_HDR_SIZE 2 1068c2ecf20Sopenharmony_ci#define IOSP_CMD_HDR_SIZE 2 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci#define IOSP_MAX_DATA_LENGTH 0x0FFF // 12 bits -> 4K 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_ci#define IOSP_PORT_MASK 0x07 // Mask to isolate port number 1118c2ecf20Sopenharmony_ci#define IOSP_CMD_STAT_BIT 0x80 // If set, this is command/status header 1128c2ecf20Sopenharmony_ci 1138c2ecf20Sopenharmony_ci#define IS_CMD_STAT_HDR(Byte1) ((Byte1) & IOSP_CMD_STAT_BIT) 1148c2ecf20Sopenharmony_ci#define IS_DATA_HDR(Byte1) (!IS_CMD_STAT_HDR(Byte1)) 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_ci#define IOSP_GET_HDR_PORT(Byte1) ((__u8) ((Byte1) & IOSP_PORT_MASK)) 1178c2ecf20Sopenharmony_ci#define IOSP_GET_HDR_DATA_LEN(Byte1, Byte2) ((__u16) (((__u16)((Byte1) & 0x78)) << 5) | (Byte2)) 1188c2ecf20Sopenharmony_ci#define IOSP_GET_STATUS_CODE(Byte1) ((__u8) (((Byte1) & 0x78) >> 3)) 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci 1218c2ecf20Sopenharmony_ci// 1228c2ecf20Sopenharmony_ci// These macros build the 1st and 2nd bytes for a data header 1238c2ecf20Sopenharmony_ci// 1248c2ecf20Sopenharmony_ci#define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78)))) 1258c2ecf20Sopenharmony_ci#define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) 1268c2ecf20Sopenharmony_ci 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci// 1298c2ecf20Sopenharmony_ci// These macros build the 1st and 2nd bytes for a command header 1308c2ecf20Sopenharmony_ci// 1318c2ecf20Sopenharmony_ci#define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3)))) 1328c2ecf20Sopenharmony_ci 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci//-------------------------------------------------------------- 1358c2ecf20Sopenharmony_ci// 1368c2ecf20Sopenharmony_ci// Define values for commands and command parameters 1378c2ecf20Sopenharmony_ci// (sent from Host to Edgeport) 1388c2ecf20Sopenharmony_ci// 1398c2ecf20Sopenharmony_ci// 1ccccPPP P1P1P1P1 [ P2P2P2P2P2 ]... 1408c2ecf20Sopenharmony_ci// 1418c2ecf20Sopenharmony_ci// cccc: 00-07 2-byte commands. Write UART register 0-7 with 1428c2ecf20Sopenharmony_ci// value in P1. See 16650.H for definitions of 1438c2ecf20Sopenharmony_ci// UART register numbers and contents. 1448c2ecf20Sopenharmony_ci// 1458c2ecf20Sopenharmony_ci// 08-0B 3-byte commands: ==== P1 ==== ==== P2 ==== 1468c2ecf20Sopenharmony_ci// 08 available for expansion 1478c2ecf20Sopenharmony_ci// 09 1-param commands Command Code Param 1488c2ecf20Sopenharmony_ci// 0A available for expansion 1498c2ecf20Sopenharmony_ci// 0B available for expansion 1508c2ecf20Sopenharmony_ci// 1518c2ecf20Sopenharmony_ci// 0C-0D 4-byte commands. P1 = extended cmd and P2,P3 = params 1528c2ecf20Sopenharmony_ci// Currently unimplemented. 1538c2ecf20Sopenharmony_ci// 1548c2ecf20Sopenharmony_ci// 0E-0F N-byte commands: P1 = num bytes after P1 (ie, TotalLen - 2) 1558c2ecf20Sopenharmony_ci// P2 = extended cmd, P3..Pn = parameters. 1568c2ecf20Sopenharmony_ci// Currently unimplemented. 1578c2ecf20Sopenharmony_ci// 1588c2ecf20Sopenharmony_ci 1598c2ecf20Sopenharmony_ci#define IOSP_WRITE_UART_REG(n) ((n) & 0x07) // UartReg[ n ] := P1 1608c2ecf20Sopenharmony_ci 1618c2ecf20Sopenharmony_ci// Register numbers and contents 1628c2ecf20Sopenharmony_ci// defined in 16554.H. 1638c2ecf20Sopenharmony_ci 1648c2ecf20Sopenharmony_ci// 0x08 // Available for expansion. 1658c2ecf20Sopenharmony_ci#define IOSP_EXT_CMD 0x09 // P1 = Command code (defined below) 1668c2ecf20Sopenharmony_ci 1678c2ecf20Sopenharmony_ci// P2 = Parameter 1688c2ecf20Sopenharmony_ci 1698c2ecf20Sopenharmony_ci// 1708c2ecf20Sopenharmony_ci// Extended Command values, used with IOSP_EXT_CMD, may 1718c2ecf20Sopenharmony_ci// or may not use parameter P2. 1728c2ecf20Sopenharmony_ci// 1738c2ecf20Sopenharmony_ci 1748c2ecf20Sopenharmony_ci#define IOSP_CMD_OPEN_PORT 0x00 // Enable ints, init UART. (NO PARAM) 1758c2ecf20Sopenharmony_ci#define IOSP_CMD_CLOSE_PORT 0x01 // Disable ints, flush buffers. (NO PARAM) 1768c2ecf20Sopenharmony_ci#define IOSP_CMD_CHASE_PORT 0x02 // Wait for Edgeport TX buffers to empty. (NO PARAM) 1778c2ecf20Sopenharmony_ci#define IOSP_CMD_SET_RX_FLOW 0x03 // Set Rx Flow Control in Edgeport 1788c2ecf20Sopenharmony_ci#define IOSP_CMD_SET_TX_FLOW 0x04 // Set Tx Flow Control in Edgeport 1798c2ecf20Sopenharmony_ci#define IOSP_CMD_SET_XON_CHAR 0x05 // Set XON Character in Edgeport 1808c2ecf20Sopenharmony_ci#define IOSP_CMD_SET_XOFF_CHAR 0x06 // Set XOFF Character in Edgeport 1818c2ecf20Sopenharmony_ci#define IOSP_CMD_RX_CHECK_REQ 0x07 // Request Edgeport to insert a Checkpoint into 1828c2ecf20Sopenharmony_ci 1838c2ecf20Sopenharmony_ci// the receive data stream (Parameter = 1 byte sequence number) 1848c2ecf20Sopenharmony_ci 1858c2ecf20Sopenharmony_ci#define IOSP_CMD_SET_BREAK 0x08 // Turn on the BREAK (LCR bit 6) 1868c2ecf20Sopenharmony_ci#define IOSP_CMD_CLEAR_BREAK 0x09 // Turn off the BREAK (LCR bit 6) 1878c2ecf20Sopenharmony_ci 1888c2ecf20Sopenharmony_ci 1898c2ecf20Sopenharmony_ci// 1908c2ecf20Sopenharmony_ci// Define macros to simplify building of IOSP cmds 1918c2ecf20Sopenharmony_ci// 1928c2ecf20Sopenharmony_ci 1938c2ecf20Sopenharmony_ci#define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ 1948c2ecf20Sopenharmony_cido { \ 1958c2ecf20Sopenharmony_ci (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \ 1968c2ecf20Sopenharmony_ci IOSP_WRITE_UART_REG(Reg)); \ 1978c2ecf20Sopenharmony_ci (*(ppBuf))[1] = (Val); \ 1988c2ecf20Sopenharmony_ci \ 1998c2ecf20Sopenharmony_ci *ppBuf += 2; \ 2008c2ecf20Sopenharmony_ci *pLen += 2; \ 2018c2ecf20Sopenharmony_ci} while (0) 2028c2ecf20Sopenharmony_ci 2038c2ecf20Sopenharmony_ci#define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ 2048c2ecf20Sopenharmony_cido { \ 2058c2ecf20Sopenharmony_ci (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \ 2068c2ecf20Sopenharmony_ci (*(ppBuf))[1] = (ExtCmd); \ 2078c2ecf20Sopenharmony_ci (*(ppBuf))[2] = (Param); \ 2088c2ecf20Sopenharmony_ci \ 2098c2ecf20Sopenharmony_ci *ppBuf += 3; \ 2108c2ecf20Sopenharmony_ci *pLen += 3; \ 2118c2ecf20Sopenharmony_ci} while (0) 2128c2ecf20Sopenharmony_ci 2138c2ecf20Sopenharmony_ci 2148c2ecf20Sopenharmony_ci 2158c2ecf20Sopenharmony_ci//-------------------------------------------------------------- 2168c2ecf20Sopenharmony_ci// 2178c2ecf20Sopenharmony_ci// Define format of flow control commands 2188c2ecf20Sopenharmony_ci// (sent from Host to Edgeport) 2198c2ecf20Sopenharmony_ci// 2208c2ecf20Sopenharmony_ci// 11001PPP FlowCmd FlowTypes 2218c2ecf20Sopenharmony_ci// 2228c2ecf20Sopenharmony_ci// Note that the 'FlowTypes' parameter is a bit mask; that is, 2238c2ecf20Sopenharmony_ci// more than one flow control type can be active at the same time. 2248c2ecf20Sopenharmony_ci// FlowTypes = 0 means 'no flow control'. 2258c2ecf20Sopenharmony_ci// 2268c2ecf20Sopenharmony_ci 2278c2ecf20Sopenharmony_ci// 2288c2ecf20Sopenharmony_ci// IOSP_CMD_SET_RX_FLOW 2298c2ecf20Sopenharmony_ci// 2308c2ecf20Sopenharmony_ci// Tells Edgeport how it can stop incoming UART data 2318c2ecf20Sopenharmony_ci// 2328c2ecf20Sopenharmony_ci// Example for Port 0 2338c2ecf20Sopenharmony_ci// P0 = 11001000 2348c2ecf20Sopenharmony_ci// P1 = IOSP_CMD_SET_RX_FLOW 2358c2ecf20Sopenharmony_ci// P2 = Bit mask as follows: 2368c2ecf20Sopenharmony_ci 2378c2ecf20Sopenharmony_ci#define IOSP_RX_FLOW_RTS 0x01 // Edgeport drops RTS to stop incoming data 2388c2ecf20Sopenharmony_ci#define IOSP_RX_FLOW_DTR 0x02 // Edgeport drops DTR to stop incoming data 2398c2ecf20Sopenharmony_ci#define IOSP_RX_FLOW_DSR_SENSITIVITY 0x04 // Ignores Rx data unless DSR high 2408c2ecf20Sopenharmony_ci 2418c2ecf20Sopenharmony_ci// Not currently implemented by firmware. 2428c2ecf20Sopenharmony_ci#define IOSP_RX_FLOW_XON_XOFF 0x08 // Edgeport sends XOFF char to stop incoming data. 2438c2ecf20Sopenharmony_ci 2448c2ecf20Sopenharmony_ci// Host must have previously programmed the 2458c2ecf20Sopenharmony_ci// XON/XOFF values with SET_XON/SET_XOFF 2468c2ecf20Sopenharmony_ci// before enabling this bit. 2478c2ecf20Sopenharmony_ci 2488c2ecf20Sopenharmony_ci// 2498c2ecf20Sopenharmony_ci// IOSP_CMD_SET_TX_FLOW 2508c2ecf20Sopenharmony_ci// 2518c2ecf20Sopenharmony_ci// Tells Edgeport what signal(s) will stop it from transmitting UART data 2528c2ecf20Sopenharmony_ci// 2538c2ecf20Sopenharmony_ci// Example for Port 0 2548c2ecf20Sopenharmony_ci// P0 = 11001000 2558c2ecf20Sopenharmony_ci// P1 = IOSP_CMD_SET_TX_FLOW 2568c2ecf20Sopenharmony_ci// P2 = Bit mask as follows: 2578c2ecf20Sopenharmony_ci 2588c2ecf20Sopenharmony_ci#define IOSP_TX_FLOW_CTS 0x01 // Edgeport stops Tx if CTS low 2598c2ecf20Sopenharmony_ci#define IOSP_TX_FLOW_DSR 0x02 // Edgeport stops Tx if DSR low 2608c2ecf20Sopenharmony_ci#define IOSP_TX_FLOW_DCD 0x04 // Edgeport stops Tx if DCD low 2618c2ecf20Sopenharmony_ci#define IOSP_TX_FLOW_XON_XOFF 0x08 // Edgeport stops Tx upon receiving XOFF char. 2628c2ecf20Sopenharmony_ci 2638c2ecf20Sopenharmony_ci// Host must have previously programmed the 2648c2ecf20Sopenharmony_ci// XON/XOFF values with SET_XON/SET_XOFF 2658c2ecf20Sopenharmony_ci// before enabling this bit. 2668c2ecf20Sopenharmony_ci#define IOSP_TX_FLOW_XOFF_CONTINUE 0x10 // If not set, Edgeport stops Tx when 2678c2ecf20Sopenharmony_ci 2688c2ecf20Sopenharmony_ci// sending XOFF in order to fix broken 2698c2ecf20Sopenharmony_ci// systems that interpret the next 2708c2ecf20Sopenharmony_ci// received char as XON. 2718c2ecf20Sopenharmony_ci// If set, Edgeport continues Tx 2728c2ecf20Sopenharmony_ci// normally after transmitting XOFF. 2738c2ecf20Sopenharmony_ci// Not currently implemented by firmware. 2748c2ecf20Sopenharmony_ci#define IOSP_TX_TOGGLE_RTS 0x20 // Edgeport drives RTS as a true half-duplex 2758c2ecf20Sopenharmony_ci 2768c2ecf20Sopenharmony_ci// Request-to-Send signal: it is raised before 2778c2ecf20Sopenharmony_ci// beginning transmission and lowered after 2788c2ecf20Sopenharmony_ci// the last Tx char leaves the UART. 2798c2ecf20Sopenharmony_ci// Not currently implemented by firmware. 2808c2ecf20Sopenharmony_ci 2818c2ecf20Sopenharmony_ci// 2828c2ecf20Sopenharmony_ci// IOSP_CMD_SET_XON_CHAR 2838c2ecf20Sopenharmony_ci// 2848c2ecf20Sopenharmony_ci// Sets the character which Edgeport transmits/interprets as XON. 2858c2ecf20Sopenharmony_ci// Note: This command MUST be sent before sending a SET_RX_FLOW or 2868c2ecf20Sopenharmony_ci// SET_TX_FLOW with the XON_XOFF bit set. 2878c2ecf20Sopenharmony_ci// 2888c2ecf20Sopenharmony_ci// Example for Port 0 2898c2ecf20Sopenharmony_ci// P0 = 11001000 2908c2ecf20Sopenharmony_ci// P1 = IOSP_CMD_SET_XON_CHAR 2918c2ecf20Sopenharmony_ci// P2 = 0x11 2928c2ecf20Sopenharmony_ci 2938c2ecf20Sopenharmony_ci 2948c2ecf20Sopenharmony_ci// 2958c2ecf20Sopenharmony_ci// IOSP_CMD_SET_XOFF_CHAR 2968c2ecf20Sopenharmony_ci// 2978c2ecf20Sopenharmony_ci// Sets the character which Edgeport transmits/interprets as XOFF. 2988c2ecf20Sopenharmony_ci// Note: This command must be sent before sending a SET_RX_FLOW or 2998c2ecf20Sopenharmony_ci// SET_TX_FLOW with the XON_XOFF bit set. 3008c2ecf20Sopenharmony_ci// 3018c2ecf20Sopenharmony_ci// Example for Port 0 3028c2ecf20Sopenharmony_ci// P0 = 11001000 3038c2ecf20Sopenharmony_ci// P1 = IOSP_CMD_SET_XOFF_CHAR 3048c2ecf20Sopenharmony_ci// P2 = 0x13 3058c2ecf20Sopenharmony_ci 3068c2ecf20Sopenharmony_ci 3078c2ecf20Sopenharmony_ci// 3088c2ecf20Sopenharmony_ci// IOSP_CMD_RX_CHECK_REQ 3098c2ecf20Sopenharmony_ci// 3108c2ecf20Sopenharmony_ci// This command is used to assist in the implementation of the 3118c2ecf20Sopenharmony_ci// IOCTL_SERIAL_PURGE Windows IOCTL. 3128c2ecf20Sopenharmony_ci// This IOSP command tries to place a marker at the end of the RX 3138c2ecf20Sopenharmony_ci// queue in the Edgeport. If the Edgeport RX queue is full then 3148c2ecf20Sopenharmony_ci// the Check will be discarded. 3158c2ecf20Sopenharmony_ci// It is up to the device driver to timeout waiting for the 3168c2ecf20Sopenharmony_ci// RX_CHECK_RSP. If a RX_CHECK_RSP is received, the driver is 3178c2ecf20Sopenharmony_ci// sure that all data has been received from the edgeport and 3188c2ecf20Sopenharmony_ci// may now purge any internal RX buffers. 3198c2ecf20Sopenharmony_ci// Note tat the sequence numbers may be used to detect lost 3208c2ecf20Sopenharmony_ci// CHECK_REQs. 3218c2ecf20Sopenharmony_ci 3228c2ecf20Sopenharmony_ci// Example for Port 0 3238c2ecf20Sopenharmony_ci// P0 = 11001000 3248c2ecf20Sopenharmony_ci// P1 = IOSP_CMD_RX_CHECK_REQ 3258c2ecf20Sopenharmony_ci// P2 = Sequence number 3268c2ecf20Sopenharmony_ci 3278c2ecf20Sopenharmony_ci 3288c2ecf20Sopenharmony_ci// Response will be: 3298c2ecf20Sopenharmony_ci// P1 = IOSP_EXT_RX_CHECK_RSP 3308c2ecf20Sopenharmony_ci// P2 = Request Sequence number 3318c2ecf20Sopenharmony_ci 3328c2ecf20Sopenharmony_ci 3338c2ecf20Sopenharmony_ci 3348c2ecf20Sopenharmony_ci//-------------------------------------------------------------- 3358c2ecf20Sopenharmony_ci// 3368c2ecf20Sopenharmony_ci// Define values for status and status parameters 3378c2ecf20Sopenharmony_ci// (received by Host from Edgeport) 3388c2ecf20Sopenharmony_ci// 3398c2ecf20Sopenharmony_ci// 1ssssPPP P1P1P1P1 [ P2P2P2P2P2 ]... 3408c2ecf20Sopenharmony_ci// 3418c2ecf20Sopenharmony_ci// ssss: 00-07 2-byte status. ssss identifies which UART register 3428c2ecf20Sopenharmony_ci// has changed value, and the new value is in P1. 3438c2ecf20Sopenharmony_ci// Note that the ssss values do not correspond to the 3448c2ecf20Sopenharmony_ci// 16554 register numbers given in 16554.H. Instead, 3458c2ecf20Sopenharmony_ci// see below for definitions of the ssss numbers 3468c2ecf20Sopenharmony_ci// used in this status message. 3478c2ecf20Sopenharmony_ci// 3488c2ecf20Sopenharmony_ci// 08-0B 3-byte status: ==== P1 ==== ==== P2 ==== 3498c2ecf20Sopenharmony_ci// 08 LSR_DATA: New LSR Errored byte 3508c2ecf20Sopenharmony_ci// 09 1-param responses Response Code Param 3518c2ecf20Sopenharmony_ci// 0A OPEN_RSP: InitialMsr TxBufferSize 3528c2ecf20Sopenharmony_ci// 0B available for expansion 3538c2ecf20Sopenharmony_ci// 3548c2ecf20Sopenharmony_ci// 0C-0D 4-byte status. P1 = extended status code and P2,P3 = params 3558c2ecf20Sopenharmony_ci// Not currently implemented. 3568c2ecf20Sopenharmony_ci// 3578c2ecf20Sopenharmony_ci// 0E-0F N-byte status: P1 = num bytes after P1 (ie, TotalLen - 2) 3588c2ecf20Sopenharmony_ci// P2 = extended status, P3..Pn = parameters. 3598c2ecf20Sopenharmony_ci// Not currently implemented. 3608c2ecf20Sopenharmony_ci// 3618c2ecf20Sopenharmony_ci 3628c2ecf20Sopenharmony_ci/**************************************************** 3638c2ecf20Sopenharmony_ci * SSSS values for 2-byte status messages (0-8) 3648c2ecf20Sopenharmony_ci ****************************************************/ 3658c2ecf20Sopenharmony_ci 3668c2ecf20Sopenharmony_ci#define IOSP_STATUS_LSR 0x00 // P1 is new value of LSR register. 3678c2ecf20Sopenharmony_ci 3688c2ecf20Sopenharmony_ci// Bits defined in 16554.H. Edgeport 3698c2ecf20Sopenharmony_ci// returns this in order to report 3708c2ecf20Sopenharmony_ci// line status errors (overrun, 3718c2ecf20Sopenharmony_ci// parity, framing, break). This form 3728c2ecf20Sopenharmony_ci// is used when a errored receive data 3738c2ecf20Sopenharmony_ci// character was NOT present in the 3748c2ecf20Sopenharmony_ci// UART when the LSR error occurred 3758c2ecf20Sopenharmony_ci// (ie, when LSR bit 0 = 0). 3768c2ecf20Sopenharmony_ci 3778c2ecf20Sopenharmony_ci#define IOSP_STATUS_MSR 0x01 // P1 is new value of MSR register. 3788c2ecf20Sopenharmony_ci 3798c2ecf20Sopenharmony_ci// Bits defined in 16554.H. Edgeport 3808c2ecf20Sopenharmony_ci// returns this in order to report 3818c2ecf20Sopenharmony_ci// changes in modem status lines 3828c2ecf20Sopenharmony_ci// (CTS, DSR, RI, CD) 3838c2ecf20Sopenharmony_ci// 3848c2ecf20Sopenharmony_ci 3858c2ecf20Sopenharmony_ci// 0x02 // Available for future expansion 3868c2ecf20Sopenharmony_ci// 0x03 // 3878c2ecf20Sopenharmony_ci// 0x04 // 3888c2ecf20Sopenharmony_ci// 0x05 // 3898c2ecf20Sopenharmony_ci// 0x06 // 3908c2ecf20Sopenharmony_ci// 0x07 // 3918c2ecf20Sopenharmony_ci 3928c2ecf20Sopenharmony_ci 3938c2ecf20Sopenharmony_ci/**************************************************** 3948c2ecf20Sopenharmony_ci * SSSS values for 3-byte status messages (8-A) 3958c2ecf20Sopenharmony_ci ****************************************************/ 3968c2ecf20Sopenharmony_ci 3978c2ecf20Sopenharmony_ci#define IOSP_STATUS_LSR_DATA 0x08 // P1 is new value of LSR register (same as STATUS_LSR) 3988c2ecf20Sopenharmony_ci 3998c2ecf20Sopenharmony_ci// P2 is errored character read from 4008c2ecf20Sopenharmony_ci// RxFIFO after LSR reported an error. 4018c2ecf20Sopenharmony_ci 4028c2ecf20Sopenharmony_ci#define IOSP_EXT_STATUS 0x09 // P1 is status/response code, param in P2. 4038c2ecf20Sopenharmony_ci 4048c2ecf20Sopenharmony_ci 4058c2ecf20Sopenharmony_ci// Response Codes (P1 values) for 3-byte status messages 4068c2ecf20Sopenharmony_ci 4078c2ecf20Sopenharmony_ci#define IOSP_EXT_STATUS_CHASE_RSP 0 // Reply to CHASE_PORT cmd. P2 is outcome: 4088c2ecf20Sopenharmony_ci#define IOSP_EXT_STATUS_CHASE_PASS 0 // P2 = 0: All Tx data drained successfully 4098c2ecf20Sopenharmony_ci#define IOSP_EXT_STATUS_CHASE_FAIL 1 // P2 = 1: Timed out (stuck due to flow 4108c2ecf20Sopenharmony_ci 4118c2ecf20Sopenharmony_ci// control from remote device). 4128c2ecf20Sopenharmony_ci 4138c2ecf20Sopenharmony_ci#define IOSP_EXT_STATUS_RX_CHECK_RSP 1 // Reply to RX_CHECK cmd. P2 is sequence number 4148c2ecf20Sopenharmony_ci 4158c2ecf20Sopenharmony_ci 4168c2ecf20Sopenharmony_ci#define IOSP_STATUS_OPEN_RSP 0x0A // Reply to OPEN_PORT cmd. 4178c2ecf20Sopenharmony_ci 4188c2ecf20Sopenharmony_ci// P1 is Initial MSR value 4198c2ecf20Sopenharmony_ci// P2 is encoded TxBuffer Size: 4208c2ecf20Sopenharmony_ci// TxBufferSize = (P2 + 1) * 64 4218c2ecf20Sopenharmony_ci 4228c2ecf20Sopenharmony_ci// 0x0B // Available for future expansion 4238c2ecf20Sopenharmony_ci 4248c2ecf20Sopenharmony_ci#define GET_TX_BUFFER_SIZE(P2) (((P2) + 1) * 64) 4258c2ecf20Sopenharmony_ci 4268c2ecf20Sopenharmony_ci 4278c2ecf20Sopenharmony_ci 4288c2ecf20Sopenharmony_ci 4298c2ecf20Sopenharmony_ci/**************************************************** 4308c2ecf20Sopenharmony_ci * SSSS values for 4-byte status messages 4318c2ecf20Sopenharmony_ci ****************************************************/ 4328c2ecf20Sopenharmony_ci 4338c2ecf20Sopenharmony_ci#define IOSP_EXT4_STATUS 0x0C // Extended status code in P1, 4348c2ecf20Sopenharmony_ci 4358c2ecf20Sopenharmony_ci// Params in P2, P3 4368c2ecf20Sopenharmony_ci// Currently unimplemented. 4378c2ecf20Sopenharmony_ci 4388c2ecf20Sopenharmony_ci// 0x0D // Currently unused, available. 4398c2ecf20Sopenharmony_ci 4408c2ecf20Sopenharmony_ci 4418c2ecf20Sopenharmony_ci 4428c2ecf20Sopenharmony_ci// 4438c2ecf20Sopenharmony_ci// Macros to parse status messages 4448c2ecf20Sopenharmony_ci// 4458c2ecf20Sopenharmony_ci 4468c2ecf20Sopenharmony_ci#define IOSP_GET_STATUS_LEN(code) ((code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4)) 4478c2ecf20Sopenharmony_ci 4488c2ecf20Sopenharmony_ci#define IOSP_STATUS_IS_2BYTE(code) ((code) < 0x08) 4498c2ecf20Sopenharmony_ci#define IOSP_STATUS_IS_3BYTE(code) (((code) >= 0x08) && ((code) <= 0x0B)) 4508c2ecf20Sopenharmony_ci#define IOSP_STATUS_IS_4BYTE(code) (((code) >= 0x0C) && ((code) <= 0x0D)) 4518c2ecf20Sopenharmony_ci 452