1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2012-2014 Freescale Semiconductor, Inc. 4 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 5 * on behalf of DENX Software Engineering GmbH 6 */ 7 8#include <linux/module.h> 9#include <linux/kernel.h> 10#include <linux/platform_device.h> 11#include <linux/clk.h> 12#include <linux/usb/otg.h> 13#include <linux/stmp_device.h> 14#include <linux/delay.h> 15#include <linux/err.h> 16#include <linux/io.h> 17#include <linux/of_device.h> 18#include <linux/regmap.h> 19#include <linux/mfd/syscon.h> 20#include <linux/iopoll.h> 21 22#define DRIVER_NAME "mxs_phy" 23 24/* Register Macro */ 25#define HW_USBPHY_PWD 0x00 26#define HW_USBPHY_TX 0x10 27#define HW_USBPHY_CTRL 0x30 28#define HW_USBPHY_CTRL_SET 0x34 29#define HW_USBPHY_CTRL_CLR 0x38 30 31#define HW_USBPHY_DEBUG_SET 0x54 32#define HW_USBPHY_DEBUG_CLR 0x58 33 34#define HW_USBPHY_IP 0x90 35#define HW_USBPHY_IP_SET 0x94 36#define HW_USBPHY_IP_CLR 0x98 37 38#define GM_USBPHY_TX_TXCAL45DP(x) (((x) & 0xf) << 16) 39#define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) 40#define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) 41 42/* imx7ulp */ 43#define HW_USBPHY_PLL_SIC 0xa0 44#define HW_USBPHY_PLL_SIC_SET 0xa4 45#define HW_USBPHY_PLL_SIC_CLR 0xa8 46 47#define BM_USBPHY_CTRL_SFTRST BIT(31) 48#define BM_USBPHY_CTRL_CLKGATE BIT(30) 49#define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) 50#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 51#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 52#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) 53#define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) 54#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) 55#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 56#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 57#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 58#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 59#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 60#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 61 62#define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) 63 64#define BM_USBPHY_DEBUG_CLKGATE BIT(30) 65/* imx7ulp */ 66#define BM_USBPHY_PLL_LOCK BIT(31) 67#define BM_USBPHY_PLL_REG_ENABLE BIT(21) 68#define BM_USBPHY_PLL_BYPASS BIT(16) 69#define BM_USBPHY_PLL_POWER BIT(12) 70#define BM_USBPHY_PLL_EN_USB_CLKS BIT(6) 71 72/* Anatop Registers */ 73#define ANADIG_ANA_MISC0 0x150 74#define ANADIG_ANA_MISC0_SET 0x154 75#define ANADIG_ANA_MISC0_CLR 0x158 76 77#define ANADIG_USB1_CHRG_DETECT_SET 0x1b4 78#define ANADIG_USB1_CHRG_DETECT_CLR 0x1b8 79#define ANADIG_USB2_CHRG_DETECT_SET 0x214 80#define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20) 81#define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19) 82#define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18) 83 84#define ANADIG_USB1_VBUS_DET_STAT 0x1c0 85#define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 86 87#define ANADIG_USB1_CHRG_DET_STAT 0x1d0 88#define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2) 89#define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1) 90#define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0) 91 92#define ANADIG_USB2_VBUS_DET_STAT 0x220 93 94#define ANADIG_USB1_LOOPBACK_SET 0x1e4 95#define ANADIG_USB1_LOOPBACK_CLR 0x1e8 96#define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0) 97 98#define ANADIG_USB2_LOOPBACK_SET 0x244 99#define ANADIG_USB2_LOOPBACK_CLR 0x248 100 101#define ANADIG_USB1_MISC 0x1f0 102#define ANADIG_USB2_MISC 0x250 103 104#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) 105#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) 106 107#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 108#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) 109 110#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) 111#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) 112#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) 113#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) 114 115#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29) 116#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28) 117#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29) 118#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28) 119 120#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 121 122/* Do disconnection between PHY and controller without vbus */ 123#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 124 125/* 126 * The PHY will be in messy if there is a wakeup after putting 127 * bus to suspend (set portsc.suspendM) but before setting PHY to low 128 * power mode (set portsc.phcd). 129 */ 130#define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 131 132/* 133 * The SOF sends too fast after resuming, it will cause disconnection 134 * between host and high speed device. 135 */ 136#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 137 138/* 139 * IC has bug fixes logic, they include 140 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST 141 * which are described at above flags, the RTL will handle it 142 * according to different versions. 143 */ 144#define MXS_PHY_NEED_IP_FIX BIT(3) 145 146/* Minimum and maximum values for device tree entries */ 147#define MXS_PHY_TX_CAL45_MIN 30 148#define MXS_PHY_TX_CAL45_MAX 55 149#define MXS_PHY_TX_D_CAL_MIN 79 150#define MXS_PHY_TX_D_CAL_MAX 119 151 152struct mxs_phy_data { 153 unsigned int flags; 154}; 155 156static const struct mxs_phy_data imx23_phy_data = { 157 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 158}; 159 160static const struct mxs_phy_data imx6q_phy_data = { 161 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 162 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 163 MXS_PHY_NEED_IP_FIX, 164}; 165 166static const struct mxs_phy_data imx6sl_phy_data = { 167 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 168 MXS_PHY_NEED_IP_FIX, 169}; 170 171static const struct mxs_phy_data vf610_phy_data = { 172 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 173 MXS_PHY_NEED_IP_FIX, 174}; 175 176static const struct mxs_phy_data imx6sx_phy_data = { 177 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 178}; 179 180static const struct mxs_phy_data imx6ul_phy_data = { 181 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 182}; 183 184static const struct mxs_phy_data imx7ulp_phy_data = { 185}; 186 187static const struct of_device_id mxs_phy_dt_ids[] = { 188 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, 189 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 190 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 191 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 192 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, 193 { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, }, 194 { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, }, 195 { /* sentinel */ } 196}; 197MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 198 199struct mxs_phy { 200 struct usb_phy phy; 201 struct clk *clk; 202 const struct mxs_phy_data *data; 203 struct regmap *regmap_anatop; 204 int port_id; 205 u32 tx_reg_set; 206 u32 tx_reg_mask; 207}; 208 209static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) 210{ 211 return mxs_phy->data == &imx6q_phy_data; 212} 213 214static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) 215{ 216 return mxs_phy->data == &imx6sl_phy_data; 217} 218 219static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy) 220{ 221 return mxs_phy->data == &imx7ulp_phy_data; 222} 223 224/* 225 * PHY needs some 32K cycles to switch from 32K clock to 226 * bus (such as AHB/AXI, etc) clock. 227 */ 228static void mxs_phy_clock_switch_delay(void) 229{ 230 usleep_range(300, 400); 231} 232 233static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) 234{ 235 void __iomem *base = mxs_phy->phy.io_priv; 236 u32 phytx; 237 238 /* Update TX register if there is anything to write */ 239 if (mxs_phy->tx_reg_mask) { 240 phytx = readl(base + HW_USBPHY_TX); 241 phytx &= ~mxs_phy->tx_reg_mask; 242 phytx |= mxs_phy->tx_reg_set; 243 writel(phytx, base + HW_USBPHY_TX); 244 } 245} 246 247static int mxs_phy_pll_enable(void __iomem *base, bool enable) 248{ 249 int ret = 0; 250 251 if (enable) { 252 u32 value; 253 254 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET); 255 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR); 256 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET); 257 ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC, 258 value, (value & BM_USBPHY_PLL_LOCK) != 0, 259 100, 10000); 260 if (ret) 261 return ret; 262 263 writel(BM_USBPHY_PLL_EN_USB_CLKS, base + 264 HW_USBPHY_PLL_SIC_SET); 265 } else { 266 writel(BM_USBPHY_PLL_EN_USB_CLKS, base + 267 HW_USBPHY_PLL_SIC_CLR); 268 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR); 269 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET); 270 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR); 271 } 272 273 return ret; 274} 275 276static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 277{ 278 int ret; 279 void __iomem *base = mxs_phy->phy.io_priv; 280 281 if (is_imx7ulp_phy(mxs_phy)) { 282 ret = mxs_phy_pll_enable(base, true); 283 if (ret) 284 return ret; 285 } 286 287 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 288 if (ret) 289 goto disable_pll; 290 291 /* Power up the PHY */ 292 writel(0, base + HW_USBPHY_PWD); 293 294 /* 295 * USB PHY Ctrl Setting 296 * - Auto clock/power on 297 * - Enable full/low speed support 298 */ 299 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 300 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 301 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 302 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 303 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 304 BM_USBPHY_CTRL_ENUTMILEVEL2 | 305 BM_USBPHY_CTRL_ENUTMILEVEL3, 306 base + HW_USBPHY_CTRL_SET); 307 308 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) 309 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); 310 311 if (mxs_phy->regmap_anatop) { 312 unsigned int reg = mxs_phy->port_id ? 313 ANADIG_USB1_CHRG_DETECT_SET : 314 ANADIG_USB2_CHRG_DETECT_SET; 315 /* 316 * The external charger detector needs to be disabled, 317 * or the signal at DP will be poor 318 */ 319 regmap_write(mxs_phy->regmap_anatop, reg, 320 ANADIG_USB1_CHRG_DETECT_EN_B | 321 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 322 } 323 324 mxs_phy_tx_init(mxs_phy); 325 326 return 0; 327 328disable_pll: 329 if (is_imx7ulp_phy(mxs_phy)) 330 mxs_phy_pll_enable(base, false); 331 return ret; 332} 333 334/* Return true if the vbus is there */ 335static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) 336{ 337 unsigned int vbus_value = 0; 338 339 if (!mxs_phy->regmap_anatop) 340 return false; 341 342 if (mxs_phy->port_id == 0) 343 regmap_read(mxs_phy->regmap_anatop, 344 ANADIG_USB1_VBUS_DET_STAT, 345 &vbus_value); 346 else if (mxs_phy->port_id == 1) 347 regmap_read(mxs_phy->regmap_anatop, 348 ANADIG_USB2_VBUS_DET_STAT, 349 &vbus_value); 350 351 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) 352 return true; 353 else 354 return false; 355} 356 357static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) 358{ 359 void __iomem *base = mxs_phy->phy.io_priv; 360 u32 reg; 361 362 if (disconnect) 363 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 364 base + HW_USBPHY_DEBUG_CLR); 365 366 if (mxs_phy->port_id == 0) { 367 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET 368 : ANADIG_USB1_LOOPBACK_CLR; 369 regmap_write(mxs_phy->regmap_anatop, reg, 370 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | 371 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); 372 } else if (mxs_phy->port_id == 1) { 373 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET 374 : ANADIG_USB2_LOOPBACK_CLR; 375 regmap_write(mxs_phy->regmap_anatop, reg, 376 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | 377 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); 378 } 379 380 if (!disconnect) 381 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 382 base + HW_USBPHY_DEBUG_SET); 383 384 /* Delay some time, and let Linestate be SE0 for controller */ 385 if (disconnect) 386 usleep_range(500, 1000); 387} 388 389static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) 390{ 391 return mxs_phy->phy.last_event == USB_EVENT_ID; 392} 393 394static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) 395{ 396 bool vbus_is_on = false; 397 398 /* If the SoCs don't need to disconnect line without vbus, quit */ 399 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) 400 return; 401 402 /* If the SoCs don't have anatop, quit */ 403 if (!mxs_phy->regmap_anatop) 404 return; 405 406 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 407 408 if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy)) 409 __mxs_phy_disconnect_line(mxs_phy, true); 410 else 411 __mxs_phy_disconnect_line(mxs_phy, false); 412 413} 414 415static int mxs_phy_init(struct usb_phy *phy) 416{ 417 int ret; 418 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 419 420 mxs_phy_clock_switch_delay(); 421 ret = clk_prepare_enable(mxs_phy->clk); 422 if (ret) 423 return ret; 424 425 return mxs_phy_hw_init(mxs_phy); 426} 427 428static void mxs_phy_shutdown(struct usb_phy *phy) 429{ 430 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 431 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 432 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 433 BM_USBPHY_CTRL_ENIDCHG_WKUP | 434 BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 435 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 436 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 437 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 438 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; 439 440 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); 441 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); 442 443 writel(BM_USBPHY_CTRL_CLKGATE, 444 phy->io_priv + HW_USBPHY_CTRL_SET); 445 446 if (is_imx7ulp_phy(mxs_phy)) 447 mxs_phy_pll_enable(phy->io_priv, false); 448 449 clk_disable_unprepare(mxs_phy->clk); 450} 451 452static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy) 453{ 454 unsigned int line_state; 455 /* bit definition is the same for all controllers */ 456 unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS, 457 dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS; 458 unsigned int reg = ANADIG_USB1_MISC; 459 460 /* If the SoCs don't have anatop, quit */ 461 if (!mxs_phy->regmap_anatop) 462 return false; 463 464 if (mxs_phy->port_id == 0) 465 reg = ANADIG_USB1_MISC; 466 else if (mxs_phy->port_id == 1) 467 reg = ANADIG_USB2_MISC; 468 469 regmap_read(mxs_phy->regmap_anatop, reg, &line_state); 470 471 if ((line_state & (dp_bit | dm_bit)) == dm_bit) 472 return true; 473 else 474 return false; 475} 476 477static int mxs_phy_suspend(struct usb_phy *x, int suspend) 478{ 479 int ret; 480 struct mxs_phy *mxs_phy = to_mxs_phy(x); 481 bool low_speed_connection, vbus_is_on; 482 483 low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy); 484 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 485 486 if (suspend) { 487 /* 488 * FIXME: Do not power down RXPWD1PT1 bit for low speed 489 * connect. The low speed connection will have problem at 490 * very rare cases during usb suspend and resume process. 491 */ 492 if (low_speed_connection & vbus_is_on) { 493 /* 494 * If value to be set as pwd value is not 0xffffffff, 495 * several 32Khz cycles are needed. 496 */ 497 mxs_phy_clock_switch_delay(); 498 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); 499 } else { 500 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 501 } 502 writel(BM_USBPHY_CTRL_CLKGATE, 503 x->io_priv + HW_USBPHY_CTRL_SET); 504 clk_disable_unprepare(mxs_phy->clk); 505 } else { 506 mxs_phy_clock_switch_delay(); 507 ret = clk_prepare_enable(mxs_phy->clk); 508 if (ret) 509 return ret; 510 writel(BM_USBPHY_CTRL_CLKGATE, 511 x->io_priv + HW_USBPHY_CTRL_CLR); 512 writel(0, x->io_priv + HW_USBPHY_PWD); 513 } 514 515 return 0; 516} 517 518static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) 519{ 520 struct mxs_phy *mxs_phy = to_mxs_phy(x); 521 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 522 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 523 BM_USBPHY_CTRL_ENIDCHG_WKUP; 524 if (enabled) { 525 mxs_phy_disconnect_line(mxs_phy, true); 526 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); 527 } else { 528 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); 529 mxs_phy_disconnect_line(mxs_phy, false); 530 } 531 532 return 0; 533} 534 535static int mxs_phy_on_connect(struct usb_phy *phy, 536 enum usb_device_speed speed) 537{ 538 dev_dbg(phy->dev, "%s device has connected\n", 539 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 540 541 if (speed == USB_SPEED_HIGH) 542 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 543 phy->io_priv + HW_USBPHY_CTRL_SET); 544 545 return 0; 546} 547 548static int mxs_phy_on_disconnect(struct usb_phy *phy, 549 enum usb_device_speed speed) 550{ 551 dev_dbg(phy->dev, "%s device has disconnected\n", 552 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 553 554 /* Sometimes, the speed is not high speed when the error occurs */ 555 if (readl(phy->io_priv + HW_USBPHY_CTRL) & 556 BM_USBPHY_CTRL_ENHOSTDISCONDETECT) 557 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 558 phy->io_priv + HW_USBPHY_CTRL_CLR); 559 560 return 0; 561} 562 563#define MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT 100 564static int mxs_charger_data_contact_detect(struct mxs_phy *x) 565{ 566 struct regmap *regmap = x->regmap_anatop; 567 int i, stable_contact_count = 0; 568 u32 val; 569 570 /* Check if vbus is valid */ 571 regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val); 572 if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) { 573 dev_err(x->phy.dev, "vbus is not valid\n"); 574 return -EINVAL; 575 } 576 577 /* Enable charger detector */ 578 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 579 ANADIG_USB1_CHRG_DETECT_EN_B); 580 /* 581 * - Do not check whether a charger is connected to the USB port 582 * - Check whether the USB plug has been in contact with each other 583 */ 584 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 585 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 586 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 587 588 /* Check if plug is connected */ 589 for (i = 0; i < MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT; i++) { 590 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 591 if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) { 592 stable_contact_count++; 593 if (stable_contact_count > 5) 594 /* Data pin makes contact */ 595 break; 596 else 597 usleep_range(5000, 10000); 598 } else { 599 stable_contact_count = 0; 600 usleep_range(5000, 6000); 601 } 602 } 603 604 if (i == MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT) { 605 dev_err(x->phy.dev, 606 "Data pin can't make good contact.\n"); 607 /* Disable charger detector */ 608 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 609 ANADIG_USB1_CHRG_DETECT_EN_B | 610 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 611 return -ENXIO; 612 } 613 614 return 0; 615} 616 617static enum usb_charger_type mxs_charger_primary_detection(struct mxs_phy *x) 618{ 619 struct regmap *regmap = x->regmap_anatop; 620 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 621 u32 val; 622 623 /* 624 * - Do check whether a charger is connected to the USB port 625 * - Do not Check whether the USB plug has been in contact with 626 * each other 627 */ 628 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 629 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 630 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 631 632 msleep(100); 633 634 /* Check if it is a charger */ 635 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 636 if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) { 637 chgr_type = SDP_TYPE; 638 dev_dbg(x->phy.dev, "It is a standard downstream port\n"); 639 } 640 641 /* Disable charger detector */ 642 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 643 ANADIG_USB1_CHRG_DETECT_EN_B | 644 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 645 646 return chgr_type; 647} 648 649/* 650 * It must be called after DP is pulled up, which is used to 651 * differentiate DCP and CDP. 652 */ 653static enum usb_charger_type mxs_charger_secondary_detection(struct mxs_phy *x) 654{ 655 struct regmap *regmap = x->regmap_anatop; 656 int val; 657 658 msleep(80); 659 660 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 661 if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) { 662 dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); 663 return DCP_TYPE; 664 } else { 665 dev_dbg(x->phy.dev, "It is a charging downstream port\n"); 666 return CDP_TYPE; 667 } 668} 669 670static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy) 671{ 672 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 673 struct regmap *regmap = mxs_phy->regmap_anatop; 674 void __iomem *base = phy->io_priv; 675 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 676 677 if (!regmap) 678 return UNKNOWN_TYPE; 679 680 if (mxs_charger_data_contact_detect(mxs_phy)) 681 return chgr_type; 682 683 chgr_type = mxs_charger_primary_detection(mxs_phy); 684 685 if (chgr_type != SDP_TYPE) { 686 /* Pull up DP via test */ 687 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 688 base + HW_USBPHY_DEBUG_CLR); 689 regmap_write(regmap, ANADIG_USB1_LOOPBACK_SET, 690 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 691 692 chgr_type = mxs_charger_secondary_detection(mxs_phy); 693 694 /* Stop the test */ 695 regmap_write(regmap, ANADIG_USB1_LOOPBACK_CLR, 696 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 697 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 698 base + HW_USBPHY_DEBUG_SET); 699 } 700 701 return chgr_type; 702} 703 704static int mxs_phy_probe(struct platform_device *pdev) 705{ 706 void __iomem *base; 707 struct clk *clk; 708 struct mxs_phy *mxs_phy; 709 int ret; 710 const struct of_device_id *of_id; 711 struct device_node *np = pdev->dev.of_node; 712 u32 val; 713 714 of_id = of_match_device(mxs_phy_dt_ids, &pdev->dev); 715 if (!of_id) 716 return -ENODEV; 717 718 base = devm_platform_ioremap_resource(pdev, 0); 719 if (IS_ERR(base)) 720 return PTR_ERR(base); 721 722 clk = devm_clk_get(&pdev->dev, NULL); 723 if (IS_ERR(clk)) { 724 dev_err(&pdev->dev, 725 "can't get the clock, err=%ld", PTR_ERR(clk)); 726 return PTR_ERR(clk); 727 } 728 729 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 730 if (!mxs_phy) 731 return -ENOMEM; 732 733 /* Some SoCs don't have anatop registers */ 734 if (of_get_property(np, "fsl,anatop", NULL)) { 735 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 736 (np, "fsl,anatop"); 737 if (IS_ERR(mxs_phy->regmap_anatop)) { 738 dev_dbg(&pdev->dev, 739 "failed to find regmap for anatop\n"); 740 return PTR_ERR(mxs_phy->regmap_anatop); 741 } 742 } 743 744 /* Precompute which bits of the TX register are to be updated, if any */ 745 if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && 746 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 747 /* Scale to a 4-bit value */ 748 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 749 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 750 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); 751 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); 752 } 753 754 if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && 755 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 756 /* Scale to a 4-bit value. */ 757 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 758 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 759 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); 760 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); 761 } 762 763 if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && 764 val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) { 765 /* Scale to a 4-bit value. Round up the values and heavily 766 * weight the rounding by adding 2/3 of the denominator. 767 */ 768 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF 769 + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) 770 / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); 771 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); 772 mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); 773 } 774 775 ret = of_alias_get_id(np, "usbphy"); 776 if (ret < 0) 777 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); 778 mxs_phy->port_id = ret; 779 780 mxs_phy->phy.io_priv = base; 781 mxs_phy->phy.dev = &pdev->dev; 782 mxs_phy->phy.label = DRIVER_NAME; 783 mxs_phy->phy.init = mxs_phy_init; 784 mxs_phy->phy.shutdown = mxs_phy_shutdown; 785 mxs_phy->phy.set_suspend = mxs_phy_suspend; 786 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 787 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 788 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 789 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; 790 mxs_phy->phy.charger_detect = mxs_phy_charger_detect; 791 792 mxs_phy->clk = clk; 793 mxs_phy->data = of_id->data; 794 795 platform_set_drvdata(pdev, mxs_phy); 796 797 device_set_wakeup_capable(&pdev->dev, true); 798 799 return usb_add_phy_dev(&mxs_phy->phy); 800} 801 802static int mxs_phy_remove(struct platform_device *pdev) 803{ 804 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 805 806 usb_remove_phy(&mxs_phy->phy); 807 808 return 0; 809} 810 811#ifdef CONFIG_PM_SLEEP 812static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) 813{ 814 unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 815 816 /* If the SoCs don't have anatop, quit */ 817 if (!mxs_phy->regmap_anatop) 818 return; 819 820 if (is_imx6q_phy(mxs_phy)) 821 regmap_write(mxs_phy->regmap_anatop, reg, 822 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); 823 else if (is_imx6sl_phy(mxs_phy)) 824 regmap_write(mxs_phy->regmap_anatop, 825 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); 826} 827 828static int mxs_phy_system_suspend(struct device *dev) 829{ 830 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 831 832 if (device_may_wakeup(dev)) 833 mxs_phy_enable_ldo_in_suspend(mxs_phy, true); 834 835 return 0; 836} 837 838static int mxs_phy_system_resume(struct device *dev) 839{ 840 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 841 842 if (device_may_wakeup(dev)) 843 mxs_phy_enable_ldo_in_suspend(mxs_phy, false); 844 845 return 0; 846} 847#endif /* CONFIG_PM_SLEEP */ 848 849static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, 850 mxs_phy_system_resume); 851 852static struct platform_driver mxs_phy_driver = { 853 .probe = mxs_phy_probe, 854 .remove = mxs_phy_remove, 855 .driver = { 856 .name = DRIVER_NAME, 857 .of_match_table = mxs_phy_dt_ids, 858 .pm = &mxs_phy_pm, 859 }, 860}; 861 862static int __init mxs_phy_module_init(void) 863{ 864 return platform_driver_register(&mxs_phy_driver); 865} 866postcore_initcall(mxs_phy_module_init); 867 868static void __exit mxs_phy_module_exit(void) 869{ 870 platform_driver_unregister(&mxs_phy_driver); 871} 872module_exit(mxs_phy_module_exit); 873 874MODULE_ALIAS("platform:mxs-usb-phy"); 875MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 876MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 877MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 878MODULE_LICENSE("GPL"); 879