1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * MUSB OTG driver DMA controller abstraction
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 */
9
10#ifndef __MUSB_DMA_H__
11#define __MUSB_DMA_H__
12
13struct musb_hw_ep;
14
15/*
16 * DMA Controller Abstraction
17 *
18 * DMA Controllers are abstracted to allow use of a variety of different
19 * implementations of DMA, as allowed by the Inventra USB cores.  On the
20 * host side, usbcore sets up the DMA mappings and flushes caches; on the
21 * peripheral side, the gadget controller driver does.  Responsibilities
22 * of a DMA controller driver include:
23 *
24 *  - Handling the details of moving multiple USB packets
25 *    in cooperation with the Inventra USB core, including especially
26 *    the correct RX side treatment of short packets and buffer-full
27 *    states (both of which terminate transfers).
28 *
29 *  - Knowing the correlation between dma channels and the
30 *    Inventra core's local endpoint resources and data direction.
31 *
32 *  - Maintaining a list of allocated/available channels.
33 *
34 *  - Updating channel status on interrupts,
35 *    whether shared with the Inventra core or separate.
36 */
37
38#define MUSB_HSDMA_BASE		0x200
39#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
40#define MUSB_HSDMA_CONTROL	0x4
41#define MUSB_HSDMA_ADDRESS	0x8
42#define MUSB_HSDMA_COUNT	0xc
43
44#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
45
46#ifdef CONFIG_MUSB_PIO_ONLY
47#define	is_dma_capable()	(0)
48#else
49#define	is_dma_capable()	(1)
50#endif
51
52#ifdef CONFIG_USB_UX500_DMA
53#define musb_dma_ux500(musb)		(musb->ops->quirks & MUSB_DMA_UX500)
54#else
55#define musb_dma_ux500(musb)		0
56#endif
57
58#ifdef CONFIG_USB_TI_CPPI41_DMA
59#define musb_dma_cppi41(musb)		(musb->ops->quirks & MUSB_DMA_CPPI41)
60#else
61#define musb_dma_cppi41(musb)		0
62#endif
63
64#ifdef CONFIG_USB_TI_CPPI_DMA
65#define musb_dma_cppi(musb)		(musb->ops->quirks & MUSB_DMA_CPPI)
66#else
67#define musb_dma_cppi(musb)		0
68#endif
69
70#ifdef CONFIG_USB_TUSB_OMAP_DMA
71#define tusb_dma_omap(musb)		(musb->ops->quirks & MUSB_DMA_TUSB_OMAP)
72#else
73#define tusb_dma_omap(musb)		0
74#endif
75
76#ifdef CONFIG_USB_INVENTRA_DMA
77#define musb_dma_inventra(musb)		(musb->ops->quirks & MUSB_DMA_INVENTRA)
78#else
79#define musb_dma_inventra(musb)		0
80#endif
81
82#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
83#define	is_cppi_enabled(musb)		\
84	(musb_dma_cppi(musb) || musb_dma_cppi41(musb))
85#else
86#define	is_cppi_enabled(musb)	0
87#endif
88
89/*
90 * DMA channel status ... updated by the dma controller driver whenever that
91 * status changes, and protected by the overall controller spinlock.
92 */
93enum dma_channel_status {
94	/* unallocated */
95	MUSB_DMA_STATUS_UNKNOWN,
96	/* allocated ... but not busy, no errors */
97	MUSB_DMA_STATUS_FREE,
98	/* busy ... transactions are active */
99	MUSB_DMA_STATUS_BUSY,
100	/* transaction(s) aborted due to ... dma or memory bus error */
101	MUSB_DMA_STATUS_BUS_ABORT,
102	/* transaction(s) aborted due to ... core error or USB fault */
103	MUSB_DMA_STATUS_CORE_ABORT
104};
105
106struct dma_controller;
107
108/**
109 * struct dma_channel - A DMA channel.
110 * @private_data: channel-private data
111 * @max_len: the maximum number of bytes the channel can move in one
112 *	transaction (typically representing many USB maximum-sized packets)
113 * @actual_len: how many bytes have been transferred
114 * @status: current channel status (updated e.g. on interrupt)
115 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
116 *
117 * channels are associated with an endpoint for the duration of at least
118 * one usb transfer.
119 */
120struct dma_channel {
121	void			*private_data;
122	/* FIXME not void* private_data, but a dma_controller * */
123	size_t			max_len;
124	size_t			actual_len;
125	enum dma_channel_status	status;
126	bool			desired_mode;
127	bool			rx_packet_done;
128};
129
130/*
131 * dma_channel_status - return status of dma channel
132 * @c: the channel
133 *
134 * Returns the software's view of the channel status.  If that status is BUSY
135 * then it's possible that the hardware has completed (or aborted) a transfer,
136 * so the driver needs to update that status.
137 */
138static inline enum dma_channel_status
139dma_channel_status(struct dma_channel *c)
140{
141	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
142}
143
144/**
145 * struct dma_controller - A DMA Controller.
146 * @musb: the usb controller
147 * @start: call this to start a DMA controller;
148 *	return 0 on success, else negative errno
149 * @stop: call this to stop a DMA controller
150 *	return 0 on success, else negative errno
151 * @channel_alloc: call this to allocate a DMA channel
152 * @channel_release: call this to release a DMA channel
153 * @channel_abort: call this to abort a pending DMA transaction,
154 *	returning it to FREE (but allocated) state
155 * @dma_callback: invoked on DMA completion, useful to run platform
156 *	code such IRQ acknowledgment.
157 *
158 * Controllers manage dma channels.
159 */
160struct dma_controller {
161	struct musb *musb;
162	struct dma_channel	*(*channel_alloc)(struct dma_controller *,
163					struct musb_hw_ep *, u8 is_tx);
164	void			(*channel_release)(struct dma_channel *);
165	int			(*channel_program)(struct dma_channel *channel,
166							u16 maxpacket, u8 mode,
167							dma_addr_t dma_addr,
168							u32 length);
169	int			(*channel_abort)(struct dma_channel *);
170	int			(*is_compatible)(struct dma_channel *channel,
171							u16 maxpacket,
172							void *buf, u32 length);
173	void			(*dma_callback)(struct dma_controller *);
174};
175
176/* called after channel_program(), may indicate a fault */
177extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
178
179#ifdef CONFIG_MUSB_PIO_ONLY
180static inline struct dma_controller *
181musb_dma_controller_create(struct musb *m, void __iomem *io)
182{
183	return NULL;
184}
185
186static inline void musb_dma_controller_destroy(struct dma_controller *d) { }
187
188#else
189
190extern struct dma_controller *
191(*musb_dma_controller_create)(struct musb *, void __iomem *);
192
193extern void (*musb_dma_controller_destroy)(struct dma_controller *);
194#endif
195
196/* Platform specific DMA functions */
197extern struct dma_controller *
198musbhs_dma_controller_create(struct musb *musb, void __iomem *base);
199extern void musbhs_dma_controller_destroy(struct dma_controller *c);
200extern struct dma_controller *
201musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base);
202extern irqreturn_t dma_controller_irq(int irq, void *private_data);
203
204extern struct dma_controller *
205tusb_dma_controller_create(struct musb *musb, void __iomem *base);
206extern void tusb_dma_controller_destroy(struct dma_controller *c);
207
208extern struct dma_controller *
209cppi_dma_controller_create(struct musb *musb, void __iomem *base);
210extern void cppi_dma_controller_destroy(struct dma_controller *c);
211
212extern struct dma_controller *
213cppi41_dma_controller_create(struct musb *musb, void __iomem *base);
214extern void cppi41_dma_controller_destroy(struct dma_controller *c);
215
216extern struct dma_controller *
217ux500_dma_controller_create(struct musb *musb, void __iomem *base);
218extern void ux500_dma_controller_destroy(struct dma_controller *c);
219
220#endif	/* __MUSB_DMA_H__ */
221