1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the NXP ISP1760 chip 4 * 5 * However, the code might contain some bugs. What doesn't work for sure is: 6 * - ISO 7 * - OTG 8 e The interrupt line is configured as active low, level. 9 * 10 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> 11 * 12 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> 13 * 14 */ 15#include <linux/gpio/consumer.h> 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/list.h> 20#include <linux/usb.h> 21#include <linux/usb/hcd.h> 22#include <linux/debugfs.h> 23#include <linux/uaccess.h> 24#include <linux/io.h> 25#include <linux/iopoll.h> 26#include <linux/mm.h> 27#include <linux/timer.h> 28#include <asm/unaligned.h> 29#include <asm/cacheflush.h> 30 31#include "isp1760-core.h" 32#include "isp1760-hcd.h" 33#include "isp1760-regs.h" 34 35static struct kmem_cache *qtd_cachep; 36static struct kmem_cache *qh_cachep; 37static struct kmem_cache *urb_listitem_cachep; 38 39typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 40 struct isp1760_qtd *qtd); 41 42static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 43{ 44 return *(struct isp1760_hcd **)hcd->hcd_priv; 45} 46 47/* urb state*/ 48#define DELETE_URB (0x0008) 49#define NO_TRANSFER_ACTIVE (0xffffffff) 50 51/* Philips Proprietary Transfer Descriptor (PTD) */ 52typedef __u32 __bitwise __dw; 53struct ptd { 54 __dw dw0; 55 __dw dw1; 56 __dw dw2; 57 __dw dw3; 58 __dw dw4; 59 __dw dw5; 60 __dw dw6; 61 __dw dw7; 62}; 63#define PTD_OFFSET 0x0400 64#define ISO_PTD_OFFSET 0x0400 65#define INT_PTD_OFFSET 0x0800 66#define ATL_PTD_OFFSET 0x0c00 67#define PAYLOAD_OFFSET 0x1000 68 69 70/* ATL */ 71/* DW0 */ 72#define DW0_VALID_BIT 1 73#define FROM_DW0_VALID(x) ((x) & 0x01) 74#define TO_DW0_LENGTH(x) (((u32) x) << 3) 75#define TO_DW0_MAXPACKET(x) (((u32) x) << 18) 76#define TO_DW0_MULTI(x) (((u32) x) << 29) 77#define TO_DW0_ENDPOINT(x) (((u32) x) << 31) 78/* DW1 */ 79#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) 80#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) 81#define DW1_TRANS_BULK ((u32) 2 << 12) 82#define DW1_TRANS_INT ((u32) 3 << 12) 83#define DW1_TRANS_SPLIT ((u32) 1 << 14) 84#define DW1_SE_USB_LOSPEED ((u32) 2 << 16) 85#define TO_DW1_PORT_NUM(x) (((u32) x) << 18) 86#define TO_DW1_HUB_NUM(x) (((u32) x) << 25) 87/* DW2 */ 88#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) 89#define TO_DW2_RL(x) ((x) << 25) 90#define FROM_DW2_RL(x) (((x) >> 25) & 0xf) 91/* DW3 */ 92#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) 93#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) 94#define TO_DW3_NAKCOUNT(x) ((x) << 19) 95#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) 96#define TO_DW3_CERR(x) ((x) << 23) 97#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) 98#define TO_DW3_DATA_TOGGLE(x) ((x) << 25) 99#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) 100#define TO_DW3_PING(x) ((x) << 26) 101#define FROM_DW3_PING(x) (((x) >> 26) & 0x1) 102#define DW3_ERROR_BIT (1 << 28) 103#define DW3_BABBLE_BIT (1 << 29) 104#define DW3_HALT_BIT (1 << 30) 105#define DW3_ACTIVE_BIT (1 << 31) 106#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01) 107 108#define INT_UNDERRUN (1 << 2) 109#define INT_BABBLE (1 << 1) 110#define INT_EXACT (1 << 0) 111 112#define SETUP_PID (2) 113#define IN_PID (1) 114#define OUT_PID (0) 115 116/* Errata 1 */ 117#define RL_COUNTER (0) 118#define NAK_COUNTER (0) 119#define ERR_COUNTER (2) 120 121struct isp1760_qtd { 122 u8 packet_type; 123 void *data_buffer; 124 u32 payload_addr; 125 126 /* the rest is HCD-private */ 127 struct list_head qtd_list; 128 struct urb *urb; 129 size_t length; 130 size_t actual_length; 131 132 /* QTD_ENQUEUED: waiting for transfer (inactive) */ 133 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ 134 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only 135 interrupt handler may touch this qtd! */ 136 /* QTD_XFER_COMPLETE: payload has been transferred successfully */ 137 /* QTD_RETIRE: transfer error/abort qtd */ 138#define QTD_ENQUEUED 0 139#define QTD_PAYLOAD_ALLOC 1 140#define QTD_XFER_STARTED 2 141#define QTD_XFER_COMPLETE 3 142#define QTD_RETIRE 4 143 u32 status; 144}; 145 146/* Queue head, one for each active endpoint */ 147struct isp1760_qh { 148 struct list_head qh_list; 149 struct list_head qtd_list; 150 u32 toggle; 151 u32 ping; 152 int slot; 153 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ 154}; 155 156struct urb_listitem { 157 struct list_head urb_list; 158 struct urb *urb; 159}; 160 161/* 162 * Access functions for isp176x registers (addresses 0..0x03FF). 163 */ 164static u32 reg_read32(void __iomem *base, u32 reg) 165{ 166 return isp1760_read32(base, reg); 167} 168 169static void reg_write32(void __iomem *base, u32 reg, u32 val) 170{ 171 isp1760_write32(base, reg, val); 172} 173 174/* 175 * Access functions for isp176x memory (offset >= 0x0400). 176 * 177 * bank_reads8() reads memory locations prefetched by an earlier write to 178 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- 179 * bank optimizations, you should use the more generic mem_reads8() below. 180 * 181 * For access to ptd memory, use the specialized ptd_read() and ptd_write() 182 * below. 183 * 184 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() 185 * doesn't quite work because some people have to enforce 32-bit access 186 */ 187static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, 188 __u32 *dst, u32 bytes) 189{ 190 __u32 __iomem *src; 191 u32 val; 192 __u8 *src_byteptr; 193 __u8 *dst_byteptr; 194 195 src = src_base + (bank_addr | src_offset); 196 197 if (src_offset < PAYLOAD_OFFSET) { 198 while (bytes >= 4) { 199 *dst = le32_to_cpu(__raw_readl(src)); 200 bytes -= 4; 201 src++; 202 dst++; 203 } 204 } else { 205 while (bytes >= 4) { 206 *dst = __raw_readl(src); 207 bytes -= 4; 208 src++; 209 dst++; 210 } 211 } 212 213 if (!bytes) 214 return; 215 216 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 217 * allocated. 218 */ 219 if (src_offset < PAYLOAD_OFFSET) 220 val = le32_to_cpu(__raw_readl(src)); 221 else 222 val = __raw_readl(src); 223 224 dst_byteptr = (void *) dst; 225 src_byteptr = (void *) &val; 226 while (bytes > 0) { 227 *dst_byteptr = *src_byteptr; 228 dst_byteptr++; 229 src_byteptr++; 230 bytes--; 231 } 232} 233 234static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, 235 u32 bytes) 236{ 237 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); 238 ndelay(90); 239 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); 240} 241 242static void mem_writes8(void __iomem *dst_base, u32 dst_offset, 243 __u32 const *src, u32 bytes) 244{ 245 __u32 __iomem *dst; 246 247 dst = dst_base + dst_offset; 248 249 if (dst_offset < PAYLOAD_OFFSET) { 250 while (bytes >= 4) { 251 __raw_writel(cpu_to_le32(*src), dst); 252 bytes -= 4; 253 src++; 254 dst++; 255 } 256 } else { 257 while (bytes >= 4) { 258 __raw_writel(*src, dst); 259 bytes -= 4; 260 src++; 261 dst++; 262 } 263 } 264 265 if (!bytes) 266 return; 267 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the 268 * extra bytes should not be read by the HW. 269 */ 270 271 if (dst_offset < PAYLOAD_OFFSET) 272 __raw_writel(cpu_to_le32(*src), dst); 273 else 274 __raw_writel(*src, dst); 275} 276 277/* 278 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, 279 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. 280 */ 281static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, 282 struct ptd *ptd) 283{ 284 reg_write32(base, HC_MEMORY_REG, 285 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); 286 ndelay(90); 287 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), 288 (void *) ptd, sizeof(*ptd)); 289} 290 291static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, 292 struct ptd *ptd) 293{ 294 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), 295 &ptd->dw1, 7*sizeof(ptd->dw1)); 296 /* Make sure dw0 gets written last (after other dw's and after payload) 297 since it contains the enable bit */ 298 wmb(); 299 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, 300 sizeof(ptd->dw0)); 301} 302 303 304/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 305static void init_memory(struct isp1760_hcd *priv) 306{ 307 int i, curr; 308 u32 payload_addr; 309 310 payload_addr = PAYLOAD_OFFSET; 311 for (i = 0; i < BLOCK_1_NUM; i++) { 312 priv->memory_pool[i].start = payload_addr; 313 priv->memory_pool[i].size = BLOCK_1_SIZE; 314 priv->memory_pool[i].free = 1; 315 payload_addr += priv->memory_pool[i].size; 316 } 317 318 curr = i; 319 for (i = 0; i < BLOCK_2_NUM; i++) { 320 priv->memory_pool[curr + i].start = payload_addr; 321 priv->memory_pool[curr + i].size = BLOCK_2_SIZE; 322 priv->memory_pool[curr + i].free = 1; 323 payload_addr += priv->memory_pool[curr + i].size; 324 } 325 326 curr = i; 327 for (i = 0; i < BLOCK_3_NUM; i++) { 328 priv->memory_pool[curr + i].start = payload_addr; 329 priv->memory_pool[curr + i].size = BLOCK_3_SIZE; 330 priv->memory_pool[curr + i].free = 1; 331 payload_addr += priv->memory_pool[curr + i].size; 332 } 333 334 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); 335} 336 337static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 338{ 339 struct isp1760_hcd *priv = hcd_to_priv(hcd); 340 int i; 341 342 WARN_ON(qtd->payload_addr); 343 344 if (!qtd->length) 345 return; 346 347 for (i = 0; i < BLOCKS; i++) { 348 if (priv->memory_pool[i].size >= qtd->length && 349 priv->memory_pool[i].free) { 350 priv->memory_pool[i].free = 0; 351 qtd->payload_addr = priv->memory_pool[i].start; 352 return; 353 } 354 } 355} 356 357static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 358{ 359 struct isp1760_hcd *priv = hcd_to_priv(hcd); 360 int i; 361 362 if (!qtd->payload_addr) 363 return; 364 365 for (i = 0; i < BLOCKS; i++) { 366 if (priv->memory_pool[i].start == qtd->payload_addr) { 367 WARN_ON(priv->memory_pool[i].free); 368 priv->memory_pool[i].free = 1; 369 qtd->payload_addr = 0; 370 return; 371 } 372 } 373 374 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", 375 __func__, qtd->payload_addr); 376 WARN_ON(1); 377 qtd->payload_addr = 0; 378} 379 380static int handshake(struct usb_hcd *hcd, u32 reg, 381 u32 mask, u32 done, int usec) 382{ 383 u32 result; 384 int ret; 385 386 ret = readl_poll_timeout_atomic(hcd->regs + reg, result, 387 ((result & mask) == done || 388 result == U32_MAX), 1, usec); 389 if (result == U32_MAX) 390 return -ENODEV; 391 392 return ret; 393} 394 395/* reset a non-running (STS_HALT == 1) controller */ 396static int ehci_reset(struct usb_hcd *hcd) 397{ 398 struct isp1760_hcd *priv = hcd_to_priv(hcd); 399 400 u32 command = reg_read32(hcd->regs, HC_USBCMD); 401 402 command |= CMD_RESET; 403 reg_write32(hcd->regs, HC_USBCMD, command); 404 hcd->state = HC_STATE_HALT; 405 priv->next_statechange = jiffies; 406 407 return handshake(hcd, HC_USBCMD, CMD_RESET, 0, 250 * 1000); 408} 409 410static struct isp1760_qh *qh_alloc(gfp_t flags) 411{ 412 struct isp1760_qh *qh; 413 414 qh = kmem_cache_zalloc(qh_cachep, flags); 415 if (!qh) 416 return NULL; 417 418 INIT_LIST_HEAD(&qh->qh_list); 419 INIT_LIST_HEAD(&qh->qtd_list); 420 qh->slot = -1; 421 422 return qh; 423} 424 425static void qh_free(struct isp1760_qh *qh) 426{ 427 WARN_ON(!list_empty(&qh->qtd_list)); 428 WARN_ON(qh->slot > -1); 429 kmem_cache_free(qh_cachep, qh); 430} 431 432/* one-time init, only for memory state */ 433static int priv_init(struct usb_hcd *hcd) 434{ 435 struct isp1760_hcd *priv = hcd_to_priv(hcd); 436 u32 hcc_params; 437 int i; 438 439 spin_lock_init(&priv->lock); 440 441 for (i = 0; i < QH_END; i++) 442 INIT_LIST_HEAD(&priv->qh_list[i]); 443 444 /* 445 * hw default: 1K periodic list heads, one per frame. 446 * periodic_size can shrink by USBCMD update if hcc_params allows. 447 */ 448 priv->periodic_size = DEFAULT_I_TDPS; 449 450 /* controllers may cache some of the periodic schedule ... */ 451 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); 452 /* full frame cache */ 453 if (HCC_ISOC_CACHE(hcc_params)) 454 priv->i_thresh = 8; 455 else /* N microframes cached */ 456 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 457 458 return 0; 459} 460 461static int isp1760_hc_setup(struct usb_hcd *hcd) 462{ 463 struct isp1760_hcd *priv = hcd_to_priv(hcd); 464 int result; 465 u32 scratch, hwmode; 466 467 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); 468 /* Change bus pattern */ 469 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); 470 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); 471 if (scratch != 0xdeadbabe) { 472 dev_err(hcd->self.controller, "Scratch test failed.\n"); 473 return -ENODEV; 474 } 475 476 /* 477 * The RESET_HC bit in the SW_RESET register is supposed to reset the 478 * host controller without touching the CPU interface registers, but at 479 * least on the ISP1761 it seems to behave as the RESET_ALL bit and 480 * reset the whole device. We thus can't use it here, so let's reset 481 * the host controller through the EHCI USB Command register. The device 482 * has been reset in core code anyway, so this shouldn't matter. 483 */ 484 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); 485 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 486 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 487 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 488 489 result = ehci_reset(hcd); 490 if (result) 491 return result; 492 493 /* Step 11 passed */ 494 495 /* ATL reset */ 496 hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET; 497 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); 498 mdelay(10); 499 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); 500 501 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); 502 503 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); 504 505 return priv_init(hcd); 506} 507 508static u32 base_to_chip(u32 base) 509{ 510 return ((base - 0x400) >> 3); 511} 512 513static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) 514{ 515 struct urb *urb; 516 517 if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) 518 return 1; 519 520 urb = qtd->urb; 521 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); 522 return (qtd->urb != urb); 523} 524 525/* magic numbers that can affect system performance */ 526#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 527#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 528#define EHCI_TUNE_RL_TT 0 529#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 530#define EHCI_TUNE_MULT_TT 1 531#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 532 533static void create_ptd_atl(struct isp1760_qh *qh, 534 struct isp1760_qtd *qtd, struct ptd *ptd) 535{ 536 u32 maxpacket; 537 u32 multi; 538 u32 rl = RL_COUNTER; 539 u32 nak = NAK_COUNTER; 540 541 memset(ptd, 0, sizeof(*ptd)); 542 543 /* according to 3.6.2, max packet len can not be > 0x400 */ 544 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, 545 usb_pipeout(qtd->urb->pipe)); 546 multi = 1 + ((maxpacket >> 11) & 0x3); 547 maxpacket &= 0x7ff; 548 549 /* DW0 */ 550 ptd->dw0 = DW0_VALID_BIT; 551 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); 552 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); 553 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); 554 555 /* DW1 */ 556 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; 557 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); 558 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); 559 560 if (usb_pipebulk(qtd->urb->pipe)) 561 ptd->dw1 |= DW1_TRANS_BULK; 562 else if (usb_pipeint(qtd->urb->pipe)) 563 ptd->dw1 |= DW1_TRANS_INT; 564 565 if (qtd->urb->dev->speed != USB_SPEED_HIGH) { 566 /* split transaction */ 567 568 ptd->dw1 |= DW1_TRANS_SPLIT; 569 if (qtd->urb->dev->speed == USB_SPEED_LOW) 570 ptd->dw1 |= DW1_SE_USB_LOSPEED; 571 572 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); 573 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); 574 575 /* SE bit for Split INT transfers */ 576 if (usb_pipeint(qtd->urb->pipe) && 577 (qtd->urb->dev->speed == USB_SPEED_LOW)) 578 ptd->dw1 |= 2 << 16; 579 580 rl = 0; 581 nak = 0; 582 } else { 583 ptd->dw0 |= TO_DW0_MULTI(multi); 584 if (usb_pipecontrol(qtd->urb->pipe) || 585 usb_pipebulk(qtd->urb->pipe)) 586 ptd->dw3 |= TO_DW3_PING(qh->ping); 587 } 588 /* DW2 */ 589 ptd->dw2 = 0; 590 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); 591 ptd->dw2 |= TO_DW2_RL(rl); 592 593 /* DW3 */ 594 ptd->dw3 |= TO_DW3_NAKCOUNT(nak); 595 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); 596 if (usb_pipecontrol(qtd->urb->pipe)) { 597 if (qtd->data_buffer == qtd->urb->setup_packet) 598 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); 599 else if (last_qtd_of_urb(qtd, qh)) 600 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); 601 } 602 603 ptd->dw3 |= DW3_ACTIVE_BIT; 604 /* Cerr */ 605 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); 606} 607 608static void transform_add_int(struct isp1760_qh *qh, 609 struct isp1760_qtd *qtd, struct ptd *ptd) 610{ 611 u32 usof; 612 u32 period; 613 614 /* 615 * Most of this is guessing. ISP1761 datasheet is quite unclear, and 616 * the algorithm from the original Philips driver code, which was 617 * pretty much used in this driver before as well, is quite horrendous 618 * and, i believe, incorrect. The code below follows the datasheet and 619 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much 620 * more reliable this way (fingers crossed...). 621 */ 622 623 if (qtd->urb->dev->speed == USB_SPEED_HIGH) { 624 /* urb->interval is in units of microframes (1/8 ms) */ 625 period = qtd->urb->interval >> 3; 626 627 if (qtd->urb->interval > 4) 628 usof = 0x01; /* One bit set => 629 interval 1 ms * uFrame-match */ 630 else if (qtd->urb->interval > 2) 631 usof = 0x22; /* Two bits set => interval 1/2 ms */ 632 else if (qtd->urb->interval > 1) 633 usof = 0x55; /* Four bits set => interval 1/4 ms */ 634 else 635 usof = 0xff; /* All bits set => interval 1/8 ms */ 636 } else { 637 /* urb->interval is in units of frames (1 ms) */ 638 period = qtd->urb->interval; 639 usof = 0x0f; /* Execute Start Split on any of the 640 four first uFrames */ 641 642 /* 643 * First 8 bits in dw5 is uSCS and "specifies which uSOF the 644 * complete split needs to be sent. Valid only for IN." Also, 645 * "All bits can be set to one for every transfer." (p 82, 646 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did 647 * that number come from? 0xff seems to work fine... 648 */ 649 /* ptd->dw5 = 0x1c; */ 650 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ 651 } 652 653 period = period >> 1;/* Ensure equal or shorter period than requested */ 654 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ 655 656 ptd->dw2 |= period; 657 ptd->dw4 = usof; 658} 659 660static void create_ptd_int(struct isp1760_qh *qh, 661 struct isp1760_qtd *qtd, struct ptd *ptd) 662{ 663 create_ptd_atl(qh, qtd, ptd); 664 transform_add_int(qh, qtd, ptd); 665} 666 667static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) 668__releases(priv->lock) 669__acquires(priv->lock) 670{ 671 struct isp1760_hcd *priv = hcd_to_priv(hcd); 672 673 if (!urb->unlinked) { 674 if (urb->status == -EINPROGRESS) 675 urb->status = 0; 676 } 677 678 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 679 void *ptr; 680 for (ptr = urb->transfer_buffer; 681 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 682 ptr += PAGE_SIZE) 683 flush_dcache_page(virt_to_page(ptr)); 684 } 685 686 /* complete() can reenter this HCD */ 687 usb_hcd_unlink_urb_from_ep(hcd, urb); 688 spin_unlock(&priv->lock); 689 usb_hcd_giveback_urb(hcd, urb, urb->status); 690 spin_lock(&priv->lock); 691} 692 693static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, 694 u8 packet_type) 695{ 696 struct isp1760_qtd *qtd; 697 698 qtd = kmem_cache_zalloc(qtd_cachep, flags); 699 if (!qtd) 700 return NULL; 701 702 INIT_LIST_HEAD(&qtd->qtd_list); 703 qtd->urb = urb; 704 qtd->packet_type = packet_type; 705 qtd->status = QTD_ENQUEUED; 706 qtd->actual_length = 0; 707 708 return qtd; 709} 710 711static void qtd_free(struct isp1760_qtd *qtd) 712{ 713 WARN_ON(qtd->payload_addr); 714 kmem_cache_free(qtd_cachep, qtd); 715} 716 717static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, 718 struct isp1760_slotinfo *slots, 719 struct isp1760_qtd *qtd, struct isp1760_qh *qh, 720 struct ptd *ptd) 721{ 722 struct isp1760_hcd *priv = hcd_to_priv(hcd); 723 int skip_map; 724 725 WARN_ON((slot < 0) || (slot > 31)); 726 WARN_ON(qtd->length && !qtd->payload_addr); 727 WARN_ON(slots[slot].qtd); 728 WARN_ON(slots[slot].qh); 729 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); 730 731 /* Make sure done map has not triggered from some unlinked transfer */ 732 if (ptd_offset == ATL_PTD_OFFSET) { 733 priv->atl_done_map |= reg_read32(hcd->regs, 734 HC_ATL_PTD_DONEMAP_REG); 735 priv->atl_done_map &= ~(1 << slot); 736 } else { 737 priv->int_done_map |= reg_read32(hcd->regs, 738 HC_INT_PTD_DONEMAP_REG); 739 priv->int_done_map &= ~(1 << slot); 740 } 741 742 qh->slot = slot; 743 qtd->status = QTD_XFER_STARTED; 744 slots[slot].timestamp = jiffies; 745 slots[slot].qtd = qtd; 746 slots[slot].qh = qh; 747 ptd_write(hcd->regs, ptd_offset, slot, ptd); 748 749 if (ptd_offset == ATL_PTD_OFFSET) { 750 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 751 skip_map &= ~(1 << qh->slot); 752 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 753 } else { 754 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 755 skip_map &= ~(1 << qh->slot); 756 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 757 } 758} 759 760static int is_short_bulk(struct isp1760_qtd *qtd) 761{ 762 return (usb_pipebulk(qtd->urb->pipe) && 763 (qtd->actual_length < qtd->length)); 764} 765 766static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, 767 struct list_head *urb_list) 768{ 769 int last_qtd; 770 struct isp1760_qtd *qtd, *qtd_next; 771 struct urb_listitem *urb_listitem; 772 773 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { 774 if (qtd->status < QTD_XFER_COMPLETE) 775 break; 776 777 last_qtd = last_qtd_of_urb(qtd, qh); 778 779 if ((!last_qtd) && (qtd->status == QTD_RETIRE)) 780 qtd_next->status = QTD_RETIRE; 781 782 if (qtd->status == QTD_XFER_COMPLETE) { 783 if (qtd->actual_length) { 784 switch (qtd->packet_type) { 785 case IN_PID: 786 mem_reads8(hcd->regs, qtd->payload_addr, 787 qtd->data_buffer, 788 qtd->actual_length); 789 fallthrough; 790 case OUT_PID: 791 qtd->urb->actual_length += 792 qtd->actual_length; 793 fallthrough; 794 case SETUP_PID: 795 break; 796 } 797 } 798 799 if (is_short_bulk(qtd)) { 800 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) 801 qtd->urb->status = -EREMOTEIO; 802 if (!last_qtd) 803 qtd_next->status = QTD_RETIRE; 804 } 805 } 806 807 if (qtd->payload_addr) 808 free_mem(hcd, qtd); 809 810 if (last_qtd) { 811 if ((qtd->status == QTD_RETIRE) && 812 (qtd->urb->status == -EINPROGRESS)) 813 qtd->urb->status = -EPIPE; 814 /* Defer calling of urb_done() since it releases lock */ 815 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, 816 GFP_ATOMIC); 817 if (unlikely(!urb_listitem)) 818 break; /* Try again on next call */ 819 urb_listitem->urb = qtd->urb; 820 list_add_tail(&urb_listitem->urb_list, urb_list); 821 } 822 823 list_del(&qtd->qtd_list); 824 qtd_free(qtd); 825 } 826} 827 828#define ENQUEUE_DEPTH 2 829static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) 830{ 831 struct isp1760_hcd *priv = hcd_to_priv(hcd); 832 int ptd_offset; 833 struct isp1760_slotinfo *slots; 834 int curr_slot, free_slot; 835 int n; 836 struct ptd ptd; 837 struct isp1760_qtd *qtd; 838 839 if (unlikely(list_empty(&qh->qtd_list))) { 840 WARN_ON(1); 841 return; 842 } 843 844 /* Make sure this endpoint's TT buffer is clean before queueing ptds */ 845 if (qh->tt_buffer_dirty) 846 return; 847 848 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, 849 qtd_list)->urb->pipe)) { 850 ptd_offset = INT_PTD_OFFSET; 851 slots = priv->int_slots; 852 } else { 853 ptd_offset = ATL_PTD_OFFSET; 854 slots = priv->atl_slots; 855 } 856 857 free_slot = -1; 858 for (curr_slot = 0; curr_slot < 32; curr_slot++) { 859 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) 860 free_slot = curr_slot; 861 if (slots[curr_slot].qh == qh) 862 break; 863 } 864 865 n = 0; 866 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { 867 if (qtd->status == QTD_ENQUEUED) { 868 WARN_ON(qtd->payload_addr); 869 alloc_mem(hcd, qtd); 870 if ((qtd->length) && (!qtd->payload_addr)) 871 break; 872 873 if ((qtd->length) && 874 ((qtd->packet_type == SETUP_PID) || 875 (qtd->packet_type == OUT_PID))) { 876 mem_writes8(hcd->regs, qtd->payload_addr, 877 qtd->data_buffer, qtd->length); 878 } 879 880 qtd->status = QTD_PAYLOAD_ALLOC; 881 } 882 883 if (qtd->status == QTD_PAYLOAD_ALLOC) { 884/* 885 if ((curr_slot > 31) && (free_slot == -1)) 886 dev_dbg(hcd->self.controller, "%s: No slot " 887 "available for transfer\n", __func__); 888*/ 889 /* Start xfer for this endpoint if not already done */ 890 if ((curr_slot > 31) && (free_slot > -1)) { 891 if (usb_pipeint(qtd->urb->pipe)) 892 create_ptd_int(qh, qtd, &ptd); 893 else 894 create_ptd_atl(qh, qtd, &ptd); 895 896 start_bus_transfer(hcd, ptd_offset, free_slot, 897 slots, qtd, qh, &ptd); 898 curr_slot = free_slot; 899 } 900 901 n++; 902 if (n >= ENQUEUE_DEPTH) 903 break; 904 } 905 } 906} 907 908static void schedule_ptds(struct usb_hcd *hcd) 909{ 910 struct isp1760_hcd *priv; 911 struct isp1760_qh *qh, *qh_next; 912 struct list_head *ep_queue; 913 LIST_HEAD(urb_list); 914 struct urb_listitem *urb_listitem, *urb_listitem_next; 915 int i; 916 917 if (!hcd) { 918 WARN_ON(1); 919 return; 920 } 921 922 priv = hcd_to_priv(hcd); 923 924 /* 925 * check finished/retired xfers, transfer payloads, call urb_done() 926 */ 927 for (i = 0; i < QH_END; i++) { 928 ep_queue = &priv->qh_list[i]; 929 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { 930 collect_qtds(hcd, qh, &urb_list); 931 if (list_empty(&qh->qtd_list)) 932 list_del(&qh->qh_list); 933 } 934 } 935 936 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, 937 urb_list) { 938 isp1760_urb_done(hcd, urb_listitem->urb); 939 kmem_cache_free(urb_listitem_cachep, urb_listitem); 940 } 941 942 /* 943 * Schedule packets for transfer. 944 * 945 * According to USB2.0 specification: 946 * 947 * 1st prio: interrupt xfers, up to 80 % of bandwidth 948 * 2nd prio: control xfers 949 * 3rd prio: bulk xfers 950 * 951 * ... but let's use a simpler scheme here (mostly because ISP1761 doc 952 * is very unclear on how to prioritize traffic): 953 * 954 * 1) Enqueue any queued control transfers, as long as payload chip mem 955 * and PTD ATL slots are available. 956 * 2) Enqueue any queued INT transfers, as long as payload chip mem 957 * and PTD INT slots are available. 958 * 3) Enqueue any queued bulk transfers, as long as payload chip mem 959 * and PTD ATL slots are available. 960 * 961 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between 962 * conservation of chip mem and performance. 963 * 964 * I'm sure this scheme could be improved upon! 965 */ 966 for (i = 0; i < QH_END; i++) { 967 ep_queue = &priv->qh_list[i]; 968 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 969 enqueue_qtds(hcd, qh); 970 } 971} 972 973#define PTD_STATE_QTD_DONE 1 974#define PTD_STATE_QTD_RELOAD 2 975#define PTD_STATE_URB_RETIRE 3 976 977static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, 978 struct urb *urb) 979{ 980 __dw dw4; 981 int i; 982 983 dw4 = ptd->dw4; 984 dw4 >>= 8; 985 986 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we 987 need to handle these errors? Is it done in hardware? */ 988 989 if (ptd->dw3 & DW3_HALT_BIT) { 990 991 urb->status = -EPROTO; /* Default unknown error */ 992 993 for (i = 0; i < 8; i++) { 994 switch (dw4 & 0x7) { 995 case INT_UNDERRUN: 996 dev_dbg(hcd->self.controller, "%s: underrun " 997 "during uFrame %d\n", 998 __func__, i); 999 urb->status = -ECOMM; /* Could not write data */ 1000 break; 1001 case INT_EXACT: 1002 dev_dbg(hcd->self.controller, "%s: transaction " 1003 "error during uFrame %d\n", 1004 __func__, i); 1005 urb->status = -EPROTO; /* timeout, bad CRC, PID 1006 error etc. */ 1007 break; 1008 case INT_BABBLE: 1009 dev_dbg(hcd->self.controller, "%s: babble " 1010 "error during uFrame %d\n", 1011 __func__, i); 1012 urb->status = -EOVERFLOW; 1013 break; 1014 } 1015 dw4 >>= 3; 1016 } 1017 1018 return PTD_STATE_URB_RETIRE; 1019 } 1020 1021 return PTD_STATE_QTD_DONE; 1022} 1023 1024static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1025 struct urb *urb) 1026{ 1027 WARN_ON(!ptd); 1028 if (ptd->dw3 & DW3_HALT_BIT) { 1029 if (ptd->dw3 & DW3_BABBLE_BIT) 1030 urb->status = -EOVERFLOW; 1031 else if (FROM_DW3_CERR(ptd->dw3)) 1032 urb->status = -EPIPE; /* Stall */ 1033 else 1034 urb->status = -EPROTO; /* Unknown */ 1035/* 1036 dev_dbg(hcd->self.controller, "%s: ptd error:\n" 1037 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" 1038 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", 1039 __func__, 1040 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, 1041 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); 1042*/ 1043 return PTD_STATE_URB_RETIRE; 1044 } 1045 1046 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1047 /* Transfer Error, *but* active and no HALT -> reload */ 1048 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); 1049 return PTD_STATE_QTD_RELOAD; 1050 } 1051 1052 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1053 /* 1054 * NAKs are handled in HW by the chip. Usually if the 1055 * device is not able to send data fast enough. 1056 * This happens mostly on slower hardware. 1057 */ 1058 return PTD_STATE_QTD_RELOAD; 1059 } 1060 1061 return PTD_STATE_QTD_DONE; 1062} 1063 1064static void handle_done_ptds(struct usb_hcd *hcd) 1065{ 1066 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1067 struct ptd ptd; 1068 struct isp1760_qh *qh; 1069 int slot; 1070 int state; 1071 struct isp1760_slotinfo *slots; 1072 u32 ptd_offset; 1073 struct isp1760_qtd *qtd; 1074 int modified; 1075 int skip_map; 1076 1077 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1078 priv->int_done_map &= ~skip_map; 1079 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1080 priv->atl_done_map &= ~skip_map; 1081 1082 modified = priv->int_done_map || priv->atl_done_map; 1083 1084 while (priv->int_done_map || priv->atl_done_map) { 1085 if (priv->int_done_map) { 1086 /* INT ptd */ 1087 slot = __ffs(priv->int_done_map); 1088 priv->int_done_map &= ~(1 << slot); 1089 slots = priv->int_slots; 1090 /* This should not trigger, and could be removed if 1091 noone have any problems with it triggering: */ 1092 if (!slots[slot].qh) { 1093 WARN_ON(1); 1094 continue; 1095 } 1096 ptd_offset = INT_PTD_OFFSET; 1097 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); 1098 state = check_int_transfer(hcd, &ptd, 1099 slots[slot].qtd->urb); 1100 } else { 1101 /* ATL ptd */ 1102 slot = __ffs(priv->atl_done_map); 1103 priv->atl_done_map &= ~(1 << slot); 1104 slots = priv->atl_slots; 1105 /* This should not trigger, and could be removed if 1106 noone have any problems with it triggering: */ 1107 if (!slots[slot].qh) { 1108 WARN_ON(1); 1109 continue; 1110 } 1111 ptd_offset = ATL_PTD_OFFSET; 1112 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1113 state = check_atl_transfer(hcd, &ptd, 1114 slots[slot].qtd->urb); 1115 } 1116 1117 qtd = slots[slot].qtd; 1118 slots[slot].qtd = NULL; 1119 qh = slots[slot].qh; 1120 slots[slot].qh = NULL; 1121 qh->slot = -1; 1122 1123 WARN_ON(qtd->status != QTD_XFER_STARTED); 1124 1125 switch (state) { 1126 case PTD_STATE_QTD_DONE: 1127 if ((usb_pipeint(qtd->urb->pipe)) && 1128 (qtd->urb->dev->speed != USB_SPEED_HIGH)) 1129 qtd->actual_length = 1130 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); 1131 else 1132 qtd->actual_length = 1133 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); 1134 1135 qtd->status = QTD_XFER_COMPLETE; 1136 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || 1137 is_short_bulk(qtd)) 1138 qtd = NULL; 1139 else 1140 qtd = list_entry(qtd->qtd_list.next, 1141 typeof(*qtd), qtd_list); 1142 1143 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1144 qh->ping = FROM_DW3_PING(ptd.dw3); 1145 break; 1146 1147 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ 1148 qtd->status = QTD_PAYLOAD_ALLOC; 1149 ptd.dw0 |= DW0_VALID_BIT; 1150 /* RL counter = ERR counter */ 1151 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); 1152 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); 1153 ptd.dw3 &= ~TO_DW3_CERR(3); 1154 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); 1155 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1156 qh->ping = FROM_DW3_PING(ptd.dw3); 1157 break; 1158 1159 case PTD_STATE_URB_RETIRE: 1160 qtd->status = QTD_RETIRE; 1161 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && 1162 (qtd->urb->status != -EPIPE) && 1163 (qtd->urb->status != -EREMOTEIO)) { 1164 qh->tt_buffer_dirty = 1; 1165 if (usb_hub_clear_tt_buffer(qtd->urb)) 1166 /* Clear failed; let's hope things work 1167 anyway */ 1168 qh->tt_buffer_dirty = 0; 1169 } 1170 qtd = NULL; 1171 qh->toggle = 0; 1172 qh->ping = 0; 1173 break; 1174 1175 default: 1176 WARN_ON(1); 1177 continue; 1178 } 1179 1180 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { 1181 if (slots == priv->int_slots) { 1182 if (state == PTD_STATE_QTD_RELOAD) 1183 dev_err(hcd->self.controller, 1184 "%s: PTD_STATE_QTD_RELOAD on " 1185 "interrupt packet\n", __func__); 1186 if (state != PTD_STATE_QTD_RELOAD) 1187 create_ptd_int(qh, qtd, &ptd); 1188 } else { 1189 if (state != PTD_STATE_QTD_RELOAD) 1190 create_ptd_atl(qh, qtd, &ptd); 1191 } 1192 1193 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, 1194 qh, &ptd); 1195 } 1196 } 1197 1198 if (modified) 1199 schedule_ptds(hcd); 1200} 1201 1202static irqreturn_t isp1760_irq(struct usb_hcd *hcd) 1203{ 1204 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1205 u32 imask; 1206 irqreturn_t irqret = IRQ_NONE; 1207 1208 spin_lock(&priv->lock); 1209 1210 if (!(hcd->state & HC_STATE_RUNNING)) 1211 goto leave; 1212 1213 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); 1214 if (unlikely(!imask)) 1215 goto leave; 1216 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ 1217 1218 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); 1219 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); 1220 1221 handle_done_ptds(hcd); 1222 1223 irqret = IRQ_HANDLED; 1224leave: 1225 spin_unlock(&priv->lock); 1226 1227 return irqret; 1228} 1229 1230/* 1231 * Workaround for problem described in chip errata 2: 1232 * 1233 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. 1234 * One solution suggested in the errata is to use SOF interrupts _instead_of_ 1235 * ATL done interrupts (the "instead of" might be important since it seems 1236 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" 1237 * to set the PTD's done bit in addition to not generating an interrupt!). 1238 * 1239 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their 1240 * done bit is not being set. This is bad - it blocks the endpoint until reboot. 1241 * 1242 * If we use SOF interrupts only, we get latency between ptd completion and the 1243 * actual handling. This is very noticeable in testusb runs which takes several 1244 * minutes longer without ATL interrupts. 1245 * 1246 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it 1247 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the 1248 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered 1249 * completed and its done map bit is set. 1250 * 1251 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen 1252 * not to cause too much lag when this HW bug occurs, while still hopefully 1253 * ensuring that the check does not falsely trigger. 1254 */ 1255#define SLOT_TIMEOUT 300 1256#define SLOT_CHECK_PERIOD 200 1257static struct timer_list errata2_timer; 1258static struct usb_hcd *errata2_timer_hcd; 1259 1260static void errata2_function(struct timer_list *unused) 1261{ 1262 struct usb_hcd *hcd = errata2_timer_hcd; 1263 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1264 int slot; 1265 struct ptd ptd; 1266 unsigned long spinflags; 1267 1268 spin_lock_irqsave(&priv->lock, spinflags); 1269 1270 for (slot = 0; slot < 32; slot++) 1271 if (priv->atl_slots[slot].qh && time_after(jiffies, 1272 priv->atl_slots[slot].timestamp + 1273 msecs_to_jiffies(SLOT_TIMEOUT))) { 1274 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1275 if (!FROM_DW0_VALID(ptd.dw0) && 1276 !FROM_DW3_ACTIVE(ptd.dw3)) 1277 priv->atl_done_map |= 1 << slot; 1278 } 1279 1280 if (priv->atl_done_map) 1281 handle_done_ptds(hcd); 1282 1283 spin_unlock_irqrestore(&priv->lock, spinflags); 1284 1285 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1286 add_timer(&errata2_timer); 1287} 1288 1289static int isp1760_run(struct usb_hcd *hcd) 1290{ 1291 int retval; 1292 u32 temp; 1293 u32 command; 1294 u32 chipid; 1295 1296 hcd->uses_new_polling = 1; 1297 1298 hcd->state = HC_STATE_RUNNING; 1299 1300 /* Set PTD interrupt AND & OR maps */ 1301 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); 1302 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); 1303 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); 1304 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); 1305 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); 1306 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); 1307 /* step 23 passed */ 1308 1309 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 1310 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); 1311 1312 command = reg_read32(hcd->regs, HC_USBCMD); 1313 command &= ~(CMD_LRESET|CMD_RESET); 1314 command |= CMD_RUN; 1315 reg_write32(hcd->regs, HC_USBCMD, command); 1316 1317 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); 1318 if (retval) 1319 return retval; 1320 1321 /* 1322 * XXX 1323 * Spec says to write FLAG_CF as last config action, priv code grabs 1324 * the semaphore while doing so. 1325 */ 1326 down_write(&ehci_cf_port_reset_rwsem); 1327 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); 1328 1329 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); 1330 up_write(&ehci_cf_port_reset_rwsem); 1331 if (retval) 1332 return retval; 1333 1334 errata2_timer_hcd = hcd; 1335 timer_setup(&errata2_timer, errata2_function, 0); 1336 errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); 1337 add_timer(&errata2_timer); 1338 1339 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); 1340 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", 1341 chipid & 0xffff, chipid >> 16); 1342 1343 /* PTD Register Init Part 2, Step 28 */ 1344 1345 /* Setup registers controlling PTD checking */ 1346 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); 1347 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); 1348 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); 1349 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); 1350 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); 1351 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); 1352 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 1353 ATL_BUF_FILL | INT_BUF_FILL); 1354 1355 /* GRR this is run-once init(), being done every time the HC starts. 1356 * So long as they're part of class devices, we can't do it init() 1357 * since the class device isn't created that early. 1358 */ 1359 return 0; 1360} 1361 1362static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) 1363{ 1364 qtd->data_buffer = databuffer; 1365 1366 if (len > MAX_PAYLOAD_SIZE) 1367 len = MAX_PAYLOAD_SIZE; 1368 qtd->length = len; 1369 1370 return qtd->length; 1371} 1372 1373static void qtd_list_free(struct list_head *qtd_list) 1374{ 1375 struct isp1760_qtd *qtd, *qtd_next; 1376 1377 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { 1378 list_del(&qtd->qtd_list); 1379 qtd_free(qtd); 1380 } 1381} 1382 1383/* 1384 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. 1385 * Also calculate the PID type (SETUP/IN/OUT) for each packet. 1386 */ 1387#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1388static void packetize_urb(struct usb_hcd *hcd, 1389 struct urb *urb, struct list_head *head, gfp_t flags) 1390{ 1391 struct isp1760_qtd *qtd; 1392 void *buf; 1393 int len, maxpacketsize; 1394 u8 packet_type; 1395 1396 /* 1397 * URBs map to sequences of QTDs: one logical transaction 1398 */ 1399 1400 if (!urb->transfer_buffer && urb->transfer_buffer_length) { 1401 /* XXX This looks like usb storage / SCSI bug */ 1402 dev_err(hcd->self.controller, 1403 "buf is null, dma is %08lx len is %d\n", 1404 (long unsigned)urb->transfer_dma, 1405 urb->transfer_buffer_length); 1406 WARN_ON(1); 1407 } 1408 1409 if (usb_pipein(urb->pipe)) 1410 packet_type = IN_PID; 1411 else 1412 packet_type = OUT_PID; 1413 1414 if (usb_pipecontrol(urb->pipe)) { 1415 qtd = qtd_alloc(flags, urb, SETUP_PID); 1416 if (!qtd) 1417 goto cleanup; 1418 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); 1419 list_add_tail(&qtd->qtd_list, head); 1420 1421 /* for zero length DATA stages, STATUS is always IN */ 1422 if (urb->transfer_buffer_length == 0) 1423 packet_type = IN_PID; 1424 } 1425 1426 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, 1427 usb_pipeout(urb->pipe))); 1428 1429 /* 1430 * buffer gets wrapped in one or more qtds; 1431 * last one may be "short" (including zero len) 1432 * and may serve as a control status ack 1433 */ 1434 buf = urb->transfer_buffer; 1435 len = urb->transfer_buffer_length; 1436 1437 for (;;) { 1438 int this_qtd_len; 1439 1440 qtd = qtd_alloc(flags, urb, packet_type); 1441 if (!qtd) 1442 goto cleanup; 1443 this_qtd_len = qtd_fill(qtd, buf, len); 1444 list_add_tail(&qtd->qtd_list, head); 1445 1446 len -= this_qtd_len; 1447 buf += this_qtd_len; 1448 1449 if (len <= 0) 1450 break; 1451 } 1452 1453 /* 1454 * control requests may need a terminating data "status" ack; 1455 * bulk ones may need a terminating short packet (zero length). 1456 */ 1457 if (urb->transfer_buffer_length != 0) { 1458 int one_more = 0; 1459 1460 if (usb_pipecontrol(urb->pipe)) { 1461 one_more = 1; 1462 if (packet_type == IN_PID) 1463 packet_type = OUT_PID; 1464 else 1465 packet_type = IN_PID; 1466 } else if (usb_pipebulk(urb->pipe) 1467 && (urb->transfer_flags & URB_ZERO_PACKET) 1468 && !(urb->transfer_buffer_length % 1469 maxpacketsize)) { 1470 one_more = 1; 1471 } 1472 if (one_more) { 1473 qtd = qtd_alloc(flags, urb, packet_type); 1474 if (!qtd) 1475 goto cleanup; 1476 1477 /* never any data in such packets */ 1478 qtd_fill(qtd, NULL, 0); 1479 list_add_tail(&qtd->qtd_list, head); 1480 } 1481 } 1482 1483 return; 1484 1485cleanup: 1486 qtd_list_free(head); 1487} 1488 1489static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1490 gfp_t mem_flags) 1491{ 1492 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1493 struct list_head *ep_queue; 1494 struct isp1760_qh *qh, *qhit; 1495 unsigned long spinflags; 1496 LIST_HEAD(new_qtds); 1497 int retval; 1498 int qh_in_queue; 1499 1500 switch (usb_pipetype(urb->pipe)) { 1501 case PIPE_CONTROL: 1502 ep_queue = &priv->qh_list[QH_CONTROL]; 1503 break; 1504 case PIPE_BULK: 1505 ep_queue = &priv->qh_list[QH_BULK]; 1506 break; 1507 case PIPE_INTERRUPT: 1508 if (urb->interval < 0) 1509 return -EINVAL; 1510 /* FIXME: Check bandwidth */ 1511 ep_queue = &priv->qh_list[QH_INTERRUPT]; 1512 break; 1513 case PIPE_ISOCHRONOUS: 1514 dev_err(hcd->self.controller, "%s: isochronous USB packets " 1515 "not yet supported\n", 1516 __func__); 1517 return -EPIPE; 1518 default: 1519 dev_err(hcd->self.controller, "%s: unknown pipe type\n", 1520 __func__); 1521 return -EPIPE; 1522 } 1523 1524 if (usb_pipein(urb->pipe)) 1525 urb->actual_length = 0; 1526 1527 packetize_urb(hcd, urb, &new_qtds, mem_flags); 1528 if (list_empty(&new_qtds)) 1529 return -ENOMEM; 1530 1531 retval = 0; 1532 spin_lock_irqsave(&priv->lock, spinflags); 1533 1534 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 1535 retval = -ESHUTDOWN; 1536 qtd_list_free(&new_qtds); 1537 goto out; 1538 } 1539 retval = usb_hcd_link_urb_to_ep(hcd, urb); 1540 if (retval) { 1541 qtd_list_free(&new_qtds); 1542 goto out; 1543 } 1544 1545 qh = urb->ep->hcpriv; 1546 if (qh) { 1547 qh_in_queue = 0; 1548 list_for_each_entry(qhit, ep_queue, qh_list) { 1549 if (qhit == qh) { 1550 qh_in_queue = 1; 1551 break; 1552 } 1553 } 1554 if (!qh_in_queue) 1555 list_add_tail(&qh->qh_list, ep_queue); 1556 } else { 1557 qh = qh_alloc(GFP_ATOMIC); 1558 if (!qh) { 1559 retval = -ENOMEM; 1560 usb_hcd_unlink_urb_from_ep(hcd, urb); 1561 qtd_list_free(&new_qtds); 1562 goto out; 1563 } 1564 list_add_tail(&qh->qh_list, ep_queue); 1565 urb->ep->hcpriv = qh; 1566 } 1567 1568 list_splice_tail(&new_qtds, &qh->qtd_list); 1569 schedule_ptds(hcd); 1570 1571out: 1572 spin_unlock_irqrestore(&priv->lock, spinflags); 1573 return retval; 1574} 1575 1576static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, 1577 struct isp1760_qh *qh) 1578{ 1579 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1580 int skip_map; 1581 1582 WARN_ON(qh->slot == -1); 1583 1584 /* We need to forcefully reclaim the slot since some transfers never 1585 return, e.g. interrupt transfers and NAKed bulk transfers. */ 1586 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { 1587 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1588 skip_map |= (1 << qh->slot); 1589 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 1590 priv->atl_slots[qh->slot].qh = NULL; 1591 priv->atl_slots[qh->slot].qtd = NULL; 1592 } else { 1593 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1594 skip_map |= (1 << qh->slot); 1595 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 1596 priv->int_slots[qh->slot].qh = NULL; 1597 priv->int_slots[qh->slot].qtd = NULL; 1598 } 1599 1600 qh->slot = -1; 1601} 1602 1603/* 1604 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing 1605 * any active transfer belonging to the urb in the process. 1606 */ 1607static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, 1608 struct isp1760_qtd *qtd) 1609{ 1610 struct urb *urb; 1611 int urb_was_running; 1612 1613 urb = qtd->urb; 1614 urb_was_running = 0; 1615 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { 1616 if (qtd->urb != urb) 1617 break; 1618 1619 if (qtd->status >= QTD_XFER_STARTED) 1620 urb_was_running = 1; 1621 if (last_qtd_of_urb(qtd, qh) && 1622 (qtd->status >= QTD_XFER_COMPLETE)) 1623 urb_was_running = 0; 1624 1625 if (qtd->status == QTD_XFER_STARTED) 1626 kill_transfer(hcd, urb, qh); 1627 qtd->status = QTD_RETIRE; 1628 } 1629 1630 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { 1631 qh->tt_buffer_dirty = 1; 1632 if (usb_hub_clear_tt_buffer(urb)) 1633 /* Clear failed; let's hope things work anyway */ 1634 qh->tt_buffer_dirty = 0; 1635 } 1636} 1637 1638static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 1639 int status) 1640{ 1641 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1642 unsigned long spinflags; 1643 struct isp1760_qh *qh; 1644 struct isp1760_qtd *qtd; 1645 int retval = 0; 1646 1647 spin_lock_irqsave(&priv->lock, spinflags); 1648 retval = usb_hcd_check_unlink_urb(hcd, urb, status); 1649 if (retval) 1650 goto out; 1651 1652 qh = urb->ep->hcpriv; 1653 if (!qh) { 1654 retval = -EINVAL; 1655 goto out; 1656 } 1657 1658 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) 1659 if (qtd->urb == urb) { 1660 dequeue_urb_from_qtd(hcd, qh, qtd); 1661 list_move(&qtd->qtd_list, &qh->qtd_list); 1662 break; 1663 } 1664 1665 urb->status = status; 1666 schedule_ptds(hcd); 1667 1668out: 1669 spin_unlock_irqrestore(&priv->lock, spinflags); 1670 return retval; 1671} 1672 1673static void isp1760_endpoint_disable(struct usb_hcd *hcd, 1674 struct usb_host_endpoint *ep) 1675{ 1676 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1677 unsigned long spinflags; 1678 struct isp1760_qh *qh, *qh_iter; 1679 int i; 1680 1681 spin_lock_irqsave(&priv->lock, spinflags); 1682 1683 qh = ep->hcpriv; 1684 if (!qh) 1685 goto out; 1686 1687 WARN_ON(!list_empty(&qh->qtd_list)); 1688 1689 for (i = 0; i < QH_END; i++) 1690 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) 1691 if (qh_iter == qh) { 1692 list_del(&qh_iter->qh_list); 1693 i = QH_END; 1694 break; 1695 } 1696 qh_free(qh); 1697 ep->hcpriv = NULL; 1698 1699 schedule_ptds(hcd); 1700 1701out: 1702 spin_unlock_irqrestore(&priv->lock, spinflags); 1703} 1704 1705static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) 1706{ 1707 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1708 u32 temp, status = 0; 1709 u32 mask; 1710 int retval = 1; 1711 unsigned long flags; 1712 1713 /* if !PM, root hub timers won't get shut down ... */ 1714 if (!HC_IS_RUNNING(hcd->state)) 1715 return 0; 1716 1717 /* init status to no-changes */ 1718 buf[0] = 0; 1719 mask = PORT_CSC; 1720 1721 spin_lock_irqsave(&priv->lock, flags); 1722 temp = reg_read32(hcd->regs, HC_PORTSC1); 1723 1724 if (temp & PORT_OWNER) { 1725 if (temp & PORT_CSC) { 1726 temp &= ~PORT_CSC; 1727 reg_write32(hcd->regs, HC_PORTSC1, temp); 1728 goto done; 1729 } 1730 } 1731 1732 /* 1733 * Return status information even for ports with OWNER set. 1734 * Otherwise hub_wq wouldn't see the disconnect event when a 1735 * high-speed device is switched over to the companion 1736 * controller by the user. 1737 */ 1738 1739 if ((temp & mask) != 0 1740 || ((temp & PORT_RESUME) != 0 1741 && time_after_eq(jiffies, 1742 priv->reset_done))) { 1743 buf [0] |= 1 << (0 + 1); 1744 status = STS_PCD; 1745 } 1746 /* FIXME autosuspend idle root hubs */ 1747done: 1748 spin_unlock_irqrestore(&priv->lock, flags); 1749 return status ? retval : 0; 1750} 1751 1752static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 1753 struct usb_hub_descriptor *desc) 1754{ 1755 int ports = HCS_N_PORTS(priv->hcs_params); 1756 u16 temp; 1757 1758 desc->bDescriptorType = USB_DT_HUB; 1759 /* priv 1.0, 2.3.9 says 20ms max */ 1760 desc->bPwrOn2PwrGood = 10; 1761 desc->bHubContrCurrent = 0; 1762 1763 desc->bNbrPorts = ports; 1764 temp = 1 + (ports / 8); 1765 desc->bDescLength = 7 + 2 * temp; 1766 1767 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 1768 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 1769 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 1770 1771 /* per-port overcurrent reporting */ 1772 temp = HUB_CHAR_INDV_PORT_OCPM; 1773 if (HCS_PPC(priv->hcs_params)) 1774 /* per-port power control */ 1775 temp |= HUB_CHAR_INDV_PORT_LPSM; 1776 else 1777 /* no power switching */ 1778 temp |= HUB_CHAR_NO_LPSM; 1779 desc->wHubCharacteristics = cpu_to_le16(temp); 1780} 1781 1782#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 1783 1784static int check_reset_complete(struct usb_hcd *hcd, int index, 1785 int port_status) 1786{ 1787 if (!(port_status & PORT_CONNECT)) 1788 return port_status; 1789 1790 /* if reset finished and it's still not enabled -- handoff */ 1791 if (!(port_status & PORT_PE)) { 1792 1793 dev_info(hcd->self.controller, 1794 "port %d full speed --> companion\n", 1795 index + 1); 1796 1797 port_status |= PORT_OWNER; 1798 port_status &= ~PORT_RWC_BITS; 1799 reg_write32(hcd->regs, HC_PORTSC1, port_status); 1800 1801 } else 1802 dev_info(hcd->self.controller, "port %d high speed\n", 1803 index + 1); 1804 1805 return port_status; 1806} 1807 1808static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, 1809 u16 wValue, u16 wIndex, char *buf, u16 wLength) 1810{ 1811 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1812 int ports = HCS_N_PORTS(priv->hcs_params); 1813 u32 temp, status; 1814 unsigned long flags; 1815 int retval = 0; 1816 1817 /* 1818 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 1819 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 1820 * (track current state ourselves) ... blink for diagnostics, 1821 * power, "this is the one", etc. EHCI spec supports this. 1822 */ 1823 1824 spin_lock_irqsave(&priv->lock, flags); 1825 switch (typeReq) { 1826 case ClearHubFeature: 1827 switch (wValue) { 1828 case C_HUB_LOCAL_POWER: 1829 case C_HUB_OVER_CURRENT: 1830 /* no hub-wide feature/status flags */ 1831 break; 1832 default: 1833 goto error; 1834 } 1835 break; 1836 case ClearPortFeature: 1837 if (!wIndex || wIndex > ports) 1838 goto error; 1839 wIndex--; 1840 temp = reg_read32(hcd->regs, HC_PORTSC1); 1841 1842 /* 1843 * Even if OWNER is set, so the port is owned by the 1844 * companion controller, hub_wq needs to be able to clear 1845 * the port-change status bits (especially 1846 * USB_PORT_STAT_C_CONNECTION). 1847 */ 1848 1849 switch (wValue) { 1850 case USB_PORT_FEAT_ENABLE: 1851 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); 1852 break; 1853 case USB_PORT_FEAT_C_ENABLE: 1854 /* XXX error? */ 1855 break; 1856 case USB_PORT_FEAT_SUSPEND: 1857 if (temp & PORT_RESET) 1858 goto error; 1859 1860 if (temp & PORT_SUSPEND) { 1861 if ((temp & PORT_PE) == 0) 1862 goto error; 1863 /* resume signaling for 20 msec */ 1864 temp &= ~(PORT_RWC_BITS); 1865 reg_write32(hcd->regs, HC_PORTSC1, 1866 temp | PORT_RESUME); 1867 priv->reset_done = jiffies + 1868 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1869 } 1870 break; 1871 case USB_PORT_FEAT_C_SUSPEND: 1872 /* we auto-clear this feature */ 1873 break; 1874 case USB_PORT_FEAT_POWER: 1875 if (HCS_PPC(priv->hcs_params)) 1876 reg_write32(hcd->regs, HC_PORTSC1, 1877 temp & ~PORT_POWER); 1878 break; 1879 case USB_PORT_FEAT_C_CONNECTION: 1880 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); 1881 break; 1882 case USB_PORT_FEAT_C_OVER_CURRENT: 1883 /* XXX error ?*/ 1884 break; 1885 case USB_PORT_FEAT_C_RESET: 1886 /* GetPortStatus clears reset */ 1887 break; 1888 default: 1889 goto error; 1890 } 1891 reg_read32(hcd->regs, HC_USBCMD); 1892 break; 1893 case GetHubDescriptor: 1894 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 1895 buf); 1896 break; 1897 case GetHubStatus: 1898 /* no hub-wide feature/status flags */ 1899 memset(buf, 0, 4); 1900 break; 1901 case GetPortStatus: 1902 if (!wIndex || wIndex > ports) 1903 goto error; 1904 wIndex--; 1905 status = 0; 1906 temp = reg_read32(hcd->regs, HC_PORTSC1); 1907 1908 /* wPortChange bits */ 1909 if (temp & PORT_CSC) 1910 status |= USB_PORT_STAT_C_CONNECTION << 16; 1911 1912 1913 /* whoever resumes must GetPortStatus to complete it!! */ 1914 if (temp & PORT_RESUME) { 1915 dev_err(hcd->self.controller, "Port resume should be skipped.\n"); 1916 1917 /* Remote Wakeup received? */ 1918 if (!priv->reset_done) { 1919 /* resume signaling for 20 msec */ 1920 priv->reset_done = jiffies 1921 + msecs_to_jiffies(20); 1922 /* check the port again */ 1923 mod_timer(&hcd->rh_timer, priv->reset_done); 1924 } 1925 1926 /* resume completed? */ 1927 else if (time_after_eq(jiffies, 1928 priv->reset_done)) { 1929 status |= USB_PORT_STAT_C_SUSPEND << 16; 1930 priv->reset_done = 0; 1931 1932 /* stop resume signaling */ 1933 temp = reg_read32(hcd->regs, HC_PORTSC1); 1934 reg_write32(hcd->regs, HC_PORTSC1, 1935 temp & ~(PORT_RWC_BITS | PORT_RESUME)); 1936 retval = handshake(hcd, HC_PORTSC1, 1937 PORT_RESUME, 0, 2000 /* 2msec */); 1938 if (retval != 0) { 1939 dev_err(hcd->self.controller, 1940 "port %d resume error %d\n", 1941 wIndex + 1, retval); 1942 goto error; 1943 } 1944 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); 1945 } 1946 } 1947 1948 /* whoever resets must GetPortStatus to complete it!! */ 1949 if ((temp & PORT_RESET) 1950 && time_after_eq(jiffies, 1951 priv->reset_done)) { 1952 status |= USB_PORT_STAT_C_RESET << 16; 1953 priv->reset_done = 0; 1954 1955 /* force reset to complete */ 1956 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); 1957 /* REVISIT: some hardware needs 550+ usec to clear 1958 * this bit; seems too long to spin routinely... 1959 */ 1960 retval = handshake(hcd, HC_PORTSC1, 1961 PORT_RESET, 0, 750); 1962 if (retval != 0) { 1963 dev_err(hcd->self.controller, "port %d reset error %d\n", 1964 wIndex + 1, retval); 1965 goto error; 1966 } 1967 1968 /* see what we found out */ 1969 temp = check_reset_complete(hcd, wIndex, 1970 reg_read32(hcd->regs, HC_PORTSC1)); 1971 } 1972 /* 1973 * Even if OWNER is set, there's no harm letting hub_wq 1974 * see the wPortStatus values (they should all be 0 except 1975 * for PORT_POWER anyway). 1976 */ 1977 1978 if (temp & PORT_OWNER) 1979 dev_err(hcd->self.controller, "PORT_OWNER is set\n"); 1980 1981 if (temp & PORT_CONNECT) { 1982 status |= USB_PORT_STAT_CONNECTION; 1983 /* status may be from integrated TT */ 1984 status |= USB_PORT_STAT_HIGH_SPEED; 1985 } 1986 if (temp & PORT_PE) 1987 status |= USB_PORT_STAT_ENABLE; 1988 if (temp & (PORT_SUSPEND|PORT_RESUME)) 1989 status |= USB_PORT_STAT_SUSPEND; 1990 if (temp & PORT_RESET) 1991 status |= USB_PORT_STAT_RESET; 1992 if (temp & PORT_POWER) 1993 status |= USB_PORT_STAT_POWER; 1994 1995 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 1996 break; 1997 case SetHubFeature: 1998 switch (wValue) { 1999 case C_HUB_LOCAL_POWER: 2000 case C_HUB_OVER_CURRENT: 2001 /* no hub-wide feature/status flags */ 2002 break; 2003 default: 2004 goto error; 2005 } 2006 break; 2007 case SetPortFeature: 2008 wIndex &= 0xff; 2009 if (!wIndex || wIndex > ports) 2010 goto error; 2011 wIndex--; 2012 temp = reg_read32(hcd->regs, HC_PORTSC1); 2013 if (temp & PORT_OWNER) 2014 break; 2015 2016/* temp &= ~PORT_RWC_BITS; */ 2017 switch (wValue) { 2018 case USB_PORT_FEAT_ENABLE: 2019 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); 2020 break; 2021 2022 case USB_PORT_FEAT_SUSPEND: 2023 if ((temp & PORT_PE) == 0 2024 || (temp & PORT_RESET) != 0) 2025 goto error; 2026 2027 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); 2028 break; 2029 case USB_PORT_FEAT_POWER: 2030 if (HCS_PPC(priv->hcs_params)) 2031 reg_write32(hcd->regs, HC_PORTSC1, 2032 temp | PORT_POWER); 2033 break; 2034 case USB_PORT_FEAT_RESET: 2035 if (temp & PORT_RESUME) 2036 goto error; 2037 /* line status bits may report this as low speed, 2038 * which can be fine if this root hub has a 2039 * transaction translator built in. 2040 */ 2041 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT 2042 && PORT_USB11(temp)) { 2043 temp |= PORT_OWNER; 2044 } else { 2045 temp |= PORT_RESET; 2046 temp &= ~PORT_PE; 2047 2048 /* 2049 * caller must wait, then call GetPortStatus 2050 * usb 2.0 spec says 50 ms resets on root 2051 */ 2052 priv->reset_done = jiffies + 2053 msecs_to_jiffies(50); 2054 } 2055 reg_write32(hcd->regs, HC_PORTSC1, temp); 2056 break; 2057 default: 2058 goto error; 2059 } 2060 reg_read32(hcd->regs, HC_USBCMD); 2061 break; 2062 2063 default: 2064error: 2065 /* "stall" on error */ 2066 retval = -EPIPE; 2067 } 2068 spin_unlock_irqrestore(&priv->lock, flags); 2069 return retval; 2070} 2071 2072static int isp1760_get_frame(struct usb_hcd *hcd) 2073{ 2074 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2075 u32 fr; 2076 2077 fr = reg_read32(hcd->regs, HC_FRINDEX); 2078 return (fr >> 3) % priv->periodic_size; 2079} 2080 2081static void isp1760_stop(struct usb_hcd *hcd) 2082{ 2083 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2084 u32 temp; 2085 2086 del_timer(&errata2_timer); 2087 2088 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, 2089 NULL, 0); 2090 msleep(20); 2091 2092 spin_lock_irq(&priv->lock); 2093 ehci_reset(hcd); 2094 /* Disable IRQ */ 2095 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2096 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2097 spin_unlock_irq(&priv->lock); 2098 2099 reg_write32(hcd->regs, HC_CONFIGFLAG, 0); 2100} 2101 2102static void isp1760_shutdown(struct usb_hcd *hcd) 2103{ 2104 u32 command, temp; 2105 2106 isp1760_stop(hcd); 2107 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2108 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2109 2110 command = reg_read32(hcd->regs, HC_USBCMD); 2111 command &= ~CMD_RUN; 2112 reg_write32(hcd->regs, HC_USBCMD, command); 2113} 2114 2115static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, 2116 struct usb_host_endpoint *ep) 2117{ 2118 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2119 struct isp1760_qh *qh = ep->hcpriv; 2120 unsigned long spinflags; 2121 2122 if (!qh) 2123 return; 2124 2125 spin_lock_irqsave(&priv->lock, spinflags); 2126 qh->tt_buffer_dirty = 0; 2127 schedule_ptds(hcd); 2128 spin_unlock_irqrestore(&priv->lock, spinflags); 2129} 2130 2131 2132static const struct hc_driver isp1760_hc_driver = { 2133 .description = "isp1760-hcd", 2134 .product_desc = "NXP ISP1760 USB Host Controller", 2135 .hcd_priv_size = sizeof(struct isp1760_hcd *), 2136 .irq = isp1760_irq, 2137 .flags = HCD_MEMORY | HCD_USB2, 2138 .reset = isp1760_hc_setup, 2139 .start = isp1760_run, 2140 .stop = isp1760_stop, 2141 .shutdown = isp1760_shutdown, 2142 .urb_enqueue = isp1760_urb_enqueue, 2143 .urb_dequeue = isp1760_urb_dequeue, 2144 .endpoint_disable = isp1760_endpoint_disable, 2145 .get_frame_number = isp1760_get_frame, 2146 .hub_status_data = isp1760_hub_status_data, 2147 .hub_control = isp1760_hub_control, 2148 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, 2149}; 2150 2151int __init isp1760_init_kmem_once(void) 2152{ 2153 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", 2154 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | 2155 SLAB_MEM_SPREAD, NULL); 2156 2157 if (!urb_listitem_cachep) 2158 return -ENOMEM; 2159 2160 qtd_cachep = kmem_cache_create("isp1760_qtd", 2161 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | 2162 SLAB_MEM_SPREAD, NULL); 2163 2164 if (!qtd_cachep) 2165 return -ENOMEM; 2166 2167 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2168 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2169 2170 if (!qh_cachep) { 2171 kmem_cache_destroy(qtd_cachep); 2172 return -ENOMEM; 2173 } 2174 2175 return 0; 2176} 2177 2178void isp1760_deinit_kmem_cache(void) 2179{ 2180 kmem_cache_destroy(qtd_cachep); 2181 kmem_cache_destroy(qh_cachep); 2182 kmem_cache_destroy(urb_listitem_cachep); 2183} 2184 2185int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs, 2186 struct resource *mem, int irq, unsigned long irqflags, 2187 struct device *dev) 2188{ 2189 struct usb_hcd *hcd; 2190 int ret; 2191 2192 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); 2193 if (!hcd) 2194 return -ENOMEM; 2195 2196 *(struct isp1760_hcd **)hcd->hcd_priv = priv; 2197 2198 priv->hcd = hcd; 2199 2200 init_memory(priv); 2201 2202 hcd->irq = irq; 2203 hcd->regs = regs; 2204 hcd->rsrc_start = mem->start; 2205 hcd->rsrc_len = resource_size(mem); 2206 2207 /* This driver doesn't support wakeup requests */ 2208 hcd->cant_recv_wakeups = 1; 2209 2210 ret = usb_add_hcd(hcd, irq, irqflags); 2211 if (ret) 2212 goto error; 2213 2214 device_wakeup_enable(hcd->self.controller); 2215 2216 return 0; 2217 2218error: 2219 usb_put_hcd(hcd); 2220 return ret; 2221} 2222 2223void isp1760_hcd_unregister(struct isp1760_hcd *priv) 2224{ 2225 if (!priv->hcd) 2226 return; 2227 2228 usb_remove_hcd(priv->hcd); 2229 usb_put_hcd(priv->hcd); 2230} 2231