1// SPDX-License-Identifier: GPL-2.0 2/* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11#include <linux/pci.h> 12#include <linux/slab.h> 13#include <linux/module.h> 14#include <linux/acpi.h> 15#include <linux/reset.h> 16 17#include "xhci.h" 18#include "xhci-trace.h" 19#include "xhci-pci.h" 20 21#define SSIC_PORT_NUM 2 22#define SSIC_PORT_CFG2 0x880c 23#define SSIC_PORT_CFG2_OFFSET 0x30 24#define PROG_DONE (1 << 30) 25#define SSIC_PORT_UNUSED (1 << 31) 26#define SPARSE_DISABLE_BIT 17 27#define SPARSE_CNTL_ENABLE 0xC12C 28 29/* Device for a quirk */ 30#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 31#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 32#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 35 36#define PCI_VENDOR_ID_ETRON 0x1b6f 37#define PCI_DEVICE_ID_EJ168 0x7023 38 39#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 41#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 42#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 43#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 45#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 46#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 47#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 48#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 49#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 50#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 51#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 52#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 53#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 54#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 55#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 56#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 57#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 58#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af 59#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 60#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 61#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 62#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 63 64#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 65#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 66#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 67#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 68 69#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 70#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 71#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 72#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 73#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 74 75static const char hcd_name[] = "xhci_hcd"; 76 77static struct hc_driver __read_mostly xhci_pci_hc_driver; 78 79static int xhci_pci_setup(struct usb_hcd *hcd); 80static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 81 struct usb_tt *tt, gfp_t mem_flags); 82 83static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 84 .reset = xhci_pci_setup, 85 .update_hub_device = xhci_pci_update_hub_device, 86}; 87 88/* called after powerup, by probe or system-pm "wakeup" */ 89static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 90{ 91 /* 92 * TODO: Implement finding debug ports later. 93 * TODO: see if there are any quirks that need to be added to handle 94 * new extended capabilities. 95 */ 96 97 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 98 if (!pci_set_mwi(pdev)) 99 xhci_dbg(xhci, "MWI active\n"); 100 101 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 102 return 0; 103} 104 105static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 106{ 107 struct pci_dev *pdev = to_pci_dev(dev); 108 struct xhci_driver_data *driver_data; 109 const struct pci_device_id *id; 110 111 id = pci_match_id(pdev->driver->id_table, pdev); 112 113 if (id && id->driver_data) { 114 driver_data = (struct xhci_driver_data *)id->driver_data; 115 xhci->quirks |= driver_data->quirks; 116 } 117 118 /* Look for vendor-specific quirks */ 119 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 120 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 121 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 122 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 123 pdev->revision == 0x0) { 124 xhci->quirks |= XHCI_RESET_EP_QUIRK; 125 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 126 "QUIRK: Fresco Logic xHC needs configure" 127 " endpoint cmd after reset endpoint"); 128 } 129 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 130 pdev->revision == 0x4) { 131 xhci->quirks |= XHCI_SLOW_SUSPEND; 132 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 133 "QUIRK: Fresco Logic xHC revision %u" 134 "must be suspended extra slowly", 135 pdev->revision); 136 } 137 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 138 xhci->quirks |= XHCI_BROKEN_STREAMS; 139 /* Fresco Logic confirms: all revisions of this chip do not 140 * support MSI, even though some of them claim to in their PCI 141 * capabilities. 142 */ 143 xhci->quirks |= XHCI_BROKEN_MSI; 144 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 145 "QUIRK: Fresco Logic revision %u " 146 "has broken MSI implementation", 147 pdev->revision); 148 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 149 } 150 151 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 152 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 153 xhci->quirks |= XHCI_BROKEN_STREAMS; 154 155 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 156 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100) 157 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 158 159 if (pdev->vendor == PCI_VENDOR_ID_NEC) 160 xhci->quirks |= XHCI_NEC_HOST; 161 162 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 163 xhci->quirks |= XHCI_AMD_0x96_HOST; 164 165 /* AMD PLL quirk */ 166 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 167 xhci->quirks |= XHCI_AMD_PLL_FIX; 168 169 if (pdev->vendor == PCI_VENDOR_ID_AMD && 170 (pdev->device == 0x145c || 171 pdev->device == 0x15e0 || 172 pdev->device == 0x15e1 || 173 pdev->device == 0x43bb)) 174 xhci->quirks |= XHCI_SUSPEND_DELAY; 175 176 if (pdev->vendor == PCI_VENDOR_ID_AMD && 177 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 178 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 179 180 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 181 xhci->quirks |= XHCI_DISABLE_SPARSE; 182 xhci->quirks |= XHCI_RESET_ON_RESUME; 183 } 184 185 if (pdev->vendor == PCI_VENDOR_ID_AMD) 186 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 187 188 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 189 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 190 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 191 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 192 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 193 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 194 195 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 196 xhci->quirks |= XHCI_LPM_SUPPORT; 197 xhci->quirks |= XHCI_INTEL_HOST; 198 xhci->quirks |= XHCI_AVOID_BEI; 199 } 200 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 201 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 202 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 203 xhci->limit_active_eps = 64; 204 xhci->quirks |= XHCI_SW_BW_CHECKING; 205 /* 206 * PPT desktop boards DH77EB and DH77DF will power back on after 207 * a few seconds of being shutdown. The fix for this is to 208 * switch the ports from xHCI to EHCI on shutdown. We can't use 209 * DMI information to find those particular boards (since each 210 * vendor will change the board name), so we have to key off all 211 * PPT chipsets. 212 */ 213 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 214 } 215 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 216 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 217 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 218 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 219 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 220 } 221 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 222 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 223 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 224 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 225 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 226 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 227 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 228 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI || 229 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) { 230 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 231 } 232 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 233 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 234 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 235 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 236 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 237 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 238 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) 239 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 240 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 241 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 242 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 243 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 244 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || 245 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) 246 xhci->quirks |= XHCI_MISSING_CAS; 247 248 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 249 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 250 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 251 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 252 253 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 254 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 255 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 256 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 257 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 258 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 259 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 260 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 261 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 262 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 263 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 264 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 265 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 266 267 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 268 pdev->device == PCI_DEVICE_ID_EJ168) { 269 xhci->quirks |= XHCI_RESET_ON_RESUME; 270 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 271 xhci->quirks |= XHCI_BROKEN_STREAMS; 272 } 273 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 274 pdev->device == 0x0014) { 275 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 276 xhci->quirks |= XHCI_ZERO_64B_REGS; 277 xhci->quirks |= XHCI_LWP_QUIRK; 278 } 279 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 280 pdev->device == 0x0015) { 281 xhci->quirks |= XHCI_RESET_ON_RESUME; 282 xhci->quirks |= XHCI_ZERO_64B_REGS; 283 xhci->quirks |= XHCI_LWP_QUIRK; 284 } 285 if (pdev->vendor == PCI_VENDOR_ID_VIA) 286 xhci->quirks |= XHCI_RESET_ON_RESUME; 287 288 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 289 if (pdev->vendor == PCI_VENDOR_ID_VIA && 290 pdev->device == 0x3432) 291 xhci->quirks |= XHCI_BROKEN_STREAMS; 292 293 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 294 xhci->quirks |= XHCI_LPM_SUPPORT; 295 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; 296 } 297 298 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 299 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 300 /* 301 * try to tame the ASMedia 1042 controller which reports 0.96 302 * but appears to behave more like 1.0 303 */ 304 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 305 xhci->quirks |= XHCI_BROKEN_STREAMS; 306 } 307 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 308 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 309 xhci->quirks |= XHCI_TRUST_TX_LENGTH; 310 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 311 } 312 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 313 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 314 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 315 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 316 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 317 318 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 319 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 320 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 321 322 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 323 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 324 325 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 326 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 327 pdev->device == 0x9026) 328 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 329 330 if (pdev->vendor == PCI_VENDOR_ID_AMD && 331 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 332 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 333 xhci->quirks |= XHCI_NO_SOFT_RETRY; 334 335 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 336 xhci->quirks |= XHCI_ZHAOXIN_HOST; 337 338 if (pdev->device == 0x9202) { 339 xhci->quirks |= XHCI_RESET_ON_RESUME; 340 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 341 } 342 343 if (pdev->device == 0x9203) 344 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 345 } 346 347 /* xHC spec requires PCI devices to support D3hot and D3cold */ 348 if (xhci->hci_version >= 0x120) 349 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 350 351 if (xhci->quirks & XHCI_RESET_ON_RESUME) 352 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 353 "QUIRK: Resetting on resume"); 354} 355 356#ifdef CONFIG_ACPI 357static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 358{ 359 static const guid_t intel_dsm_guid = 360 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 361 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 362 union acpi_object *obj; 363 364 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 365 NULL); 366 ACPI_FREE(obj); 367} 368 369static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 370{ 371 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 372 struct xhci_hub *rhub = &xhci->usb3_rhub; 373 int ret; 374 int i; 375 376 /* This is not the usb3 roothub we are looking for */ 377 if (hcd != rhub->hcd) 378 return; 379 380 if (hdev->maxchild > rhub->num_ports) { 381 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 382 return; 383 } 384 385 for (i = 0; i < hdev->maxchild; i++) { 386 ret = usb_acpi_port_lpm_incapable(hdev, i); 387 388 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 389 390 if (ret >= 0) { 391 rhub->ports[i]->lpm_incapable = ret; 392 continue; 393 } 394 } 395} 396 397#else 398static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 399static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 400#endif /* CONFIG_ACPI */ 401 402/* called during probe() after chip reset completes */ 403static int xhci_pci_setup(struct usb_hcd *hcd) 404{ 405 struct xhci_hcd *xhci; 406 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 407 int retval; 408 409 xhci = hcd_to_xhci(hcd); 410 if (!xhci->sbrn) 411 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); 412 413 /* imod_interval is the interrupt moderation value in nanoseconds. */ 414 xhci->imod_interval = 40000; 415 416 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 417 if (retval) 418 return retval; 419 420 if (!usb_hcd_is_primary_hcd(hcd)) 421 return 0; 422 423 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 424 xhci_pme_acpi_rtd3_enable(pdev); 425 426 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); 427 428 /* Find any debug ports */ 429 return xhci_pci_reinit(xhci, pdev); 430} 431 432static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 433 struct usb_tt *tt, gfp_t mem_flags) 434{ 435 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 436 if (!hdev->parent) 437 xhci_find_lpm_incapable_ports(hcd, hdev); 438 439 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 440} 441 442/* 443 * We need to register our own PCI probe function (instead of the USB core's 444 * function) in order to create a second roothub under xHCI. 445 */ 446static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 447{ 448 int retval; 449 struct xhci_hcd *xhci; 450 struct usb_hcd *hcd; 451 struct xhci_driver_data *driver_data; 452 struct reset_control *reset; 453 454 driver_data = (struct xhci_driver_data *)id->driver_data; 455 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { 456 retval = renesas_xhci_check_request_fw(dev, id); 457 if (retval) 458 return retval; 459 } 460 461 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 462 if (IS_ERR(reset)) 463 return PTR_ERR(reset); 464 reset_control_reset(reset); 465 466 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 467 pm_runtime_get_noresume(&dev->dev); 468 469 /* Register the USB 2.0 roothub. 470 * FIXME: USB core must know to register the USB 2.0 roothub first. 471 * This is sort of silly, because we could just set the HCD driver flags 472 * to say USB 2.0, but I'm not sure what the implications would be in 473 * the other parts of the HCD code. 474 */ 475 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); 476 477 if (retval) 478 goto put_runtime_pm; 479 480 /* USB 2.0 roothub is stored in the PCI device now. */ 481 hcd = dev_get_drvdata(&dev->dev); 482 xhci = hcd_to_xhci(hcd); 483 xhci->reset = reset; 484 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 485 pci_name(dev), hcd); 486 if (!xhci->shared_hcd) { 487 retval = -ENOMEM; 488 goto dealloc_usb2_hcd; 489 } 490 491 retval = xhci_ext_cap_init(xhci); 492 if (retval) 493 goto put_usb3_hcd; 494 495 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, 496 IRQF_SHARED); 497 if (retval) 498 goto put_usb3_hcd; 499 /* Roothub already marked as USB 3.0 speed */ 500 501 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && 502 HCC_MAX_PSA(xhci->hcc_params) >= 4) 503 xhci->shared_hcd->can_do_streams = 1; 504 505 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 506 pm_runtime_put_noidle(&dev->dev); 507 508 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 509 pm_runtime_forbid(&dev->dev); 510 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 511 pm_runtime_allow(&dev->dev); 512 513 dma_set_max_seg_size(&dev->dev, UINT_MAX); 514 515 return 0; 516 517put_usb3_hcd: 518 usb_put_hcd(xhci->shared_hcd); 519dealloc_usb2_hcd: 520 usb_hcd_pci_remove(dev); 521put_runtime_pm: 522 pm_runtime_put_noidle(&dev->dev); 523 return retval; 524} 525 526static void xhci_pci_remove(struct pci_dev *dev) 527{ 528 struct xhci_hcd *xhci; 529 530 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 531 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK) 532 renesas_xhci_pci_exit(dev); 533 534 xhci->xhc_state |= XHCI_STATE_REMOVING; 535 536 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 537 pm_runtime_forbid(&dev->dev); 538 539 if (xhci->shared_hcd) { 540 usb_remove_hcd(xhci->shared_hcd); 541 usb_put_hcd(xhci->shared_hcd); 542 xhci->shared_hcd = NULL; 543 } 544 545 /* Workaround for spurious wakeups at shutdown with HSW */ 546 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 547 pci_set_power_state(dev, PCI_D3hot); 548 549 /* Workaround for decreasing power consumption after S5 */ 550 if (xhci->quirks & XHCI_LWP_QUIRK) 551 pci_set_power_state(dev, PCI_D3hot); 552 553 usb_hcd_pci_remove(dev); 554} 555 556#ifdef CONFIG_PM 557/* 558 * In some Intel xHCI controllers, in order to get D3 working, 559 * through a vendor specific SSIC CONFIG register at offset 0x883c, 560 * SSIC PORT need to be marked as "unused" before putting xHCI 561 * into D3. After D3 exit, the SSIC port need to be marked as "used". 562 * Without this change, xHCI might not enter D3 state. 563 */ 564static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 565{ 566 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 567 u32 val; 568 void __iomem *reg; 569 int i; 570 571 for (i = 0; i < SSIC_PORT_NUM; i++) { 572 reg = (void __iomem *) xhci->cap_regs + 573 SSIC_PORT_CFG2 + 574 i * SSIC_PORT_CFG2_OFFSET; 575 576 /* Notify SSIC that SSIC profile programming is not done. */ 577 val = readl(reg) & ~PROG_DONE; 578 writel(val, reg); 579 580 /* Mark SSIC port as unused(suspend) or used(resume) */ 581 val = readl(reg); 582 if (suspend) 583 val |= SSIC_PORT_UNUSED; 584 else 585 val &= ~SSIC_PORT_UNUSED; 586 writel(val, reg); 587 588 /* Notify SSIC that SSIC profile programming is done */ 589 val = readl(reg) | PROG_DONE; 590 writel(val, reg); 591 readl(reg); 592 } 593} 594 595/* 596 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 597 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 598 */ 599static void xhci_pme_quirk(struct usb_hcd *hcd) 600{ 601 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 602 void __iomem *reg; 603 u32 val; 604 605 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 606 val = readl(reg); 607 writel(val | BIT(28), reg); 608 readl(reg); 609} 610 611static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 612{ 613 u32 reg; 614 615 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 616 reg &= ~BIT(SPARSE_DISABLE_BIT); 617 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 618} 619 620static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 621{ 622 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 623 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 624 int ret; 625 626 /* 627 * Systems with the TI redriver that loses port status change events 628 * need to have the registers polled during D3, so avoid D3cold. 629 */ 630 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 631 pci_d3cold_disable(pdev); 632 633 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 634 xhci_pme_quirk(hcd); 635 636 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 637 xhci_ssic_port_unused_quirk(hcd, true); 638 639 if (xhci->quirks & XHCI_DISABLE_SPARSE) 640 xhci_sparse_control_quirk(hcd); 641 642 ret = xhci_suspend(xhci, do_wakeup); 643 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 644 xhci_ssic_port_unused_quirk(hcd, false); 645 646 return ret; 647} 648 649static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 650{ 651 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 652 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 653 int retval = 0; 654 655 reset_control_reset(xhci->reset); 656 657 /* The BIOS on systems with the Intel Panther Point chipset may or may 658 * not support xHCI natively. That means that during system resume, it 659 * may switch the ports back to EHCI so that users can use their 660 * keyboard to select a kernel from GRUB after resume from hibernate. 661 * 662 * The BIOS is supposed to remember whether the OS had xHCI ports 663 * enabled before resume, and switch the ports back to xHCI when the 664 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 665 * writers. 666 * 667 * Unconditionally switch the ports back to xHCI after a system resume. 668 * It should not matter whether the EHCI or xHCI controller is 669 * resumed first. It's enough to do the switchover in xHCI because 670 * USB core won't notice anything as the hub driver doesn't start 671 * running again until after all the devices (including both EHCI and 672 * xHCI host controllers) have been resumed. 673 */ 674 675 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 676 usb_enable_intel_xhci_ports(pdev); 677 678 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 679 xhci_ssic_port_unused_quirk(hcd, false); 680 681 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 682 xhci_pme_quirk(hcd); 683 684 retval = xhci_resume(xhci, hibernated); 685 return retval; 686} 687 688static void xhci_pci_shutdown(struct usb_hcd *hcd) 689{ 690 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 691 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 692 693 xhci_shutdown(hcd); 694 695 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 696 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 697 pci_set_power_state(pdev, PCI_D3hot); 698 699 /* Workaround for decreasing power consumption after S5 */ 700 if (xhci->quirks & XHCI_LWP_QUIRK) 701 pci_set_power_state(pdev, PCI_D3hot); 702} 703#endif /* CONFIG_PM */ 704 705/*-------------------------------------------------------------------------*/ 706 707static const struct xhci_driver_data reneses_data = { 708 .quirks = XHCI_RENESAS_FW_QUIRK, 709 .firmware = "renesas_usb_fw.mem", 710}; 711 712/* PCI driver selection metadata; PCI hotplugging uses this */ 713static const struct pci_device_id pci_ids[] = { 714 { PCI_DEVICE(0x1912, 0x0014), 715 .driver_data = (unsigned long)&reneses_data, 716 }, 717 { PCI_DEVICE(0x1912, 0x0015), 718 .driver_data = (unsigned long)&reneses_data, 719 }, 720 /* handle any USB 3.0 xHCI controller */ 721 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 722 }, 723 { /* end: all zeroes */ } 724}; 725MODULE_DEVICE_TABLE(pci, pci_ids); 726 727/* 728 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't 729 * load firmware, so don't encumber the xhci-pci driver with it. 730 */ 731#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) 732MODULE_FIRMWARE("renesas_usb_fw.mem"); 733#endif 734 735/* pci driver glue; this is a "new style" PCI driver module */ 736static struct pci_driver xhci_pci_driver = { 737 .name = hcd_name, 738 .id_table = pci_ids, 739 740 .probe = xhci_pci_probe, 741 .remove = xhci_pci_remove, 742 /* suspend and resume implemented later */ 743 744 .shutdown = usb_hcd_pci_shutdown, 745#ifdef CONFIG_PM 746 .driver = { 747 .pm = &usb_hcd_pci_pm_ops 748 }, 749#endif 750}; 751 752static int __init xhci_pci_init(void) 753{ 754 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 755#ifdef CONFIG_PM 756 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; 757 xhci_pci_hc_driver.pci_resume = xhci_pci_resume; 758 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown; 759#endif 760 return pci_register_driver(&xhci_pci_driver); 761} 762module_init(xhci_pci_init); 763 764static void __exit xhci_pci_exit(void) 765{ 766 pci_unregister_driver(&xhci_pci_driver); 767} 768module_exit(xhci_pci_exit); 769 770MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 771MODULE_LICENSE("GPL"); 772