1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MediaTek xHCI Host Controller Driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: 7 * Chunfeng Yun <chunfeng.yun@mediatek.com> 8 */ 9 10#include <linux/clk.h> 11#include <linux/dma-mapping.h> 12#include <linux/iopoll.h> 13#include <linux/kernel.h> 14#include <linux/mfd/syscon.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/pm_runtime.h> 19#include <linux/regmap.h> 20#include <linux/regulator/consumer.h> 21 22#include "xhci.h" 23#include "xhci-mtk.h" 24 25/* ip_pw_ctrl0 register */ 26#define CTRL0_IP_SW_RST BIT(0) 27 28/* ip_pw_ctrl1 register */ 29#define CTRL1_IP_HOST_PDN BIT(0) 30 31/* ip_pw_ctrl2 register */ 32#define CTRL2_IP_DEV_PDN BIT(0) 33 34/* ip_pw_sts1 register */ 35#define STS1_IP_SLEEP_STS BIT(30) 36#define STS1_U3_MAC_RST BIT(16) 37#define STS1_XHCI_RST BIT(11) 38#define STS1_SYS125_RST BIT(10) 39#define STS1_REF_RST BIT(8) 40#define STS1_SYSPLL_STABLE BIT(0) 41 42/* ip_xhci_cap register */ 43#define CAP_U3_PORT_NUM(p) ((p) & 0xff) 44#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 45 46/* u3_ctrl_p register */ 47#define CTRL_U3_PORT_HOST_SEL BIT(2) 48#define CTRL_U3_PORT_PDN BIT(1) 49#define CTRL_U3_PORT_DIS BIT(0) 50 51/* u2_ctrl_p register */ 52#define CTRL_U2_PORT_HOST_SEL BIT(2) 53#define CTRL_U2_PORT_PDN BIT(1) 54#define CTRL_U2_PORT_DIS BIT(0) 55 56/* u2_phy_pll register */ 57#define CTRL_U2_FORCE_PLL_STB BIT(28) 58 59/* usb remote wakeup registers in syscon */ 60/* mt8173 etc */ 61#define PERI_WK_CTRL1 0x4 62#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ 63#define WC1_IS_EN BIT(25) 64#define WC1_IS_P BIT(6) /* polarity for ip sleep */ 65 66/* mt2712 etc */ 67#define PERI_SSUSB_SPM_CTRL 0x0 68#define SSC_IP_SLEEP_EN BIT(4) 69#define SSC_SPM_INT_EN BIT(1) 70 71enum ssusb_uwk_vers { 72 SSUSB_UWK_V1 = 1, 73 SSUSB_UWK_V2, 74}; 75 76static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 77{ 78 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 79 u32 value, check_val; 80 int u3_ports_disabled = 0; 81 int ret; 82 int i; 83 84 if (!mtk->has_ippc) 85 return 0; 86 87 /* power on host ip */ 88 value = readl(&ippc->ip_pw_ctr1); 89 value &= ~CTRL1_IP_HOST_PDN; 90 writel(value, &ippc->ip_pw_ctr1); 91 92 /* power on and enable u3 ports except skipped ones */ 93 for (i = 0; i < mtk->num_u3_ports; i++) { 94 if ((0x1 << i) & mtk->u3p_dis_msk) { 95 u3_ports_disabled++; 96 continue; 97 } 98 99 value = readl(&ippc->u3_ctrl_p[i]); 100 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 101 value |= CTRL_U3_PORT_HOST_SEL; 102 writel(value, &ippc->u3_ctrl_p[i]); 103 } 104 105 /* power on and enable all u2 ports */ 106 for (i = 0; i < mtk->num_u2_ports; i++) { 107 value = readl(&ippc->u2_ctrl_p[i]); 108 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 109 value |= CTRL_U2_PORT_HOST_SEL; 110 writel(value, &ippc->u2_ctrl_p[i]); 111 } 112 113 /* 114 * wait for clocks to be stable, and clock domains reset to 115 * be inactive after power on and enable ports 116 */ 117 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 118 STS1_SYS125_RST | STS1_XHCI_RST; 119 120 if (mtk->num_u3_ports > u3_ports_disabled) 121 check_val |= STS1_U3_MAC_RST; 122 123 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 124 (check_val == (value & check_val)), 100, 20000); 125 if (ret) { 126 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 127 return ret; 128 } 129 130 return 0; 131} 132 133static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 134{ 135 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 136 u32 value; 137 int ret; 138 int i; 139 140 if (!mtk->has_ippc) 141 return 0; 142 143 /* power down u3 ports except skipped ones */ 144 for (i = 0; i < mtk->num_u3_ports; i++) { 145 if ((0x1 << i) & mtk->u3p_dis_msk) 146 continue; 147 148 value = readl(&ippc->u3_ctrl_p[i]); 149 value |= CTRL_U3_PORT_PDN; 150 writel(value, &ippc->u3_ctrl_p[i]); 151 } 152 153 /* power down all u2 ports */ 154 for (i = 0; i < mtk->num_u2_ports; i++) { 155 value = readl(&ippc->u2_ctrl_p[i]); 156 value |= CTRL_U2_PORT_PDN; 157 writel(value, &ippc->u2_ctrl_p[i]); 158 } 159 160 /* power down host ip */ 161 value = readl(&ippc->ip_pw_ctr1); 162 value |= CTRL1_IP_HOST_PDN; 163 writel(value, &ippc->ip_pw_ctr1); 164 165 /* wait for host ip to sleep */ 166 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 167 (value & STS1_IP_SLEEP_STS), 100, 100000); 168 if (ret) { 169 dev_err(mtk->dev, "ip sleep failed!!!\n"); 170 return ret; 171 } 172 return 0; 173} 174 175static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 176{ 177 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 178 u32 value; 179 180 if (!mtk->has_ippc) 181 return 0; 182 183 /* reset whole ip */ 184 value = readl(&ippc->ip_pw_ctr0); 185 value |= CTRL0_IP_SW_RST; 186 writel(value, &ippc->ip_pw_ctr0); 187 udelay(1); 188 value = readl(&ippc->ip_pw_ctr0); 189 value &= ~CTRL0_IP_SW_RST; 190 writel(value, &ippc->ip_pw_ctr0); 191 192 /* 193 * device ip is default power-on in fact 194 * power down device ip, otherwise ip-sleep will fail 195 */ 196 value = readl(&ippc->ip_pw_ctr2); 197 value |= CTRL2_IP_DEV_PDN; 198 writel(value, &ippc->ip_pw_ctr2); 199 200 value = readl(&ippc->ip_xhci_cap); 201 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 202 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 203 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 204 mtk->num_u2_ports, mtk->num_u3_ports); 205 206 return xhci_mtk_host_enable(mtk); 207} 208 209static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) 210{ 211 struct device *dev = mtk->dev; 212 213 mtk->sys_clk = devm_clk_get(dev, "sys_ck"); 214 if (IS_ERR(mtk->sys_clk)) { 215 dev_err(dev, "fail to get sys_ck\n"); 216 return PTR_ERR(mtk->sys_clk); 217 } 218 219 mtk->xhci_clk = devm_clk_get_optional(dev, "xhci_ck"); 220 if (IS_ERR(mtk->xhci_clk)) 221 return PTR_ERR(mtk->xhci_clk); 222 223 mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck"); 224 if (IS_ERR(mtk->ref_clk)) 225 return PTR_ERR(mtk->ref_clk); 226 227 mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck"); 228 if (IS_ERR(mtk->mcu_clk)) 229 return PTR_ERR(mtk->mcu_clk); 230 231 mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck"); 232 return PTR_ERR_OR_ZERO(mtk->dma_clk); 233} 234 235static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) 236{ 237 int ret; 238 239 ret = clk_prepare_enable(mtk->ref_clk); 240 if (ret) { 241 dev_err(mtk->dev, "failed to enable ref_clk\n"); 242 goto ref_clk_err; 243 } 244 245 ret = clk_prepare_enable(mtk->sys_clk); 246 if (ret) { 247 dev_err(mtk->dev, "failed to enable sys_clk\n"); 248 goto sys_clk_err; 249 } 250 251 ret = clk_prepare_enable(mtk->xhci_clk); 252 if (ret) { 253 dev_err(mtk->dev, "failed to enable xhci_clk\n"); 254 goto xhci_clk_err; 255 } 256 257 ret = clk_prepare_enable(mtk->mcu_clk); 258 if (ret) { 259 dev_err(mtk->dev, "failed to enable mcu_clk\n"); 260 goto mcu_clk_err; 261 } 262 263 ret = clk_prepare_enable(mtk->dma_clk); 264 if (ret) { 265 dev_err(mtk->dev, "failed to enable dma_clk\n"); 266 goto dma_clk_err; 267 } 268 269 return 0; 270 271dma_clk_err: 272 clk_disable_unprepare(mtk->mcu_clk); 273mcu_clk_err: 274 clk_disable_unprepare(mtk->xhci_clk); 275xhci_clk_err: 276 clk_disable_unprepare(mtk->sys_clk); 277sys_clk_err: 278 clk_disable_unprepare(mtk->ref_clk); 279ref_clk_err: 280 return ret; 281} 282 283static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) 284{ 285 clk_disable_unprepare(mtk->dma_clk); 286 clk_disable_unprepare(mtk->mcu_clk); 287 clk_disable_unprepare(mtk->xhci_clk); 288 clk_disable_unprepare(mtk->sys_clk); 289 clk_disable_unprepare(mtk->ref_clk); 290} 291 292/* only clocks can be turn off for ip-sleep wakeup mode */ 293static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) 294{ 295 u32 reg, msk, val; 296 297 switch (mtk->uwk_vers) { 298 case SSUSB_UWK_V1: 299 reg = mtk->uwk_reg_base + PERI_WK_CTRL1; 300 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; 301 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; 302 break; 303 case SSUSB_UWK_V2: 304 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; 305 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; 306 val = enable ? msk : 0; 307 break; 308 default: 309 return; 310 } 311 regmap_update_bits(mtk->uwk, reg, msk, val); 312} 313 314static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 315 struct device_node *dn) 316{ 317 struct of_phandle_args args; 318 int ret; 319 320 /* Wakeup function is optional */ 321 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); 322 if (!mtk->uwk_en) 323 return 0; 324 325 ret = of_parse_phandle_with_fixed_args(dn, 326 "mediatek,syscon-wakeup", 2, 0, &args); 327 if (ret) 328 return ret; 329 330 mtk->uwk_reg_base = args.args[0]; 331 mtk->uwk_vers = args.args[1]; 332 mtk->uwk = syscon_node_to_regmap(args.np); 333 of_node_put(args.np); 334 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", 335 mtk->uwk_reg_base, mtk->uwk_vers); 336 337 return PTR_ERR_OR_ZERO(mtk->uwk); 338 339} 340 341static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) 342{ 343 if (mtk->uwk_en) 344 usb_wakeup_ip_sleep_set(mtk, enable); 345} 346 347static int xhci_mtk_setup(struct usb_hcd *hcd); 348static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 349 .reset = xhci_mtk_setup, 350 .check_bandwidth = xhci_mtk_check_bandwidth, 351 .reset_bandwidth = xhci_mtk_reset_bandwidth, 352}; 353 354static struct hc_driver __read_mostly xhci_mtk_hc_driver; 355 356static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 357{ 358 int ret; 359 360 ret = regulator_enable(mtk->vbus); 361 if (ret) { 362 dev_err(mtk->dev, "failed to enable vbus\n"); 363 return ret; 364 } 365 366 ret = regulator_enable(mtk->vusb33); 367 if (ret) { 368 dev_err(mtk->dev, "failed to enable vusb33\n"); 369 regulator_disable(mtk->vbus); 370 return ret; 371 } 372 return 0; 373} 374 375static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 376{ 377 regulator_disable(mtk->vbus); 378 regulator_disable(mtk->vusb33); 379} 380 381static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 382{ 383 struct usb_hcd *hcd = xhci_to_hcd(xhci); 384 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 385 386 /* 387 * As of now platform drivers don't provide MSI support so we ensure 388 * here that the generic code does not try to make a pci_dev from our 389 * dev struct in order to setup MSI 390 */ 391 xhci->quirks |= XHCI_PLAT; 392 xhci->quirks |= XHCI_MTK_HOST; 393 /* 394 * MTK host controller gives a spurious successful event after a 395 * short transfer. Ignore it. 396 */ 397 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 398 if (mtk->lpm_support) 399 xhci->quirks |= XHCI_LPM_SUPPORT; 400 if (mtk->u2_lpm_disable) 401 xhci->quirks |= XHCI_HW_LPM_DISABLE; 402 403 /* 404 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream, 405 * and it's 3 when support it. 406 */ 407 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4) 408 xhci->quirks |= XHCI_BROKEN_STREAMS; 409} 410 411/* called during probe() after chip reset completes */ 412static int xhci_mtk_setup(struct usb_hcd *hcd) 413{ 414 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 415 int ret; 416 417 if (usb_hcd_is_primary_hcd(hcd)) { 418 ret = xhci_mtk_ssusb_config(mtk); 419 if (ret) 420 return ret; 421 } 422 423 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 424 if (ret) 425 return ret; 426 427 if (usb_hcd_is_primary_hcd(hcd)) { 428 ret = xhci_mtk_sch_init(mtk); 429 if (ret) 430 return ret; 431 } 432 433 return ret; 434} 435 436static int xhci_mtk_probe(struct platform_device *pdev) 437{ 438 struct device *dev = &pdev->dev; 439 struct device_node *node = dev->of_node; 440 struct xhci_hcd_mtk *mtk; 441 const struct hc_driver *driver; 442 struct xhci_hcd *xhci; 443 struct resource *res; 444 struct usb_hcd *hcd; 445 int ret = -ENODEV; 446 int irq; 447 448 if (usb_disabled()) 449 return -ENODEV; 450 451 driver = &xhci_mtk_hc_driver; 452 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 453 if (!mtk) 454 return -ENOMEM; 455 456 mtk->dev = dev; 457 mtk->vbus = devm_regulator_get(dev, "vbus"); 458 if (IS_ERR(mtk->vbus)) { 459 dev_err(dev, "fail to get vbus\n"); 460 return PTR_ERR(mtk->vbus); 461 } 462 463 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 464 if (IS_ERR(mtk->vusb33)) { 465 dev_err(dev, "fail to get vusb33\n"); 466 return PTR_ERR(mtk->vusb33); 467 } 468 469 ret = xhci_mtk_clks_get(mtk); 470 if (ret) 471 return ret; 472 473 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 474 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable"); 475 /* optional property, ignore the error if it does not exist */ 476 of_property_read_u32(node, "mediatek,u3p-dis-msk", 477 &mtk->u3p_dis_msk); 478 479 ret = usb_wakeup_of_property_parse(mtk, node); 480 if (ret) { 481 dev_err(dev, "failed to parse uwk property\n"); 482 return ret; 483 } 484 485 pm_runtime_enable(dev); 486 pm_runtime_get_sync(dev); 487 device_enable_async_suspend(dev); 488 489 ret = xhci_mtk_ldos_enable(mtk); 490 if (ret) 491 goto disable_pm; 492 493 ret = xhci_mtk_clks_enable(mtk); 494 if (ret) 495 goto disable_ldos; 496 497 irq = platform_get_irq(pdev, 0); 498 if (irq < 0) { 499 ret = irq; 500 goto disable_clk; 501 } 502 503 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 504 if (!hcd) { 505 ret = -ENOMEM; 506 goto disable_clk; 507 } 508 509 /* 510 * USB 2.0 roothub is stored in the platform_device. 511 * Swap it with mtk HCD. 512 */ 513 mtk->hcd = platform_get_drvdata(pdev); 514 platform_set_drvdata(pdev, mtk); 515 516 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 517 hcd->regs = devm_ioremap_resource(dev, res); 518 if (IS_ERR(hcd->regs)) { 519 ret = PTR_ERR(hcd->regs); 520 goto put_usb2_hcd; 521 } 522 hcd->rsrc_start = res->start; 523 hcd->rsrc_len = resource_size(res); 524 525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 526 if (res) { /* ippc register is optional */ 527 mtk->ippc_regs = devm_ioremap_resource(dev, res); 528 if (IS_ERR(mtk->ippc_regs)) { 529 ret = PTR_ERR(mtk->ippc_regs); 530 goto put_usb2_hcd; 531 } 532 mtk->has_ippc = true; 533 } else { 534 mtk->has_ippc = false; 535 } 536 537 device_init_wakeup(dev, true); 538 dma_set_max_seg_size(dev, UINT_MAX); 539 540 xhci = hcd_to_xhci(hcd); 541 xhci->main_hcd = hcd; 542 543 /* 544 * imod_interval is the interrupt moderation value in nanoseconds. 545 * The increment interval is 8 times as much as that defined in 546 * the xHCI spec on MTK's controller. 547 */ 548 xhci->imod_interval = 5000; 549 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); 550 551 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 552 dev_name(dev), hcd); 553 if (!xhci->shared_hcd) { 554 ret = -ENOMEM; 555 goto disable_device_wakeup; 556 } 557 558 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 559 if (ret) 560 goto put_usb3_hcd; 561 562 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 && 563 !(xhci->quirks & XHCI_BROKEN_STREAMS)) 564 xhci->shared_hcd->can_do_streams = 1; 565 566 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 567 if (ret) 568 goto dealloc_usb2_hcd; 569 570 return 0; 571 572dealloc_usb2_hcd: 573 usb_remove_hcd(hcd); 574 575put_usb3_hcd: 576 xhci_mtk_sch_exit(mtk); 577 usb_put_hcd(xhci->shared_hcd); 578 579disable_device_wakeup: 580 device_init_wakeup(dev, false); 581 582put_usb2_hcd: 583 usb_put_hcd(hcd); 584 585disable_clk: 586 xhci_mtk_clks_disable(mtk); 587 588disable_ldos: 589 xhci_mtk_ldos_disable(mtk); 590 591disable_pm: 592 pm_runtime_put_sync(dev); 593 pm_runtime_disable(dev); 594 return ret; 595} 596 597static int xhci_mtk_remove(struct platform_device *dev) 598{ 599 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev); 600 struct usb_hcd *hcd = mtk->hcd; 601 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 602 struct usb_hcd *shared_hcd = xhci->shared_hcd; 603 604 pm_runtime_put_noidle(&dev->dev); 605 pm_runtime_disable(&dev->dev); 606 607 usb_remove_hcd(shared_hcd); 608 xhci->shared_hcd = NULL; 609 device_init_wakeup(&dev->dev, false); 610 611 usb_remove_hcd(hcd); 612 usb_put_hcd(shared_hcd); 613 usb_put_hcd(hcd); 614 xhci_mtk_sch_exit(mtk); 615 xhci_mtk_clks_disable(mtk); 616 xhci_mtk_ldos_disable(mtk); 617 618 return 0; 619} 620 621/* 622 * if ip sleep fails, and all clocks are disabled, access register will hang 623 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend. 624 * and no need to check whether ip sleep failed or not; this will cause SPM 625 * to wake up system immediately after system suspend complete if ip sleep 626 * fails, it is what we wanted. 627 */ 628static int __maybe_unused xhci_mtk_suspend(struct device *dev) 629{ 630 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 631 struct usb_hcd *hcd = mtk->hcd; 632 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 633 634 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 635 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 636 del_timer_sync(&hcd->rh_timer); 637 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 638 del_timer_sync(&xhci->shared_hcd->rh_timer); 639 640 xhci_mtk_host_disable(mtk); 641 xhci_mtk_clks_disable(mtk); 642 usb_wakeup_set(mtk, true); 643 return 0; 644} 645 646static int __maybe_unused xhci_mtk_resume(struct device *dev) 647{ 648 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 649 struct usb_hcd *hcd = mtk->hcd; 650 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 651 652 usb_wakeup_set(mtk, false); 653 xhci_mtk_clks_enable(mtk); 654 xhci_mtk_host_enable(mtk); 655 656 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 657 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 658 usb_hcd_poll_rh_status(xhci->shared_hcd); 659 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 660 usb_hcd_poll_rh_status(hcd); 661 return 0; 662} 663 664static const struct dev_pm_ops xhci_mtk_pm_ops = { 665 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 666}; 667#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL 668 669#ifdef CONFIG_OF 670static const struct of_device_id mtk_xhci_of_match[] = { 671 { .compatible = "mediatek,mt8173-xhci"}, 672 { .compatible = "mediatek,mtk-xhci"}, 673 { }, 674}; 675MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 676#endif 677 678static struct platform_driver mtk_xhci_driver = { 679 .probe = xhci_mtk_probe, 680 .remove = xhci_mtk_remove, 681 .driver = { 682 .name = "xhci-mtk", 683 .pm = DEV_PM_OPS, 684 .of_match_table = of_match_ptr(mtk_xhci_of_match), 685 }, 686}; 687MODULE_ALIAS("platform:xhci-mtk"); 688 689static int __init xhci_mtk_init(void) 690{ 691 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 692 return platform_driver_register(&mtk_xhci_driver); 693} 694module_init(xhci_mtk_init); 695 696static void __exit xhci_mtk_exit(void) 697{ 698 platform_driver_unregister(&mtk_xhci_driver); 699} 700module_exit(xhci_mtk_exit); 701 702MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 703MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 704MODULE_LICENSE("GPL v2"); 705