1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2005-2009 MontaVista Software, Inc. 4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. 5 * 6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided 7 * by Hunter Wu. 8 * Power Management support by Dave Liu <daveliu@freescale.com>, 9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and 10 * Anton Vorontsov <avorontsov@ru.mvista.com>. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/types.h> 16#include <linux/delay.h> 17#include <linux/pm.h> 18#include <linux/err.h> 19#include <linux/usb.h> 20#include <linux/usb/ehci_def.h> 21#include <linux/usb/hcd.h> 22#include <linux/usb/otg.h> 23#include <linux/platform_device.h> 24#include <linux/fsl_devices.h> 25#include <linux/of_platform.h> 26#include <linux/io.h> 27 28#include "ehci.h" 29#include "ehci-fsl.h" 30 31#define DRIVER_DESC "Freescale EHCI Host controller driver" 32#define DRV_NAME "fsl-ehci" 33 34static struct hc_driver __read_mostly fsl_ehci_hc_driver; 35 36/* configure so an HC device and id are always provided */ 37/* always called with process context; sleeping is OK */ 38 39/* 40 * fsl_ehci_drv_probe - initialize FSL-based HCDs 41 * @pdev: USB Host Controller being probed 42 * Context: !in_interrupt() 43 * 44 * Allocates basic resources for this USB host controller. 45 * 46 */ 47static int fsl_ehci_drv_probe(struct platform_device *pdev) 48{ 49 struct fsl_usb2_platform_data *pdata; 50 struct usb_hcd *hcd; 51 struct resource *res; 52 int irq; 53 int retval; 54 u32 tmp; 55 56 pr_debug("initializing FSL-SOC USB Controller\n"); 57 58 /* Need platform data for setup */ 59 pdata = dev_get_platdata(&pdev->dev); 60 if (!pdata) { 61 dev_err(&pdev->dev, 62 "No platform data for %s.\n", dev_name(&pdev->dev)); 63 return -ENODEV; 64 } 65 66 /* 67 * This is a host mode driver, verify that we're supposed to be 68 * in host mode. 69 */ 70 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || 71 (pdata->operating_mode == FSL_USB2_MPH_HOST) || 72 (pdata->operating_mode == FSL_USB2_DR_OTG))) { 73 dev_err(&pdev->dev, 74 "Non Host Mode configured for %s. Wrong driver linked.\n", 75 dev_name(&pdev->dev)); 76 return -ENODEV; 77 } 78 79 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 80 if (!res) { 81 dev_err(&pdev->dev, 82 "Found HC with no IRQ. Check %s setup!\n", 83 dev_name(&pdev->dev)); 84 return -ENODEV; 85 } 86 irq = res->start; 87 88 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, 89 &pdev->dev, dev_name(&pdev->dev), NULL); 90 if (!hcd) { 91 retval = -ENOMEM; 92 goto err1; 93 } 94 95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 96 hcd->regs = devm_ioremap_resource(&pdev->dev, res); 97 if (IS_ERR(hcd->regs)) { 98 retval = PTR_ERR(hcd->regs); 99 goto err2; 100 } 101 102 hcd->rsrc_start = res->start; 103 hcd->rsrc_len = resource_size(res); 104 105 pdata->regs = hcd->regs; 106 107 if (pdata->power_budget) 108 hcd->power_budget = pdata->power_budget; 109 110 /* 111 * do platform specific init: check the clock, grab/config pins, etc. 112 */ 113 if (pdata->init && pdata->init(pdev)) { 114 retval = -ENODEV; 115 goto err2; 116 } 117 118 /* Enable USB controller, 83xx or 8536 */ 119 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { 120 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 121 tmp &= ~CONTROL_REGISTER_W1C_MASK; 122 tmp |= 0x4; 123 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 124 } 125 126 /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */ 127 if (pdata->controller_ver == FSL_USB_VER_2_5 && 128 pdata->phy_mode == FSL_USB2_PHY_ULPI) 129 iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL); 130 131 /* 132 * Enable UTMI phy and program PTS field in UTMI mode before asserting 133 * controller reset for USB Controller version 2.5 134 */ 135 if (pdata->has_fsl_erratum_a007792) { 136 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 137 tmp &= ~CONTROL_REGISTER_W1C_MASK; 138 tmp |= CTRL_UTMI_PHY_EN; 139 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 140 141 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); 142 } 143 144 /* Don't need to set host mode here. It will be done by tdi_reset() */ 145 146 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 147 if (retval != 0) 148 goto err2; 149 device_wakeup_enable(hcd->self.controller); 150 151#ifdef CONFIG_USB_OTG 152 if (pdata->operating_mode == FSL_USB2_DR_OTG) { 153 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 154 155 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); 156 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", 157 hcd, ehci, hcd->usb_phy); 158 159 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 160 retval = otg_set_host(hcd->usb_phy->otg, 161 &ehci_to_hcd(ehci)->self); 162 if (retval) { 163 usb_put_phy(hcd->usb_phy); 164 goto err2; 165 } 166 } else { 167 dev_err(&pdev->dev, "can't find phy\n"); 168 retval = -ENODEV; 169 goto err2; 170 } 171 172 hcd->skip_phy_initialization = 1; 173 } 174#endif 175 return retval; 176 177 err2: 178 usb_put_hcd(hcd); 179 err1: 180 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); 181 if (pdata->exit) 182 pdata->exit(pdev); 183 return retval; 184} 185 186static bool usb_phy_clk_valid(struct usb_hcd *hcd) 187{ 188 void __iomem *non_ehci = hcd->regs; 189 bool ret = true; 190 191 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) 192 ret = false; 193 194 return ret; 195} 196 197static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 198 enum fsl_usb2_phy_modes phy_mode, 199 unsigned int port_offset) 200{ 201 u32 portsc, tmp; 202 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 203 void __iomem *non_ehci = hcd->regs; 204 struct device *dev = hcd->self.controller; 205 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 206 207 if (pdata->controller_ver < 0) { 208 dev_warn(hcd->self.controller, "Could not get controller version\n"); 209 return -ENODEV; 210 } 211 212 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); 213 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); 214 215 switch (phy_mode) { 216 case FSL_USB2_PHY_ULPI: 217 if (pdata->have_sysif_regs && pdata->controller_ver) { 218 /* controller version 1.6 or above */ 219 /* turn off UTMI PHY first */ 220 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 221 tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); 222 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 223 224 /* then turn on ULPI and enable USB controller */ 225 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 226 tmp &= ~CONTROL_REGISTER_W1C_MASK; 227 tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; 228 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 229 } 230 portsc |= PORT_PTS_ULPI; 231 break; 232 case FSL_USB2_PHY_SERIAL: 233 portsc |= PORT_PTS_SERIAL; 234 break; 235 case FSL_USB2_PHY_UTMI_WIDE: 236 portsc |= PORT_PTS_PTW; 237 fallthrough; 238 case FSL_USB2_PHY_UTMI: 239 /* Presence of this node "has_fsl_erratum_a006918" 240 * in device-tree is used to stop USB controller 241 * initialization in Linux 242 */ 243 if (pdata->has_fsl_erratum_a006918) { 244 dev_warn(dev, "USB PHY clock invalid\n"); 245 return -EINVAL; 246 } 247 fallthrough; 248 case FSL_USB2_PHY_UTMI_DUAL: 249 /* PHY_CLK_VALID bit is de-featured from all controller 250 * versions below 2.4 and is to be checked only for 251 * internal UTMI phy 252 */ 253 if (pdata->controller_ver > FSL_USB_VER_2_4 && 254 pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) { 255 dev_err(dev, "USB PHY clock invalid\n"); 256 return -EINVAL; 257 } 258 259 if (pdata->have_sysif_regs && pdata->controller_ver) { 260 /* controller version 1.6 or above */ 261 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 262 tmp &= ~CONTROL_REGISTER_W1C_MASK; 263 tmp |= UTMI_PHY_EN; 264 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 265 266 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to 267 become stable - 10ms*/ 268 } 269 /* enable UTMI PHY */ 270 if (pdata->have_sysif_regs) { 271 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 272 tmp &= ~CONTROL_REGISTER_W1C_MASK; 273 tmp |= CTRL_UTMI_PHY_EN; 274 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 275 } 276 portsc |= PORT_PTS_UTMI; 277 break; 278 case FSL_USB2_PHY_NONE: 279 break; 280 } 281 282 if (pdata->have_sysif_regs && 283 pdata->controller_ver > FSL_USB_VER_1_6 && 284 !usb_phy_clk_valid(hcd)) { 285 dev_warn(hcd->self.controller, "USB PHY clock invalid\n"); 286 return -EINVAL; 287 } 288 289 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 290 291 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { 292 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 293 tmp &= ~CONTROL_REGISTER_W1C_MASK; 294 tmp |= USB_CTRL_USB_EN; 295 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 296 } 297 298 return 0; 299} 300 301static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) 302{ 303 struct usb_hcd *hcd = ehci_to_hcd(ehci); 304 struct fsl_usb2_platform_data *pdata; 305 void __iomem *non_ehci = hcd->regs; 306 307 pdata = dev_get_platdata(hcd->self.controller); 308 309 if (pdata->have_sysif_regs) { 310 /* 311 * Turn on cache snooping hardware, since some PowerPC platforms 312 * wholly rely on hardware to deal with cache coherent 313 */ 314 315 /* Setup Snooping for all the 4GB space */ 316 /* SNOOP1 starts from 0x0, size 2G */ 317 iowrite32be(0x0 | SNOOP_SIZE_2GB, 318 non_ehci + FSL_SOC_USB_SNOOP1); 319 /* SNOOP2 starts from 0x80000000, size 2G */ 320 iowrite32be(0x80000000 | SNOOP_SIZE_2GB, 321 non_ehci + FSL_SOC_USB_SNOOP2); 322 } 323 324 /* Deal with USB erratum A-005275 */ 325 if (pdata->has_fsl_erratum_a005275 == 1) 326 ehci->has_fsl_hs_errata = 1; 327 328 if (pdata->has_fsl_erratum_a005697 == 1) 329 ehci->has_fsl_susp_errata = 1; 330 331 if ((pdata->operating_mode == FSL_USB2_DR_HOST) || 332 (pdata->operating_mode == FSL_USB2_DR_OTG)) 333 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 334 return -EINVAL; 335 336 if (pdata->operating_mode == FSL_USB2_MPH_HOST) { 337 338 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ 339 if (pdata->has_fsl_erratum_14 == 1) 340 ehci->has_fsl_port_bug = 1; 341 342 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) 343 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 344 return -EINVAL; 345 346 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) 347 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) 348 return -EINVAL; 349 } 350 351 if (pdata->have_sysif_regs) { 352#ifdef CONFIG_FSL_SOC_BOOKE 353 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); 354 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 355#else 356 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); 357 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 358#endif 359 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); 360 } 361 362 return 0; 363} 364 365/* called after powerup, by probe or system-pm "wakeup" */ 366static int ehci_fsl_reinit(struct ehci_hcd *ehci) 367{ 368 if (ehci_fsl_usb_setup(ehci)) 369 return -EINVAL; 370 371 return 0; 372} 373 374/* called during probe() after chip reset completes */ 375static int ehci_fsl_setup(struct usb_hcd *hcd) 376{ 377 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 378 int retval; 379 struct fsl_usb2_platform_data *pdata; 380 struct device *dev; 381 382 dev = hcd->self.controller; 383 pdata = dev_get_platdata(hcd->self.controller); 384 ehci->big_endian_desc = pdata->big_endian_desc; 385 ehci->big_endian_mmio = pdata->big_endian_mmio; 386 387 /* EHCI registers start at offset 0x100 */ 388 ehci->caps = hcd->regs + 0x100; 389 390#ifdef CONFIG_PPC_83xx 391 /* 392 * Deal with MPC834X that need port power to be cycled after the power 393 * fault condition is removed. Otherwise the state machine does not 394 * reflect PORTSC[CSC] correctly. 395 */ 396 ehci->need_oc_pp_cycle = 1; 397#endif 398 399 hcd->has_tt = 1; 400 401 retval = ehci_setup(hcd); 402 if (retval) 403 return retval; 404 405 if (of_device_is_compatible(dev->parent->of_node, 406 "fsl,mpc5121-usb2-dr")) { 407 /* 408 * set SBUSCFG:AHBBRST so that control msgs don't 409 * fail when doing heavy PATA writes. 410 */ 411 ehci_writel(ehci, SBUSCFG_INCR8, 412 hcd->regs + FSL_SOC_USB_SBUSCFG); 413 } 414 415 retval = ehci_fsl_reinit(ehci); 416 return retval; 417} 418 419struct ehci_fsl { 420 struct ehci_hcd ehci; 421 422#ifdef CONFIG_PM 423 /* Saved USB PHY settings, need to restore after deep sleep. */ 424 u32 usb_ctrl; 425#endif 426}; 427 428#ifdef CONFIG_PM 429 430#ifdef CONFIG_PPC_MPC512x 431static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 432{ 433 struct usb_hcd *hcd = dev_get_drvdata(dev); 434 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 435 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 436 u32 tmp; 437 438#ifdef CONFIG_DYNAMIC_DEBUG 439 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); 440 mode &= USBMODE_CM_MASK; 441 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ 442 443 dev_dbg(dev, "suspend=%d already_suspended=%d " 444 "mode=%d usbcmd %08x\n", pdata->suspended, 445 pdata->already_suspended, mode, tmp); 446#endif 447 448 /* 449 * If the controller is already suspended, then this must be a 450 * PM suspend. Remember this fact, so that we will leave the 451 * controller suspended at PM resume time. 452 */ 453 if (pdata->suspended) { 454 dev_dbg(dev, "already suspended, leaving early\n"); 455 pdata->already_suspended = 1; 456 return 0; 457 } 458 459 dev_dbg(dev, "suspending...\n"); 460 461 ehci->rh_state = EHCI_RH_SUSPENDED; 462 dev->power.power_state = PMSG_SUSPEND; 463 464 /* ignore non-host interrupts */ 465 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 466 467 /* stop the controller */ 468 tmp = ehci_readl(ehci, &ehci->regs->command); 469 tmp &= ~CMD_RUN; 470 ehci_writel(ehci, tmp, &ehci->regs->command); 471 472 /* save EHCI registers */ 473 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); 474 pdata->pm_command &= ~CMD_RUN; 475 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); 476 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); 477 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); 478 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); 479 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); 480 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); 481 pdata->pm_configured_flag = 482 ehci_readl(ehci, &ehci->regs->configured_flag); 483 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); 484 pdata->pm_usbgenctrl = ehci_readl(ehci, 485 hcd->regs + FSL_SOC_USB_USBGENCTRL); 486 487 /* clear the W1C bits */ 488 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); 489 490 pdata->suspended = 1; 491 492 /* clear PP to cut power to the port */ 493 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); 494 tmp &= ~PORT_POWER; 495 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); 496 497 return 0; 498} 499 500static int ehci_fsl_mpc512x_drv_resume(struct device *dev) 501{ 502 struct usb_hcd *hcd = dev_get_drvdata(dev); 503 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 504 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 505 u32 tmp; 506 507 dev_dbg(dev, "suspend=%d already_suspended=%d\n", 508 pdata->suspended, pdata->already_suspended); 509 510 /* 511 * If the controller was already suspended at suspend time, 512 * then don't resume it now. 513 */ 514 if (pdata->already_suspended) { 515 dev_dbg(dev, "already suspended, leaving early\n"); 516 pdata->already_suspended = 0; 517 return 0; 518 } 519 520 if (!pdata->suspended) { 521 dev_dbg(dev, "not suspended, leaving early\n"); 522 return 0; 523 } 524 525 pdata->suspended = 0; 526 527 dev_dbg(dev, "resuming...\n"); 528 529 /* set host mode */ 530 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); 531 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); 532 533 ehci_writel(ehci, pdata->pm_usbgenctrl, 534 hcd->regs + FSL_SOC_USB_USBGENCTRL); 535 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, 536 hcd->regs + FSL_SOC_USB_ISIPHYCTRL); 537 538 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); 539 540 /* restore EHCI registers */ 541 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); 542 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); 543 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); 544 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); 545 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); 546 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); 547 ehci_writel(ehci, pdata->pm_configured_flag, 548 &ehci->regs->configured_flag); 549 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); 550 551 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 552 ehci->rh_state = EHCI_RH_RUNNING; 553 dev->power.power_state = PMSG_ON; 554 555 tmp = ehci_readl(ehci, &ehci->regs->command); 556 tmp |= CMD_RUN; 557 ehci_writel(ehci, tmp, &ehci->regs->command); 558 559 usb_hcd_resume_root_hub(hcd); 560 561 return 0; 562} 563#else 564static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 565{ 566 return 0; 567} 568 569static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) 570{ 571 return 0; 572} 573#endif /* CONFIG_PPC_MPC512x */ 574 575static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) 576{ 577 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 578 579 return container_of(ehci, struct ehci_fsl, ehci); 580} 581 582static int ehci_fsl_drv_suspend(struct device *dev) 583{ 584 struct usb_hcd *hcd = dev_get_drvdata(dev); 585 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 586 void __iomem *non_ehci = hcd->regs; 587 588 if (of_device_is_compatible(dev->parent->of_node, 589 "fsl,mpc5121-usb2-dr")) { 590 return ehci_fsl_mpc512x_drv_suspend(dev); 591 } 592 593 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), 594 device_may_wakeup(dev)); 595 if (!fsl_deep_sleep()) 596 return 0; 597 598 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 599 return 0; 600} 601 602static int ehci_fsl_drv_resume(struct device *dev) 603{ 604 struct usb_hcd *hcd = dev_get_drvdata(dev); 605 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 606 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 607 void __iomem *non_ehci = hcd->regs; 608 609 if (of_device_is_compatible(dev->parent->of_node, 610 "fsl,mpc5121-usb2-dr")) { 611 return ehci_fsl_mpc512x_drv_resume(dev); 612 } 613 614 ehci_prepare_ports_for_controller_resume(ehci); 615 if (!fsl_deep_sleep()) 616 return 0; 617 618 usb_root_hub_lost_power(hcd->self.root_hub); 619 620 /* Restore USB PHY settings and enable the controller. */ 621 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); 622 623 ehci_reset(ehci); 624 ehci_fsl_reinit(ehci); 625 626 return 0; 627} 628 629static int ehci_fsl_drv_restore(struct device *dev) 630{ 631 struct usb_hcd *hcd = dev_get_drvdata(dev); 632 633 usb_root_hub_lost_power(hcd->self.root_hub); 634 return 0; 635} 636 637static const struct dev_pm_ops ehci_fsl_pm_ops = { 638 .suspend = ehci_fsl_drv_suspend, 639 .resume = ehci_fsl_drv_resume, 640 .restore = ehci_fsl_drv_restore, 641}; 642 643#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) 644#else 645#define EHCI_FSL_PM_OPS NULL 646#endif /* CONFIG_PM */ 647 648#ifdef CONFIG_USB_OTG 649static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) 650{ 651 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 652 u32 status; 653 654 if (!port) 655 return -EINVAL; 656 657 port--; 658 659 /* start port reset before HNP protocol time out */ 660 status = readl(&ehci->regs->port_status[port]); 661 if (!(status & PORT_CONNECT)) 662 return -ENODEV; 663 664 /* hub_wq will finish the reset later */ 665 if (ehci_is_TDI(ehci)) { 666 writel(PORT_RESET | 667 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), 668 &ehci->regs->port_status[port]); 669 } else { 670 writel(PORT_RESET, &ehci->regs->port_status[port]); 671 } 672 673 return 0; 674} 675#else 676#define ehci_start_port_reset NULL 677#endif /* CONFIG_USB_OTG */ 678 679static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { 680 .extra_priv_size = sizeof(struct ehci_fsl), 681 .reset = ehci_fsl_setup, 682}; 683 684/** 685 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs 686 * @pdev: USB Host Controller being removed 687 * Context: !in_interrupt() 688 * 689 * Reverses the effect of usb_hcd_fsl_probe(). 690 * 691 */ 692 693static int fsl_ehci_drv_remove(struct platform_device *pdev) 694{ 695 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 696 struct usb_hcd *hcd = platform_get_drvdata(pdev); 697 698 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 699 otg_set_host(hcd->usb_phy->otg, NULL); 700 usb_put_phy(hcd->usb_phy); 701 } 702 703 usb_remove_hcd(hcd); 704 705 /* 706 * do platform specific un-initialization: 707 * release iomux pins, disable clock, etc. 708 */ 709 if (pdata->exit) 710 pdata->exit(pdev); 711 usb_put_hcd(hcd); 712 713 return 0; 714} 715 716static struct platform_driver ehci_fsl_driver = { 717 .probe = fsl_ehci_drv_probe, 718 .remove = fsl_ehci_drv_remove, 719 .shutdown = usb_hcd_platform_shutdown, 720 .driver = { 721 .name = "fsl-ehci", 722 .pm = EHCI_FSL_PM_OPS, 723 }, 724}; 725 726static int __init ehci_fsl_init(void) 727{ 728 if (usb_disabled()) 729 return -ENODEV; 730 731 pr_info(DRV_NAME ": " DRIVER_DESC "\n"); 732 733 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); 734 735 fsl_ehci_hc_driver.product_desc = 736 "Freescale On-Chip EHCI Host Controller"; 737 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; 738 739 740 return platform_driver_register(&ehci_fsl_driver); 741} 742module_init(ehci_fsl_init); 743 744static void __exit ehci_fsl_cleanup(void) 745{ 746 platform_driver_unregister(&ehci_fsl_driver); 747} 748module_exit(ehci_fsl_cleanup); 749 750MODULE_DESCRIPTION(DRIVER_DESC); 751MODULE_LICENSE("GPL"); 752MODULE_ALIAS("platform:" DRV_NAME); 753