1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Xilinx USB peripheral controller driver 4 * 5 * Copyright (C) 2004 by Thomas Rathbone 6 * Copyright (C) 2005 by HP Labs 7 * Copyright (C) 2005 by David Brownell 8 * Copyright (C) 2010 - 2014 Xilinx, Inc. 9 * 10 * Some parts of this driver code is based on the driver for at91-series 11 * USB peripheral controller (at91_udc.c). 12 */ 13 14#include <linux/delay.h> 15#include <linux/device.h> 16#include <linux/dma-mapping.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/module.h> 20#include <linux/of_address.h> 21#include <linux/of_device.h> 22#include <linux/of_platform.h> 23#include <linux/of_irq.h> 24#include <linux/prefetch.h> 25#include <linux/usb/ch9.h> 26#include <linux/usb/gadget.h> 27 28/* Register offsets for the USB device.*/ 29#define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */ 30#define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */ 31#define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */ 32#define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */ 33#define XUSB_STATUS_OFFSET 0x0108 /* Status Register */ 34#define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */ 35#define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */ 36#define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */ 37#define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */ 38#define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */ 39#define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */ 40#define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */ 41#define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */ 42#define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */ 43#define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */ 44 45/* Endpoint Configuration Space offsets */ 46#define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */ 47#define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */ 48#define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */ 49 50#define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */ 51#define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */ 52 53/* Interrupt register related masks.*/ 54#define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */ 55#define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */ 56#define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */ 57#define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */ 58#define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */ 59#define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */ 60#define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */ 61#define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */ 62#define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */ 63#define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */ 64#define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */ 65#define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */ 66#define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */ 67#define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */ 68#define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */ 69#define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */ 70/* Suspend,Reset,Suspend and Disconnect Mask */ 71#define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000 72/* Buffers completion Mask */ 73#define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF 74/* Mask for buffer 0 and buffer 1 completion for all Endpoints */ 75#define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101 76#define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */ 77 78/* Endpoint Configuration Status Register */ 79#define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */ 80#define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */ 81#define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */ 82 83/* USB device specific global configuration constants.*/ 84#define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */ 85#define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */ 86/* DPRAM is the source address for DMA transfer */ 87#define XUSB_DMA_READ_FROM_DPRAM 0x80000000 88#define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */ 89#define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */ 90/* 91 * When this bit is set, the DMA buffer ready bit is set by hardware upon 92 * DMA transfer completion. 93 */ 94#define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */ 95/* Phase States */ 96#define SETUP_PHASE 0x0000 /* Setup Phase */ 97#define DATA_PHASE 0x0001 /* Data Phase */ 98#define STATUS_PHASE 0x0002 /* Status Phase */ 99 100#define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */ 101#define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */ 102#define EPNAME_SIZE 4 /* Buffer size for endpoint name */ 103 104/* container_of helper macros */ 105#define to_udc(g) container_of((g), struct xusb_udc, gadget) 106#define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb) 107#define to_xusb_req(req) container_of((req), struct xusb_req, usb_req) 108 109/** 110 * struct xusb_req - Xilinx USB device request structure 111 * @usb_req: Linux usb request structure 112 * @queue: usb device request queue 113 * @ep: pointer to xusb_endpoint structure 114 */ 115struct xusb_req { 116 struct usb_request usb_req; 117 struct list_head queue; 118 struct xusb_ep *ep; 119}; 120 121/** 122 * struct xusb_ep - USB end point structure. 123 * @ep_usb: usb endpoint instance 124 * @queue: endpoint message queue 125 * @udc: xilinx usb peripheral driver instance pointer 126 * @desc: pointer to the usb endpoint descriptor 127 * @rambase: the endpoint buffer address 128 * @offset: the endpoint register offset value 129 * @name: name of the endpoint 130 * @epnumber: endpoint number 131 * @maxpacket: maximum packet size the endpoint can store 132 * @buffer0count: the size of the packet recieved in the first buffer 133 * @buffer1count: the size of the packet received in the second buffer 134 * @curbufnum: current buffer of endpoint that will be processed next 135 * @buffer0ready: the busy state of first buffer 136 * @buffer1ready: the busy state of second buffer 137 * @is_in: endpoint direction (IN or OUT) 138 * @is_iso: endpoint type(isochronous or non isochronous) 139 */ 140struct xusb_ep { 141 struct usb_ep ep_usb; 142 struct list_head queue; 143 struct xusb_udc *udc; 144 const struct usb_endpoint_descriptor *desc; 145 u32 rambase; 146 u32 offset; 147 char name[4]; 148 u16 epnumber; 149 u16 maxpacket; 150 u16 buffer0count; 151 u16 buffer1count; 152 u8 curbufnum; 153 bool buffer0ready; 154 bool buffer1ready; 155 bool is_in; 156 bool is_iso; 157}; 158 159/** 160 * struct xusb_udc - USB peripheral driver structure 161 * @gadget: USB gadget driver instance 162 * @ep: an array of endpoint structures 163 * @driver: pointer to the usb gadget driver instance 164 * @setup: usb_ctrlrequest structure for control requests 165 * @req: pointer to dummy request for get status command 166 * @dev: pointer to device structure in gadget 167 * @usb_state: device in suspended state or not 168 * @remote_wkp: remote wakeup enabled by host 169 * @setupseqtx: tx status 170 * @setupseqrx: rx status 171 * @addr: the usb device base address 172 * @lock: instance of spinlock 173 * @dma_enabled: flag indicating whether the dma is included in the system 174 * @read_fn: function pointer to read device registers 175 * @write_fn: function pointer to write to device registers 176 */ 177struct xusb_udc { 178 struct usb_gadget gadget; 179 struct xusb_ep ep[8]; 180 struct usb_gadget_driver *driver; 181 struct usb_ctrlrequest setup; 182 struct xusb_req *req; 183 struct device *dev; 184 u32 usb_state; 185 u32 remote_wkp; 186 u32 setupseqtx; 187 u32 setupseqrx; 188 void __iomem *addr; 189 spinlock_t lock; 190 bool dma_enabled; 191 192 unsigned int (*read_fn)(void __iomem *); 193 void (*write_fn)(void __iomem *, u32, u32); 194}; 195 196/* Endpoint buffer start addresses in the core */ 197static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 198 0x1600 }; 199 200static const char driver_name[] = "xilinx-udc"; 201static const char ep0name[] = "ep0"; 202 203/* Control endpoint configuration.*/ 204static const struct usb_endpoint_descriptor config_bulk_out_desc = { 205 .bLength = USB_DT_ENDPOINT_SIZE, 206 .bDescriptorType = USB_DT_ENDPOINT, 207 .bEndpointAddress = USB_DIR_OUT, 208 .bmAttributes = USB_ENDPOINT_XFER_BULK, 209 .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET), 210}; 211 212/** 213 * xudc_write32 - little endian write to device registers 214 * @addr: base addr of device registers 215 * @offset: register offset 216 * @val: data to be written 217 */ 218static void xudc_write32(void __iomem *addr, u32 offset, u32 val) 219{ 220 iowrite32(val, addr + offset); 221} 222 223/** 224 * xudc_read32 - little endian read from device registers 225 * @addr: addr of device register 226 * Return: value at addr 227 */ 228static unsigned int xudc_read32(void __iomem *addr) 229{ 230 return ioread32(addr); 231} 232 233/** 234 * xudc_write32_be - big endian write to device registers 235 * @addr: base addr of device registers 236 * @offset: register offset 237 * @val: data to be written 238 */ 239static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val) 240{ 241 iowrite32be(val, addr + offset); 242} 243 244/** 245 * xudc_read32_be - big endian read from device registers 246 * @addr: addr of device register 247 * Return: value at addr 248 */ 249static unsigned int xudc_read32_be(void __iomem *addr) 250{ 251 return ioread32be(addr); 252} 253 254/** 255 * xudc_wrstatus - Sets up the usb device status stages. 256 * @udc: pointer to the usb device controller structure. 257 */ 258static void xudc_wrstatus(struct xusb_udc *udc) 259{ 260 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 261 u32 epcfgreg; 262 263 epcfgreg = udc->read_fn(udc->addr + ep0->offset)| 264 XUSB_EP_CFG_DATA_TOGGLE_MASK; 265 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 266 udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0); 267 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 268} 269 270/** 271 * xudc_epconfig - Configures the given endpoint. 272 * @ep: pointer to the usb device endpoint structure. 273 * @udc: pointer to the usb peripheral controller structure. 274 * 275 * This function configures a specific endpoint with the given configuration 276 * data. 277 */ 278static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc) 279{ 280 u32 epcfgreg; 281 282 /* 283 * Configure the end point direction, type, Max Packet Size and the 284 * EP buffer location. 285 */ 286 epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) | 287 (ep->ep_usb.maxpacket << 15) | (ep->rambase)); 288 udc->write_fn(udc->addr, ep->offset, epcfgreg); 289 290 /* Set the Buffer count and the Buffer ready bits.*/ 291 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, 292 ep->buffer0count); 293 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, 294 ep->buffer1count); 295 if (ep->buffer0ready) 296 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 297 1 << ep->epnumber); 298 if (ep->buffer1ready) 299 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 300 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 301} 302 303/** 304 * xudc_start_dma - Starts DMA transfer. 305 * @ep: pointer to the usb device endpoint structure. 306 * @src: DMA source address. 307 * @dst: DMA destination address. 308 * @length: number of bytes to transfer. 309 * 310 * Return: 0 on success, error code on failure 311 * 312 * This function starts DMA transfer by writing to DMA source, 313 * destination and lenth registers. 314 */ 315static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src, 316 dma_addr_t dst, u32 length) 317{ 318 struct xusb_udc *udc = ep->udc; 319 int rc = 0; 320 u32 timeout = 500; 321 u32 reg; 322 323 /* 324 * Set the addresses in the DMA source and 325 * destination registers and then set the length 326 * into the DMA length register. 327 */ 328 udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src); 329 udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst); 330 udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length); 331 332 /* 333 * Wait till DMA transaction is complete and 334 * check whether the DMA transaction was 335 * successful. 336 */ 337 do { 338 reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET); 339 if (!(reg & XUSB_DMA_DMASR_BUSY)) 340 break; 341 342 /* 343 * We can't sleep here, because it's also called from 344 * interrupt context. 345 */ 346 timeout--; 347 if (!timeout) { 348 dev_err(udc->dev, "DMA timeout\n"); 349 return -ETIMEDOUT; 350 } 351 udelay(1); 352 } while (1); 353 354 if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) & 355 XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){ 356 dev_err(udc->dev, "DMA Error\n"); 357 rc = -EINVAL; 358 } 359 360 return rc; 361} 362 363/** 364 * xudc_dma_send - Sends IN data using DMA. 365 * @ep: pointer to the usb device endpoint structure. 366 * @req: pointer to the usb request structure. 367 * @buffer: pointer to data to be sent. 368 * @length: number of bytes to send. 369 * 370 * Return: 0 on success, -EAGAIN if no buffer is free and error 371 * code on failure. 372 * 373 * This function sends data using DMA. 374 */ 375static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req, 376 u8 *buffer, u32 length) 377{ 378 u32 *eprambase; 379 dma_addr_t src; 380 dma_addr_t dst; 381 struct xusb_udc *udc = ep->udc; 382 383 src = req->usb_req.dma + req->usb_req.actual; 384 if (req->usb_req.length) 385 dma_sync_single_for_device(udc->dev, src, 386 length, DMA_TO_DEVICE); 387 if (!ep->curbufnum && !ep->buffer0ready) { 388 /* Get the Buffer address and copy the transmit data.*/ 389 eprambase = (u32 __force *)(udc->addr + ep->rambase); 390 dst = virt_to_phys(eprambase); 391 udc->write_fn(udc->addr, ep->offset + 392 XUSB_EP_BUF0COUNT_OFFSET, length); 393 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 394 XUSB_DMA_BRR_CTRL | (1 << ep->epnumber)); 395 ep->buffer0ready = 1; 396 ep->curbufnum = 1; 397 } else if (ep->curbufnum && !ep->buffer1ready) { 398 /* Get the Buffer address and copy the transmit data.*/ 399 eprambase = (u32 __force *)(udc->addr + ep->rambase + 400 ep->ep_usb.maxpacket); 401 dst = virt_to_phys(eprambase); 402 udc->write_fn(udc->addr, ep->offset + 403 XUSB_EP_BUF1COUNT_OFFSET, length); 404 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 405 XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber + 406 XUSB_STATUS_EP_BUFF2_SHIFT))); 407 ep->buffer1ready = 1; 408 ep->curbufnum = 0; 409 } else { 410 /* None of ping pong buffers are ready currently .*/ 411 return -EAGAIN; 412 } 413 414 return xudc_start_dma(ep, src, dst, length); 415} 416 417/** 418 * xudc_dma_receive - Receives OUT data using DMA. 419 * @ep: pointer to the usb device endpoint structure. 420 * @req: pointer to the usb request structure. 421 * @buffer: pointer to storage buffer of received data. 422 * @length: number of bytes to receive. 423 * 424 * Return: 0 on success, -EAGAIN if no buffer is free and error 425 * code on failure. 426 * 427 * This function receives data using DMA. 428 */ 429static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req, 430 u8 *buffer, u32 length) 431{ 432 u32 *eprambase; 433 dma_addr_t src; 434 dma_addr_t dst; 435 struct xusb_udc *udc = ep->udc; 436 437 dst = req->usb_req.dma + req->usb_req.actual; 438 if (!ep->curbufnum && !ep->buffer0ready) { 439 /* Get the Buffer address and copy the transmit data */ 440 eprambase = (u32 __force *)(udc->addr + ep->rambase); 441 src = virt_to_phys(eprambase); 442 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 443 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 444 (1 << ep->epnumber)); 445 ep->buffer0ready = 1; 446 ep->curbufnum = 1; 447 } else if (ep->curbufnum && !ep->buffer1ready) { 448 /* Get the Buffer address and copy the transmit data */ 449 eprambase = (u32 __force *)(udc->addr + 450 ep->rambase + ep->ep_usb.maxpacket); 451 src = virt_to_phys(eprambase); 452 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 453 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 454 (1 << (ep->epnumber + 455 XUSB_STATUS_EP_BUFF2_SHIFT))); 456 ep->buffer1ready = 1; 457 ep->curbufnum = 0; 458 } else { 459 /* None of the ping-pong buffers are ready currently */ 460 return -EAGAIN; 461 } 462 463 return xudc_start_dma(ep, src, dst, length); 464} 465 466/** 467 * xudc_eptxrx - Transmits or receives data to or from an endpoint. 468 * @ep: pointer to the usb endpoint configuration structure. 469 * @req: pointer to the usb request structure. 470 * @bufferptr: pointer to buffer containing the data to be sent. 471 * @bufferlen: The number of data bytes to be sent. 472 * 473 * Return: 0 on success, -EAGAIN if no buffer is free. 474 * 475 * This function copies the transmit/receive data to/from the end point buffer 476 * and enables the buffer for transmission/reception. 477 */ 478static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, 479 u8 *bufferptr, u32 bufferlen) 480{ 481 u32 *eprambase; 482 u32 bytestosend; 483 int rc = 0; 484 struct xusb_udc *udc = ep->udc; 485 486 bytestosend = bufferlen; 487 if (udc->dma_enabled) { 488 if (ep->is_in) 489 rc = xudc_dma_send(ep, req, bufferptr, bufferlen); 490 else 491 rc = xudc_dma_receive(ep, req, bufferptr, bufferlen); 492 return rc; 493 } 494 /* Put the transmit buffer into the correct ping-pong buffer.*/ 495 if (!ep->curbufnum && !ep->buffer0ready) { 496 /* Get the Buffer address and copy the transmit data.*/ 497 eprambase = (u32 __force *)(udc->addr + ep->rambase); 498 if (ep->is_in) { 499 memcpy_toio((void __iomem *)eprambase, bufferptr, 500 bytestosend); 501 udc->write_fn(udc->addr, ep->offset + 502 XUSB_EP_BUF0COUNT_OFFSET, bufferlen); 503 } else { 504 memcpy_toio((void __iomem *)bufferptr, eprambase, 505 bytestosend); 506 } 507 /* 508 * Enable the buffer for transmission. 509 */ 510 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 511 1 << ep->epnumber); 512 ep->buffer0ready = 1; 513 ep->curbufnum = 1; 514 } else if (ep->curbufnum && !ep->buffer1ready) { 515 /* Get the Buffer address and copy the transmit data.*/ 516 eprambase = (u32 __force *)(udc->addr + ep->rambase + 517 ep->ep_usb.maxpacket); 518 if (ep->is_in) { 519 memcpy_toio((void __iomem *)eprambase, bufferptr, 520 bytestosend); 521 udc->write_fn(udc->addr, ep->offset + 522 XUSB_EP_BUF1COUNT_OFFSET, bufferlen); 523 } else { 524 memcpy_toio((void __iomem *)bufferptr, eprambase, 525 bytestosend); 526 } 527 /* 528 * Enable the buffer for transmission. 529 */ 530 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 531 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 532 ep->buffer1ready = 1; 533 ep->curbufnum = 0; 534 } else { 535 /* None of the ping-pong buffers are ready currently */ 536 return -EAGAIN; 537 } 538 return rc; 539} 540 541/** 542 * xudc_done - Exeutes the endpoint data transfer completion tasks. 543 * @ep: pointer to the usb device endpoint structure. 544 * @req: pointer to the usb request structure. 545 * @status: Status of the data transfer. 546 * 547 * Deletes the message from the queue and updates data transfer completion 548 * status. 549 */ 550static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status) 551{ 552 struct xusb_udc *udc = ep->udc; 553 554 list_del_init(&req->queue); 555 556 if (req->usb_req.status == -EINPROGRESS) 557 req->usb_req.status = status; 558 else 559 status = req->usb_req.status; 560 561 if (status && status != -ESHUTDOWN) 562 dev_dbg(udc->dev, "%s done %p, status %d\n", 563 ep->ep_usb.name, req, status); 564 /* unmap request if DMA is present*/ 565 if (udc->dma_enabled && ep->epnumber && req->usb_req.length) 566 usb_gadget_unmap_request(&udc->gadget, &req->usb_req, 567 ep->is_in); 568 569 if (req->usb_req.complete) { 570 spin_unlock(&udc->lock); 571 req->usb_req.complete(&ep->ep_usb, &req->usb_req); 572 spin_lock(&udc->lock); 573 } 574} 575 576/** 577 * xudc_read_fifo - Reads the data from the given endpoint buffer. 578 * @ep: pointer to the usb device endpoint structure. 579 * @req: pointer to the usb request structure. 580 * 581 * Return: 0 if request is completed and -EAGAIN if not completed. 582 * 583 * Pulls OUT packet data from the endpoint buffer. 584 */ 585static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req) 586{ 587 u8 *buf; 588 u32 is_short, count, bufferspace; 589 u8 bufoffset; 590 u8 two_pkts = 0; 591 int ret; 592 int retval = -EAGAIN; 593 struct xusb_udc *udc = ep->udc; 594 595 if (ep->buffer0ready && ep->buffer1ready) { 596 dev_dbg(udc->dev, "Packet NOT ready!\n"); 597 return retval; 598 } 599top: 600 if (ep->curbufnum) 601 bufoffset = XUSB_EP_BUF1COUNT_OFFSET; 602 else 603 bufoffset = XUSB_EP_BUF0COUNT_OFFSET; 604 605 count = udc->read_fn(udc->addr + ep->offset + bufoffset); 606 607 if (!ep->buffer0ready && !ep->buffer1ready) 608 two_pkts = 1; 609 610 buf = req->usb_req.buf + req->usb_req.actual; 611 prefetchw(buf); 612 bufferspace = req->usb_req.length - req->usb_req.actual; 613 is_short = count < ep->ep_usb.maxpacket; 614 615 if (unlikely(!bufferspace)) { 616 /* 617 * This happens when the driver's buffer 618 * is smaller than what the host sent. 619 * discard the extra data. 620 */ 621 if (req->usb_req.status != -EOVERFLOW) 622 dev_dbg(udc->dev, "%s overflow %d\n", 623 ep->ep_usb.name, count); 624 req->usb_req.status = -EOVERFLOW; 625 xudc_done(ep, req, -EOVERFLOW); 626 return 0; 627 } 628 629 ret = xudc_eptxrx(ep, req, buf, count); 630 switch (ret) { 631 case 0: 632 req->usb_req.actual += min(count, bufferspace); 633 dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n", 634 ep->ep_usb.name, count, is_short ? "/S" : "", req, 635 req->usb_req.actual, req->usb_req.length); 636 bufferspace -= count; 637 /* Completion */ 638 if ((req->usb_req.actual == req->usb_req.length) || is_short) { 639 if (udc->dma_enabled && req->usb_req.length) 640 dma_sync_single_for_cpu(udc->dev, 641 req->usb_req.dma, 642 req->usb_req.actual, 643 DMA_FROM_DEVICE); 644 xudc_done(ep, req, 0); 645 return 0; 646 } 647 if (two_pkts) { 648 two_pkts = 0; 649 goto top; 650 } 651 break; 652 case -EAGAIN: 653 dev_dbg(udc->dev, "receive busy\n"); 654 break; 655 case -EINVAL: 656 case -ETIMEDOUT: 657 /* DMA error, dequeue the request */ 658 xudc_done(ep, req, -ECONNRESET); 659 retval = 0; 660 break; 661 } 662 663 return retval; 664} 665 666/** 667 * xudc_write_fifo - Writes data into the given endpoint buffer. 668 * @ep: pointer to the usb device endpoint structure. 669 * @req: pointer to the usb request structure. 670 * 671 * Return: 0 if request is completed and -EAGAIN if not completed. 672 * 673 * Loads endpoint buffer for an IN packet. 674 */ 675static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req) 676{ 677 u32 max; 678 u32 length; 679 int ret; 680 int retval = -EAGAIN; 681 struct xusb_udc *udc = ep->udc; 682 int is_last, is_short = 0; 683 u8 *buf; 684 685 max = le16_to_cpu(ep->desc->wMaxPacketSize); 686 buf = req->usb_req.buf + req->usb_req.actual; 687 prefetch(buf); 688 length = req->usb_req.length - req->usb_req.actual; 689 length = min(length, max); 690 691 ret = xudc_eptxrx(ep, req, buf, length); 692 switch (ret) { 693 case 0: 694 req->usb_req.actual += length; 695 if (unlikely(length != max)) { 696 is_last = is_short = 1; 697 } else { 698 if (likely(req->usb_req.length != 699 req->usb_req.actual) || req->usb_req.zero) 700 is_last = 0; 701 else 702 is_last = 1; 703 } 704 dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n", 705 __func__, ep->ep_usb.name, length, is_last ? "/L" : "", 706 is_short ? "/S" : "", 707 req->usb_req.length - req->usb_req.actual, req); 708 /* completion */ 709 if (is_last) { 710 xudc_done(ep, req, 0); 711 retval = 0; 712 } 713 break; 714 case -EAGAIN: 715 dev_dbg(udc->dev, "Send busy\n"); 716 break; 717 case -EINVAL: 718 case -ETIMEDOUT: 719 /* DMA error, dequeue the request */ 720 xudc_done(ep, req, -ECONNRESET); 721 retval = 0; 722 break; 723 } 724 725 return retval; 726} 727 728/** 729 * xudc_nuke - Cleans up the data transfer message list. 730 * @ep: pointer to the usb device endpoint structure. 731 * @status: Status of the data transfer. 732 */ 733static void xudc_nuke(struct xusb_ep *ep, int status) 734{ 735 struct xusb_req *req; 736 737 while (!list_empty(&ep->queue)) { 738 req = list_first_entry(&ep->queue, struct xusb_req, queue); 739 xudc_done(ep, req, status); 740 } 741} 742 743/** 744 * xudc_ep_set_halt - Stalls/unstalls the given endpoint. 745 * @_ep: pointer to the usb device endpoint structure. 746 * @value: value to indicate stall/unstall. 747 * 748 * Return: 0 for success and error value on failure 749 */ 750static int xudc_ep_set_halt(struct usb_ep *_ep, int value) 751{ 752 struct xusb_ep *ep = to_xusb_ep(_ep); 753 struct xusb_udc *udc; 754 unsigned long flags; 755 u32 epcfgreg; 756 757 if (!_ep || (!ep->desc && ep->epnumber)) { 758 pr_debug("%s: bad ep or descriptor\n", __func__); 759 return -EINVAL; 760 } 761 udc = ep->udc; 762 763 if (ep->is_in && (!list_empty(&ep->queue)) && value) { 764 dev_dbg(udc->dev, "requests pending can't halt\n"); 765 return -EAGAIN; 766 } 767 768 if (ep->buffer0ready || ep->buffer1ready) { 769 dev_dbg(udc->dev, "HW buffers busy can't halt\n"); 770 return -EAGAIN; 771 } 772 773 spin_lock_irqsave(&udc->lock, flags); 774 775 if (value) { 776 /* Stall the device.*/ 777 epcfgreg = udc->read_fn(udc->addr + ep->offset); 778 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 779 udc->write_fn(udc->addr, ep->offset, epcfgreg); 780 } else { 781 /* Unstall the device.*/ 782 epcfgreg = udc->read_fn(udc->addr + ep->offset); 783 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 784 udc->write_fn(udc->addr, ep->offset, epcfgreg); 785 if (ep->epnumber) { 786 /* Reset the toggle bit.*/ 787 epcfgreg = udc->read_fn(ep->udc->addr + ep->offset); 788 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 789 udc->write_fn(udc->addr, ep->offset, epcfgreg); 790 } 791 } 792 793 spin_unlock_irqrestore(&udc->lock, flags); 794 return 0; 795} 796 797/** 798 * xudc_ep_enable - Enables the given endpoint. 799 * @ep: pointer to the xusb endpoint structure. 800 * @desc: pointer to usb endpoint descriptor. 801 * 802 * Return: 0 for success and error value on failure 803 */ 804static int __xudc_ep_enable(struct xusb_ep *ep, 805 const struct usb_endpoint_descriptor *desc) 806{ 807 struct xusb_udc *udc = ep->udc; 808 u32 tmp; 809 u32 epcfg; 810 u32 ier; 811 u16 maxpacket; 812 813 ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0); 814 /* Bit 3...0:endpoint number */ 815 ep->epnumber = (desc->bEndpointAddress & 0x0f); 816 ep->desc = desc; 817 ep->ep_usb.desc = desc; 818 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 819 ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize); 820 821 switch (tmp) { 822 case USB_ENDPOINT_XFER_CONTROL: 823 dev_dbg(udc->dev, "only one control endpoint\n"); 824 /* NON- ISO */ 825 ep->is_iso = 0; 826 return -EINVAL; 827 case USB_ENDPOINT_XFER_INT: 828 /* NON- ISO */ 829 ep->is_iso = 0; 830 if (maxpacket > 64) { 831 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 832 return -EINVAL; 833 } 834 break; 835 case USB_ENDPOINT_XFER_BULK: 836 /* NON- ISO */ 837 ep->is_iso = 0; 838 if (!(is_power_of_2(maxpacket) && maxpacket >= 8 && 839 maxpacket <= 512)) { 840 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 841 return -EINVAL; 842 } 843 break; 844 case USB_ENDPOINT_XFER_ISOC: 845 /* ISO */ 846 ep->is_iso = 1; 847 break; 848 } 849 850 ep->buffer0ready = 0; 851 ep->buffer1ready = 0; 852 ep->curbufnum = 0; 853 ep->rambase = rambase[ep->epnumber]; 854 xudc_epconfig(ep, udc); 855 856 dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n", 857 ep->epnumber, maxpacket); 858 859 /* Enable the End point.*/ 860 epcfg = udc->read_fn(udc->addr + ep->offset); 861 epcfg |= XUSB_EP_CFG_VALID_MASK; 862 udc->write_fn(udc->addr, ep->offset, epcfg); 863 if (ep->epnumber) 864 ep->rambase <<= 2; 865 866 /* Enable buffer completion interrupts for endpoint */ 867 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 868 ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber); 869 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 870 871 /* for OUT endpoint set buffers ready to receive */ 872 if (ep->epnumber && !ep->is_in) { 873 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 874 1 << ep->epnumber); 875 ep->buffer0ready = 1; 876 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 877 (1 << (ep->epnumber + 878 XUSB_STATUS_EP_BUFF2_SHIFT))); 879 ep->buffer1ready = 1; 880 } 881 882 return 0; 883} 884 885/** 886 * xudc_ep_enable - Enables the given endpoint. 887 * @_ep: pointer to the usb endpoint structure. 888 * @desc: pointer to usb endpoint descriptor. 889 * 890 * Return: 0 for success and error value on failure 891 */ 892static int xudc_ep_enable(struct usb_ep *_ep, 893 const struct usb_endpoint_descriptor *desc) 894{ 895 struct xusb_ep *ep; 896 struct xusb_udc *udc; 897 unsigned long flags; 898 int ret; 899 900 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 901 pr_debug("%s: bad ep or descriptor\n", __func__); 902 return -EINVAL; 903 } 904 905 ep = to_xusb_ep(_ep); 906 udc = ep->udc; 907 908 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 909 dev_dbg(udc->dev, "bogus device state\n"); 910 return -ESHUTDOWN; 911 } 912 913 spin_lock_irqsave(&udc->lock, flags); 914 ret = __xudc_ep_enable(ep, desc); 915 spin_unlock_irqrestore(&udc->lock, flags); 916 917 return ret; 918} 919 920/** 921 * xudc_ep_disable - Disables the given endpoint. 922 * @_ep: pointer to the usb endpoint structure. 923 * 924 * Return: 0 for success and error value on failure 925 */ 926static int xudc_ep_disable(struct usb_ep *_ep) 927{ 928 struct xusb_ep *ep; 929 unsigned long flags; 930 u32 epcfg; 931 struct xusb_udc *udc; 932 933 if (!_ep) { 934 pr_debug("%s: invalid ep\n", __func__); 935 return -EINVAL; 936 } 937 938 ep = to_xusb_ep(_ep); 939 udc = ep->udc; 940 941 spin_lock_irqsave(&udc->lock, flags); 942 943 xudc_nuke(ep, -ESHUTDOWN); 944 945 /* Restore the endpoint's pristine config */ 946 ep->desc = NULL; 947 ep->ep_usb.desc = NULL; 948 949 dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber); 950 /* Disable the endpoint.*/ 951 epcfg = udc->read_fn(udc->addr + ep->offset); 952 epcfg &= ~XUSB_EP_CFG_VALID_MASK; 953 udc->write_fn(udc->addr, ep->offset, epcfg); 954 955 spin_unlock_irqrestore(&udc->lock, flags); 956 return 0; 957} 958 959/** 960 * xudc_ep_alloc_request - Initializes the request queue. 961 * @_ep: pointer to the usb endpoint structure. 962 * @gfp_flags: Flags related to the request call. 963 * 964 * Return: pointer to request structure on success and a NULL on failure. 965 */ 966static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep, 967 gfp_t gfp_flags) 968{ 969 struct xusb_ep *ep = to_xusb_ep(_ep); 970 struct xusb_req *req; 971 972 req = kzalloc(sizeof(*req), gfp_flags); 973 if (!req) 974 return NULL; 975 976 req->ep = ep; 977 INIT_LIST_HEAD(&req->queue); 978 return &req->usb_req; 979} 980 981/** 982 * xudc_free_request - Releases the request from queue. 983 * @_ep: pointer to the usb device endpoint structure. 984 * @_req: pointer to the usb request structure. 985 */ 986static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req) 987{ 988 struct xusb_req *req = to_xusb_req(_req); 989 990 kfree(req); 991} 992 993/** 994 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 995 * @ep0: pointer to the xusb endpoint 0 structure. 996 * @req: pointer to the xusb request structure. 997 * 998 * Return: 0 for success and error value on failure 999 */ 1000static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) 1001{ 1002 struct xusb_udc *udc = ep0->udc; 1003 u32 length; 1004 u8 *corebuf; 1005 1006 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1007 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1008 return -EINVAL; 1009 } 1010 if (!list_empty(&ep0->queue)) { 1011 dev_dbg(udc->dev, "%s:ep0 busy\n", __func__); 1012 return -EBUSY; 1013 } 1014 1015 req->usb_req.status = -EINPROGRESS; 1016 req->usb_req.actual = 0; 1017 1018 list_add_tail(&req->queue, &ep0->queue); 1019 1020 if (udc->setup.bRequestType & USB_DIR_IN) { 1021 prefetch(req->usb_req.buf); 1022 length = req->usb_req.length; 1023 corebuf = (void __force *) ((ep0->rambase << 2) + 1024 udc->addr); 1025 length = req->usb_req.actual = min_t(u32, length, 1026 EP0_MAX_PACKET); 1027 memcpy_toio((void __iomem *)corebuf, req->usb_req.buf, length); 1028 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); 1029 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1030 } else { 1031 if (udc->setup.wLength) { 1032 /* Enable EP0 buffer to receive data */ 1033 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1034 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1035 } else { 1036 xudc_wrstatus(udc); 1037 } 1038 } 1039 1040 return 0; 1041} 1042 1043/** 1044 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 1045 * @_ep: pointer to the usb endpoint 0 structure. 1046 * @_req: pointer to the usb request structure. 1047 * @gfp_flags: Flags related to the request call. 1048 * 1049 * Return: 0 for success and error value on failure 1050 */ 1051static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req, 1052 gfp_t gfp_flags) 1053{ 1054 struct xusb_req *req = to_xusb_req(_req); 1055 struct xusb_ep *ep0 = to_xusb_ep(_ep); 1056 struct xusb_udc *udc = ep0->udc; 1057 unsigned long flags; 1058 int ret; 1059 1060 spin_lock_irqsave(&udc->lock, flags); 1061 ret = __xudc_ep0_queue(ep0, req); 1062 spin_unlock_irqrestore(&udc->lock, flags); 1063 1064 return ret; 1065} 1066 1067/** 1068 * xudc_ep_queue - Adds the request to endpoint queue. 1069 * @_ep: pointer to the usb endpoint structure. 1070 * @_req: pointer to the usb request structure. 1071 * @gfp_flags: Flags related to the request call. 1072 * 1073 * Return: 0 for success and error value on failure 1074 */ 1075static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1076 gfp_t gfp_flags) 1077{ 1078 struct xusb_req *req = to_xusb_req(_req); 1079 struct xusb_ep *ep = to_xusb_ep(_ep); 1080 struct xusb_udc *udc = ep->udc; 1081 int ret; 1082 unsigned long flags; 1083 1084 if (!ep->desc) { 1085 dev_dbg(udc->dev, "%s: queuing request to disabled %s\n", 1086 __func__, ep->name); 1087 return -ESHUTDOWN; 1088 } 1089 1090 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1091 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1092 return -EINVAL; 1093 } 1094 1095 spin_lock_irqsave(&udc->lock, flags); 1096 1097 _req->status = -EINPROGRESS; 1098 _req->actual = 0; 1099 1100 if (udc->dma_enabled) { 1101 ret = usb_gadget_map_request(&udc->gadget, &req->usb_req, 1102 ep->is_in); 1103 if (ret) { 1104 dev_dbg(udc->dev, "gadget_map failed ep%d\n", 1105 ep->epnumber); 1106 spin_unlock_irqrestore(&udc->lock, flags); 1107 return -EAGAIN; 1108 } 1109 } 1110 1111 if (list_empty(&ep->queue)) { 1112 if (ep->is_in) { 1113 dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n"); 1114 if (!xudc_write_fifo(ep, req)) 1115 req = NULL; 1116 } else { 1117 dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n"); 1118 if (!xudc_read_fifo(ep, req)) 1119 req = NULL; 1120 } 1121 } 1122 1123 if (req != NULL) 1124 list_add_tail(&req->queue, &ep->queue); 1125 1126 spin_unlock_irqrestore(&udc->lock, flags); 1127 return 0; 1128} 1129 1130/** 1131 * xudc_ep_dequeue - Removes the request from the queue. 1132 * @_ep: pointer to the usb device endpoint structure. 1133 * @_req: pointer to the usb request structure. 1134 * 1135 * Return: 0 for success and error value on failure 1136 */ 1137static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1138{ 1139 struct xusb_ep *ep = to_xusb_ep(_ep); 1140 struct xusb_req *req = to_xusb_req(_req); 1141 struct xusb_udc *udc = ep->udc; 1142 unsigned long flags; 1143 1144 spin_lock_irqsave(&udc->lock, flags); 1145 /* Make sure it's actually queued on this endpoint */ 1146 list_for_each_entry(req, &ep->queue, queue) { 1147 if (&req->usb_req == _req) 1148 break; 1149 } 1150 if (&req->usb_req != _req) { 1151 spin_unlock_irqrestore(&udc->lock, flags); 1152 return -EINVAL; 1153 } 1154 xudc_done(ep, req, -ECONNRESET); 1155 spin_unlock_irqrestore(&udc->lock, flags); 1156 1157 return 0; 1158} 1159 1160/** 1161 * xudc_ep0_enable - Enables the given endpoint. 1162 * @ep: pointer to the usb endpoint structure. 1163 * @desc: pointer to usb endpoint descriptor. 1164 * 1165 * Return: error always. 1166 * 1167 * endpoint 0 enable should not be called by gadget layer. 1168 */ 1169static int xudc_ep0_enable(struct usb_ep *ep, 1170 const struct usb_endpoint_descriptor *desc) 1171{ 1172 return -EINVAL; 1173} 1174 1175/** 1176 * xudc_ep0_disable - Disables the given endpoint. 1177 * @ep: pointer to the usb endpoint structure. 1178 * 1179 * Return: error always. 1180 * 1181 * endpoint 0 disable should not be called by gadget layer. 1182 */ 1183static int xudc_ep0_disable(struct usb_ep *ep) 1184{ 1185 return -EINVAL; 1186} 1187 1188static const struct usb_ep_ops xusb_ep0_ops = { 1189 .enable = xudc_ep0_enable, 1190 .disable = xudc_ep0_disable, 1191 .alloc_request = xudc_ep_alloc_request, 1192 .free_request = xudc_free_request, 1193 .queue = xudc_ep0_queue, 1194 .dequeue = xudc_ep_dequeue, 1195 .set_halt = xudc_ep_set_halt, 1196}; 1197 1198static const struct usb_ep_ops xusb_ep_ops = { 1199 .enable = xudc_ep_enable, 1200 .disable = xudc_ep_disable, 1201 .alloc_request = xudc_ep_alloc_request, 1202 .free_request = xudc_free_request, 1203 .queue = xudc_ep_queue, 1204 .dequeue = xudc_ep_dequeue, 1205 .set_halt = xudc_ep_set_halt, 1206}; 1207 1208/** 1209 * xudc_get_frame - Reads the current usb frame number. 1210 * @gadget: pointer to the usb gadget structure. 1211 * 1212 * Return: current frame number for success and error value on failure. 1213 */ 1214static int xudc_get_frame(struct usb_gadget *gadget) 1215{ 1216 struct xusb_udc *udc; 1217 int frame; 1218 1219 if (!gadget) 1220 return -ENODEV; 1221 1222 udc = to_udc(gadget); 1223 frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET); 1224 return frame; 1225} 1226 1227/** 1228 * xudc_wakeup - Send remote wakeup signal to host 1229 * @gadget: pointer to the usb gadget structure. 1230 * 1231 * Return: 0 on success and error on failure 1232 */ 1233static int xudc_wakeup(struct usb_gadget *gadget) 1234{ 1235 struct xusb_udc *udc = to_udc(gadget); 1236 u32 crtlreg; 1237 int status = -EINVAL; 1238 unsigned long flags; 1239 1240 spin_lock_irqsave(&udc->lock, flags); 1241 1242 /* Remote wake up not enabled by host */ 1243 if (!udc->remote_wkp) 1244 goto done; 1245 1246 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1247 crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK; 1248 /* set remote wake up bit */ 1249 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1250 /* 1251 * wait for a while and reset remote wake up bit since this bit 1252 * is not cleared by HW after sending remote wakeup to host. 1253 */ 1254 mdelay(2); 1255 1256 crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK; 1257 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1258 status = 0; 1259done: 1260 spin_unlock_irqrestore(&udc->lock, flags); 1261 return status; 1262} 1263 1264/** 1265 * xudc_pullup - start/stop USB traffic 1266 * @gadget: pointer to the usb gadget structure. 1267 * @is_on: flag to start or stop 1268 * 1269 * Return: 0 always 1270 * 1271 * This function starts/stops SIE engine of IP based on is_on. 1272 */ 1273static int xudc_pullup(struct usb_gadget *gadget, int is_on) 1274{ 1275 struct xusb_udc *udc = to_udc(gadget); 1276 unsigned long flags; 1277 u32 crtlreg; 1278 1279 spin_lock_irqsave(&udc->lock, flags); 1280 1281 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1282 if (is_on) 1283 crtlreg |= XUSB_CONTROL_USB_READY_MASK; 1284 else 1285 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK; 1286 1287 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1288 1289 spin_unlock_irqrestore(&udc->lock, flags); 1290 1291 return 0; 1292} 1293 1294/** 1295 * xudc_eps_init - initialize endpoints. 1296 * @udc: pointer to the usb device controller structure. 1297 */ 1298static void xudc_eps_init(struct xusb_udc *udc) 1299{ 1300 u32 ep_number; 1301 1302 INIT_LIST_HEAD(&udc->gadget.ep_list); 1303 1304 for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) { 1305 struct xusb_ep *ep = &udc->ep[ep_number]; 1306 1307 if (ep_number) { 1308 list_add_tail(&ep->ep_usb.ep_list, 1309 &udc->gadget.ep_list); 1310 usb_ep_set_maxpacket_limit(&ep->ep_usb, 1311 (unsigned short) ~0); 1312 snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number); 1313 ep->ep_usb.name = ep->name; 1314 ep->ep_usb.ops = &xusb_ep_ops; 1315 1316 ep->ep_usb.caps.type_iso = true; 1317 ep->ep_usb.caps.type_bulk = true; 1318 ep->ep_usb.caps.type_int = true; 1319 } else { 1320 ep->ep_usb.name = ep0name; 1321 usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET); 1322 ep->ep_usb.ops = &xusb_ep0_ops; 1323 1324 ep->ep_usb.caps.type_control = true; 1325 } 1326 1327 ep->ep_usb.caps.dir_in = true; 1328 ep->ep_usb.caps.dir_out = true; 1329 1330 ep->udc = udc; 1331 ep->epnumber = ep_number; 1332 ep->desc = NULL; 1333 /* 1334 * The configuration register address offset between 1335 * each endpoint is 0x10. 1336 */ 1337 ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10); 1338 ep->is_in = 0; 1339 ep->is_iso = 0; 1340 ep->maxpacket = 0; 1341 xudc_epconfig(ep, udc); 1342 1343 /* Initialize one queue per endpoint */ 1344 INIT_LIST_HEAD(&ep->queue); 1345 } 1346} 1347 1348/** 1349 * xudc_stop_activity - Stops any further activity on the device. 1350 * @udc: pointer to the usb device controller structure. 1351 */ 1352static void xudc_stop_activity(struct xusb_udc *udc) 1353{ 1354 int i; 1355 struct xusb_ep *ep; 1356 1357 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1358 ep = &udc->ep[i]; 1359 xudc_nuke(ep, -ESHUTDOWN); 1360 } 1361} 1362 1363/** 1364 * xudc_start - Starts the device. 1365 * @gadget: pointer to the usb gadget structure 1366 * @driver: pointer to gadget driver structure 1367 * 1368 * Return: zero on success and error on failure 1369 */ 1370static int xudc_start(struct usb_gadget *gadget, 1371 struct usb_gadget_driver *driver) 1372{ 1373 struct xusb_udc *udc = to_udc(gadget); 1374 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1375 const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc; 1376 unsigned long flags; 1377 int ret = 0; 1378 1379 spin_lock_irqsave(&udc->lock, flags); 1380 1381 if (udc->driver) { 1382 dev_err(udc->dev, "%s is already bound to %s\n", 1383 udc->gadget.name, udc->driver->driver.name); 1384 ret = -EBUSY; 1385 goto err; 1386 } 1387 1388 /* hook up the driver */ 1389 udc->driver = driver; 1390 udc->gadget.speed = driver->max_speed; 1391 1392 /* Enable the control endpoint. */ 1393 ret = __xudc_ep_enable(ep0, desc); 1394 1395 /* Set device address and remote wakeup to 0 */ 1396 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1397 udc->remote_wkp = 0; 1398err: 1399 spin_unlock_irqrestore(&udc->lock, flags); 1400 return ret; 1401} 1402 1403/** 1404 * xudc_stop - stops the device. 1405 * @gadget: pointer to the usb gadget structure 1406 * 1407 * Return: zero always 1408 */ 1409static int xudc_stop(struct usb_gadget *gadget) 1410{ 1411 struct xusb_udc *udc = to_udc(gadget); 1412 unsigned long flags; 1413 1414 spin_lock_irqsave(&udc->lock, flags); 1415 1416 udc->gadget.speed = USB_SPEED_UNKNOWN; 1417 udc->driver = NULL; 1418 1419 /* Set device address and remote wakeup to 0 */ 1420 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1421 udc->remote_wkp = 0; 1422 1423 xudc_stop_activity(udc); 1424 1425 spin_unlock_irqrestore(&udc->lock, flags); 1426 1427 return 0; 1428} 1429 1430static const struct usb_gadget_ops xusb_udc_ops = { 1431 .get_frame = xudc_get_frame, 1432 .wakeup = xudc_wakeup, 1433 .pullup = xudc_pullup, 1434 .udc_start = xudc_start, 1435 .udc_stop = xudc_stop, 1436}; 1437 1438/** 1439 * xudc_clear_stall_all_ep - clears stall of every endpoint. 1440 * @udc: pointer to the udc structure. 1441 */ 1442static void xudc_clear_stall_all_ep(struct xusb_udc *udc) 1443{ 1444 struct xusb_ep *ep; 1445 u32 epcfgreg; 1446 int i; 1447 1448 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1449 ep = &udc->ep[i]; 1450 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1451 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1452 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1453 if (ep->epnumber) { 1454 /* Reset the toggle bit.*/ 1455 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1456 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 1457 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1458 } 1459 } 1460} 1461 1462/** 1463 * xudc_startup_handler - The usb device controller interrupt handler. 1464 * @udc: pointer to the udc structure. 1465 * @intrstatus: The mask value containing the interrupt sources. 1466 * 1467 * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts. 1468 */ 1469static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus) 1470{ 1471 u32 intrreg; 1472 1473 if (intrstatus & XUSB_STATUS_RESET_MASK) { 1474 1475 dev_dbg(udc->dev, "Reset\n"); 1476 1477 if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK) 1478 udc->gadget.speed = USB_SPEED_HIGH; 1479 else 1480 udc->gadget.speed = USB_SPEED_FULL; 1481 1482 xudc_stop_activity(udc); 1483 xudc_clear_stall_all_ep(udc); 1484 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 1485 1486 /* Set device address and remote wakeup to 0 */ 1487 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1488 udc->remote_wkp = 0; 1489 1490 /* Enable the suspend, resume and disconnect */ 1491 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1492 intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK | 1493 XUSB_STATUS_DISCONNECT_MASK; 1494 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1495 } 1496 if (intrstatus & XUSB_STATUS_SUSPEND_MASK) { 1497 1498 dev_dbg(udc->dev, "Suspend\n"); 1499 1500 /* Enable the reset, resume and disconnect */ 1501 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1502 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1503 XUSB_STATUS_DISCONNECT_MASK; 1504 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1505 1506 udc->usb_state = USB_STATE_SUSPENDED; 1507 1508 if (udc->driver->suspend) { 1509 spin_unlock(&udc->lock); 1510 udc->driver->suspend(&udc->gadget); 1511 spin_lock(&udc->lock); 1512 } 1513 } 1514 if (intrstatus & XUSB_STATUS_RESUME_MASK) { 1515 bool condition = (udc->usb_state != USB_STATE_SUSPENDED); 1516 1517 dev_WARN_ONCE(udc->dev, condition, 1518 "Resume IRQ while not suspended\n"); 1519 1520 dev_dbg(udc->dev, "Resume\n"); 1521 1522 /* Enable the reset, suspend and disconnect */ 1523 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1524 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK | 1525 XUSB_STATUS_DISCONNECT_MASK; 1526 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1527 1528 udc->usb_state = 0; 1529 1530 if (udc->driver->resume) { 1531 spin_unlock(&udc->lock); 1532 udc->driver->resume(&udc->gadget); 1533 spin_lock(&udc->lock); 1534 } 1535 } 1536 if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) { 1537 1538 dev_dbg(udc->dev, "Disconnect\n"); 1539 1540 /* Enable the reset, resume and suspend */ 1541 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1542 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1543 XUSB_STATUS_SUSPEND_MASK; 1544 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1545 1546 if (udc->driver && udc->driver->disconnect) { 1547 spin_unlock(&udc->lock); 1548 udc->driver->disconnect(&udc->gadget); 1549 spin_lock(&udc->lock); 1550 } 1551 } 1552} 1553 1554/** 1555 * xudc_ep0_stall - Stall endpoint zero. 1556 * @udc: pointer to the udc structure. 1557 * 1558 * This function stalls endpoint zero. 1559 */ 1560static void xudc_ep0_stall(struct xusb_udc *udc) 1561{ 1562 u32 epcfgreg; 1563 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1564 1565 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1566 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1567 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1568} 1569 1570/** 1571 * xudc_setaddress - executes SET_ADDRESS command 1572 * @udc: pointer to the udc structure. 1573 * 1574 * This function executes USB SET_ADDRESS command 1575 */ 1576static void xudc_setaddress(struct xusb_udc *udc) 1577{ 1578 struct xusb_ep *ep0 = &udc->ep[0]; 1579 struct xusb_req *req = udc->req; 1580 int ret; 1581 1582 req->usb_req.length = 0; 1583 ret = __xudc_ep0_queue(ep0, req); 1584 if (ret == 0) 1585 return; 1586 1587 dev_err(udc->dev, "Can't respond to SET ADDRESS request\n"); 1588 xudc_ep0_stall(udc); 1589} 1590 1591/** 1592 * xudc_getstatus - executes GET_STATUS command 1593 * @udc: pointer to the udc structure. 1594 * 1595 * This function executes USB GET_STATUS command 1596 */ 1597static void xudc_getstatus(struct xusb_udc *udc) 1598{ 1599 struct xusb_ep *ep0 = &udc->ep[0]; 1600 struct xusb_req *req = udc->req; 1601 struct xusb_ep *target_ep; 1602 u16 status = 0; 1603 u32 epcfgreg; 1604 int epnum; 1605 u32 halt; 1606 int ret; 1607 1608 switch (udc->setup.bRequestType & USB_RECIP_MASK) { 1609 case USB_RECIP_DEVICE: 1610 /* Get device status */ 1611 status = 1 << USB_DEVICE_SELF_POWERED; 1612 if (udc->remote_wkp) 1613 status |= (1 << USB_DEVICE_REMOTE_WAKEUP); 1614 break; 1615 case USB_RECIP_INTERFACE: 1616 break; 1617 case USB_RECIP_ENDPOINT: 1618 epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1619 if (epnum >= XUSB_MAX_ENDPOINTS) 1620 goto stall; 1621 target_ep = &udc->ep[epnum]; 1622 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1623 halt = epcfgreg & XUSB_EP_CFG_STALL_MASK; 1624 if (udc->setup.wIndex & USB_DIR_IN) { 1625 if (!target_ep->is_in) 1626 goto stall; 1627 } else { 1628 if (target_ep->is_in) 1629 goto stall; 1630 } 1631 if (halt) 1632 status = 1 << USB_ENDPOINT_HALT; 1633 break; 1634 default: 1635 goto stall; 1636 } 1637 1638 req->usb_req.length = 2; 1639 *(u16 *)req->usb_req.buf = cpu_to_le16(status); 1640 ret = __xudc_ep0_queue(ep0, req); 1641 if (ret == 0) 1642 return; 1643stall: 1644 dev_err(udc->dev, "Can't respond to getstatus request\n"); 1645 xudc_ep0_stall(udc); 1646} 1647 1648/** 1649 * xudc_set_clear_feature - Executes the set feature and clear feature commands. 1650 * @udc: pointer to the usb device controller structure. 1651 * 1652 * Processes the SET_FEATURE and CLEAR_FEATURE commands. 1653 */ 1654static void xudc_set_clear_feature(struct xusb_udc *udc) 1655{ 1656 struct xusb_ep *ep0 = &udc->ep[0]; 1657 struct xusb_req *req = udc->req; 1658 struct xusb_ep *target_ep; 1659 u8 endpoint; 1660 u8 outinbit; 1661 u32 epcfgreg; 1662 int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0); 1663 int ret; 1664 1665 switch (udc->setup.bRequestType) { 1666 case USB_RECIP_DEVICE: 1667 switch (udc->setup.wValue) { 1668 case USB_DEVICE_TEST_MODE: 1669 /* 1670 * The Test Mode will be executed 1671 * after the status phase. 1672 */ 1673 break; 1674 case USB_DEVICE_REMOTE_WAKEUP: 1675 if (flag) 1676 udc->remote_wkp = 1; 1677 else 1678 udc->remote_wkp = 0; 1679 break; 1680 default: 1681 xudc_ep0_stall(udc); 1682 break; 1683 } 1684 break; 1685 case USB_RECIP_ENDPOINT: 1686 if (!udc->setup.wValue) { 1687 endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1688 if (endpoint >= XUSB_MAX_ENDPOINTS) { 1689 xudc_ep0_stall(udc); 1690 return; 1691 } 1692 target_ep = &udc->ep[endpoint]; 1693 outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK; 1694 outinbit = outinbit >> 7; 1695 1696 /* Make sure direction matches.*/ 1697 if (outinbit != target_ep->is_in) { 1698 xudc_ep0_stall(udc); 1699 return; 1700 } 1701 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1702 if (!endpoint) { 1703 /* Clear the stall.*/ 1704 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1705 udc->write_fn(udc->addr, 1706 target_ep->offset, epcfgreg); 1707 } else { 1708 if (flag) { 1709 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1710 udc->write_fn(udc->addr, 1711 target_ep->offset, 1712 epcfgreg); 1713 } else { 1714 /* Unstall the endpoint.*/ 1715 epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK | 1716 XUSB_EP_CFG_DATA_TOGGLE_MASK); 1717 udc->write_fn(udc->addr, 1718 target_ep->offset, 1719 epcfgreg); 1720 } 1721 } 1722 } 1723 break; 1724 default: 1725 xudc_ep0_stall(udc); 1726 return; 1727 } 1728 1729 req->usb_req.length = 0; 1730 ret = __xudc_ep0_queue(ep0, req); 1731 if (ret == 0) 1732 return; 1733 1734 dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n"); 1735 xudc_ep0_stall(udc); 1736} 1737 1738/** 1739 * xudc_handle_setup - Processes the setup packet. 1740 * @udc: pointer to the usb device controller structure. 1741 * 1742 * Process setup packet and delegate to gadget layer. 1743 */ 1744static void xudc_handle_setup(struct xusb_udc *udc) 1745 __must_hold(&udc->lock) 1746{ 1747 struct xusb_ep *ep0 = &udc->ep[0]; 1748 struct usb_ctrlrequest setup; 1749 u32 *ep0rambase; 1750 1751 /* Load up the chapter 9 command buffer.*/ 1752 ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); 1753 memcpy_toio((void __iomem *)&setup, ep0rambase, 8); 1754 1755 udc->setup = setup; 1756 udc->setup.wValue = cpu_to_le16(setup.wValue); 1757 udc->setup.wIndex = cpu_to_le16(setup.wIndex); 1758 udc->setup.wLength = cpu_to_le16(setup.wLength); 1759 1760 /* Clear previous requests */ 1761 xudc_nuke(ep0, -ECONNRESET); 1762 1763 if (udc->setup.bRequestType & USB_DIR_IN) { 1764 /* Execute the get command.*/ 1765 udc->setupseqrx = STATUS_PHASE; 1766 udc->setupseqtx = DATA_PHASE; 1767 } else { 1768 /* Execute the put command.*/ 1769 udc->setupseqrx = DATA_PHASE; 1770 udc->setupseqtx = STATUS_PHASE; 1771 } 1772 1773 switch (udc->setup.bRequest) { 1774 case USB_REQ_GET_STATUS: 1775 /* Data+Status phase form udc */ 1776 if ((udc->setup.bRequestType & 1777 (USB_DIR_IN | USB_TYPE_MASK)) != 1778 (USB_DIR_IN | USB_TYPE_STANDARD)) 1779 break; 1780 xudc_getstatus(udc); 1781 return; 1782 case USB_REQ_SET_ADDRESS: 1783 /* Status phase from udc */ 1784 if (udc->setup.bRequestType != (USB_DIR_OUT | 1785 USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1786 break; 1787 xudc_setaddress(udc); 1788 return; 1789 case USB_REQ_CLEAR_FEATURE: 1790 case USB_REQ_SET_FEATURE: 1791 /* Requests with no data phase, status phase from udc */ 1792 if ((udc->setup.bRequestType & USB_TYPE_MASK) 1793 != USB_TYPE_STANDARD) 1794 break; 1795 xudc_set_clear_feature(udc); 1796 return; 1797 default: 1798 break; 1799 } 1800 1801 spin_unlock(&udc->lock); 1802 if (udc->driver->setup(&udc->gadget, &setup) < 0) 1803 xudc_ep0_stall(udc); 1804 spin_lock(&udc->lock); 1805} 1806 1807/** 1808 * xudc_ep0_out - Processes the endpoint 0 OUT token. 1809 * @udc: pointer to the usb device controller structure. 1810 */ 1811static void xudc_ep0_out(struct xusb_udc *udc) 1812{ 1813 struct xusb_ep *ep0 = &udc->ep[0]; 1814 struct xusb_req *req; 1815 u8 *ep0rambase; 1816 unsigned int bytes_to_rx; 1817 void *buffer; 1818 1819 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1820 1821 switch (udc->setupseqrx) { 1822 case STATUS_PHASE: 1823 /* 1824 * This resets both state machines for the next 1825 * Setup packet. 1826 */ 1827 udc->setupseqrx = SETUP_PHASE; 1828 udc->setupseqtx = SETUP_PHASE; 1829 req->usb_req.actual = req->usb_req.length; 1830 xudc_done(ep0, req, 0); 1831 break; 1832 case DATA_PHASE: 1833 bytes_to_rx = udc->read_fn(udc->addr + 1834 XUSB_EP_BUF0COUNT_OFFSET); 1835 /* Copy the data to be received from the DPRAM. */ 1836 ep0rambase = (u8 __force *) (udc->addr + 1837 (ep0->rambase << 2)); 1838 buffer = req->usb_req.buf + req->usb_req.actual; 1839 req->usb_req.actual = req->usb_req.actual + bytes_to_rx; 1840 memcpy_toio((void __iomem *)buffer, ep0rambase, bytes_to_rx); 1841 1842 if (req->usb_req.length == req->usb_req.actual) { 1843 /* Data transfer completed get ready for Status stage */ 1844 xudc_wrstatus(udc); 1845 } else { 1846 /* Enable EP0 buffer to receive data */ 1847 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1848 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1849 } 1850 break; 1851 default: 1852 break; 1853 } 1854} 1855 1856/** 1857 * xudc_ep0_in - Processes the endpoint 0 IN token. 1858 * @udc: pointer to the usb device controller structure. 1859 */ 1860static void xudc_ep0_in(struct xusb_udc *udc) 1861{ 1862 struct xusb_ep *ep0 = &udc->ep[0]; 1863 struct xusb_req *req; 1864 unsigned int bytes_to_tx; 1865 void *buffer; 1866 u32 epcfgreg; 1867 u16 count = 0; 1868 u16 length; 1869 u8 *ep0rambase; 1870 u8 test_mode = udc->setup.wIndex >> 8; 1871 1872 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1873 bytes_to_tx = req->usb_req.length - req->usb_req.actual; 1874 1875 switch (udc->setupseqtx) { 1876 case STATUS_PHASE: 1877 switch (udc->setup.bRequest) { 1878 case USB_REQ_SET_ADDRESS: 1879 /* Set the address of the device.*/ 1880 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 1881 udc->setup.wValue); 1882 break; 1883 case USB_REQ_SET_FEATURE: 1884 if (udc->setup.bRequestType == 1885 USB_RECIP_DEVICE) { 1886 if (udc->setup.wValue == 1887 USB_DEVICE_TEST_MODE) 1888 udc->write_fn(udc->addr, 1889 XUSB_TESTMODE_OFFSET, 1890 test_mode); 1891 } 1892 break; 1893 } 1894 req->usb_req.actual = req->usb_req.length; 1895 xudc_done(ep0, req, 0); 1896 break; 1897 case DATA_PHASE: 1898 if (!bytes_to_tx) { 1899 /* 1900 * We're done with data transfer, next 1901 * will be zero length OUT with data toggle of 1902 * 1. Setup data_toggle. 1903 */ 1904 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1905 epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK; 1906 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1907 udc->setupseqtx = STATUS_PHASE; 1908 } else { 1909 length = count = min_t(u32, bytes_to_tx, 1910 EP0_MAX_PACKET); 1911 /* Copy the data to be transmitted into the DPRAM. */ 1912 ep0rambase = (u8 __force *) (udc->addr + 1913 (ep0->rambase << 2)); 1914 buffer = req->usb_req.buf + req->usb_req.actual; 1915 req->usb_req.actual = req->usb_req.actual + length; 1916 memcpy_toio((void __iomem *)ep0rambase, buffer, length); 1917 } 1918 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); 1919 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1920 break; 1921 default: 1922 break; 1923 } 1924} 1925 1926/** 1927 * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler. 1928 * @udc: pointer to the udc structure. 1929 * @intrstatus: It's the mask value for the interrupt sources on endpoint 0. 1930 * 1931 * Processes the commands received during enumeration phase. 1932 */ 1933static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus) 1934{ 1935 1936 if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) { 1937 xudc_handle_setup(udc); 1938 } else { 1939 if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK) 1940 xudc_ep0_out(udc); 1941 else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK) 1942 xudc_ep0_in(udc); 1943 } 1944} 1945 1946/** 1947 * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler. 1948 * @udc: pointer to the udc structure. 1949 * @epnum: End point number for which the interrupt is to be processed 1950 * @intrstatus: mask value for interrupt sources of endpoints other 1951 * than endpoint 0. 1952 * 1953 * Processes the buffer completion interrupts. 1954 */ 1955static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum, 1956 u32 intrstatus) 1957{ 1958 1959 struct xusb_req *req; 1960 struct xusb_ep *ep; 1961 1962 ep = &udc->ep[epnum]; 1963 /* Process the End point interrupts.*/ 1964 if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum)) 1965 ep->buffer0ready = 0; 1966 if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum)) 1967 ep->buffer1ready = 0; 1968 1969 if (list_empty(&ep->queue)) 1970 return; 1971 1972 req = list_first_entry(&ep->queue, struct xusb_req, queue); 1973 1974 if (ep->is_in) 1975 xudc_write_fifo(ep, req); 1976 else 1977 xudc_read_fifo(ep, req); 1978} 1979 1980/** 1981 * xudc_irq - The main interrupt handler. 1982 * @irq: The interrupt number. 1983 * @_udc: pointer to the usb device controller structure. 1984 * 1985 * Return: IRQ_HANDLED after the interrupt is handled. 1986 */ 1987static irqreturn_t xudc_irq(int irq, void *_udc) 1988{ 1989 struct xusb_udc *udc = _udc; 1990 u32 intrstatus; 1991 u32 ier; 1992 u8 index; 1993 u32 bufintr; 1994 unsigned long flags; 1995 1996 spin_lock_irqsave(&udc->lock, flags); 1997 1998 /* 1999 * Event interrupts are level sensitive hence first disable 2000 * IER, read ISR and figure out active interrupts. 2001 */ 2002 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2003 ier &= ~XUSB_STATUS_INTR_EVENT_MASK; 2004 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2005 2006 /* Read the Interrupt Status Register.*/ 2007 intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET); 2008 2009 /* Call the handler for the event interrupt.*/ 2010 if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) { 2011 /* 2012 * Check if there is any action to be done for : 2013 * - USB Reset received {XUSB_STATUS_RESET_MASK} 2014 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK} 2015 * - USB Resume received {XUSB_STATUS_RESUME_MASK} 2016 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK} 2017 */ 2018 xudc_startup_handler(udc, intrstatus); 2019 } 2020 2021 /* Check the buffer completion interrupts */ 2022 if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) { 2023 /* Enable Reset, Suspend, Resume and Disconnect */ 2024 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2025 ier |= XUSB_STATUS_INTR_EVENT_MASK; 2026 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2027 2028 if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK) 2029 xudc_ctrl_ep_handler(udc, intrstatus); 2030 2031 for (index = 1; index < 8; index++) { 2032 bufintr = ((intrstatus & 2033 (XUSB_STATUS_EP1_BUFF1_COMP_MASK << 2034 (index - 1))) || (intrstatus & 2035 (XUSB_STATUS_EP1_BUFF2_COMP_MASK << 2036 (index - 1)))); 2037 if (bufintr) { 2038 xudc_nonctrl_ep_handler(udc, index, 2039 intrstatus); 2040 } 2041 } 2042 } 2043 2044 spin_unlock_irqrestore(&udc->lock, flags); 2045 return IRQ_HANDLED; 2046} 2047 2048/** 2049 * xudc_probe - The device probe function for driver initialization. 2050 * @pdev: pointer to the platform device structure. 2051 * 2052 * Return: 0 for success and error value on failure 2053 */ 2054static int xudc_probe(struct platform_device *pdev) 2055{ 2056 struct device_node *np = pdev->dev.of_node; 2057 struct resource *res; 2058 struct xusb_udc *udc; 2059 int irq; 2060 int ret; 2061 u32 ier; 2062 u8 *buff; 2063 2064 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2065 if (!udc) 2066 return -ENOMEM; 2067 2068 /* Create a dummy request for GET_STATUS, SET_ADDRESS */ 2069 udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req), 2070 GFP_KERNEL); 2071 if (!udc->req) 2072 return -ENOMEM; 2073 2074 buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL); 2075 if (!buff) 2076 return -ENOMEM; 2077 2078 udc->req->usb_req.buf = buff; 2079 2080 /* Map the registers */ 2081 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2082 udc->addr = devm_ioremap_resource(&pdev->dev, res); 2083 if (IS_ERR(udc->addr)) 2084 return PTR_ERR(udc->addr); 2085 2086 irq = platform_get_irq(pdev, 0); 2087 if (irq < 0) 2088 return irq; 2089 ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0, 2090 dev_name(&pdev->dev), udc); 2091 if (ret < 0) { 2092 dev_dbg(&pdev->dev, "unable to request irq %d", irq); 2093 goto fail; 2094 } 2095 2096 udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma"); 2097 2098 /* Setup gadget structure */ 2099 udc->gadget.ops = &xusb_udc_ops; 2100 udc->gadget.max_speed = USB_SPEED_HIGH; 2101 udc->gadget.speed = USB_SPEED_UNKNOWN; 2102 udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb; 2103 udc->gadget.name = driver_name; 2104 2105 spin_lock_init(&udc->lock); 2106 2107 /* Check for IP endianness */ 2108 udc->write_fn = xudc_write32_be; 2109 udc->read_fn = xudc_read32_be; 2110 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, USB_TEST_J); 2111 if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET)) 2112 != USB_TEST_J) { 2113 udc->write_fn = xudc_write32; 2114 udc->read_fn = xudc_read32; 2115 } 2116 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 2117 2118 xudc_eps_init(udc); 2119 2120 /* Set device address to 0.*/ 2121 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 2122 2123 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2124 if (ret) 2125 goto fail; 2126 2127 udc->dev = &udc->gadget.dev; 2128 2129 /* Enable the interrupts.*/ 2130 ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK | 2131 XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK | 2132 XUSB_STATUS_SETUP_PACKET_MASK | 2133 XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK; 2134 2135 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2136 2137 platform_set_drvdata(pdev, udc); 2138 2139 dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n", 2140 driver_name, (u32)res->start, udc->addr, 2141 udc->dma_enabled ? "with DMA" : "without DMA"); 2142 2143 return 0; 2144fail: 2145 dev_err(&pdev->dev, "probe failed, %d\n", ret); 2146 return ret; 2147} 2148 2149/** 2150 * xudc_remove - Releases the resources allocated during the initialization. 2151 * @pdev: pointer to the platform device structure. 2152 * 2153 * Return: 0 always 2154 */ 2155static int xudc_remove(struct platform_device *pdev) 2156{ 2157 struct xusb_udc *udc = platform_get_drvdata(pdev); 2158 2159 usb_del_gadget_udc(&udc->gadget); 2160 2161 return 0; 2162} 2163 2164/* Match table for of_platform binding */ 2165static const struct of_device_id usb_of_match[] = { 2166 { .compatible = "xlnx,usb2-device-4.00.a", }, 2167 { /* end of list */ }, 2168}; 2169MODULE_DEVICE_TABLE(of, usb_of_match); 2170 2171static struct platform_driver xudc_driver = { 2172 .driver = { 2173 .name = driver_name, 2174 .of_match_table = usb_of_match, 2175 }, 2176 .probe = xudc_probe, 2177 .remove = xudc_remove, 2178}; 2179 2180module_platform_driver(xudc_driver); 2181 2182MODULE_DESCRIPTION("Xilinx udc driver"); 2183MODULE_AUTHOR("Xilinx, Inc"); 2184MODULE_LICENSE("GPL"); 2185