1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 */
5
6#ifndef __ASM_ARCH_REGS_UDC_H
7#define __ASM_ARCH_REGS_UDC_H
8
9#define S3C2410_USBDREG(x) (x)
10
11#define S3C2410_UDC_FUNC_ADDR_REG	S3C2410_USBDREG(0x0140)
12#define S3C2410_UDC_PWR_REG		S3C2410_USBDREG(0x0144)
13#define S3C2410_UDC_EP_INT_REG		S3C2410_USBDREG(0x0148)
14
15#define S3C2410_UDC_USB_INT_REG		S3C2410_USBDREG(0x0158)
16#define S3C2410_UDC_EP_INT_EN_REG	S3C2410_USBDREG(0x015c)
17
18#define S3C2410_UDC_USB_INT_EN_REG	S3C2410_USBDREG(0x016c)
19
20#define S3C2410_UDC_FRAME_NUM1_REG	S3C2410_USBDREG(0x0170)
21#define S3C2410_UDC_FRAME_NUM2_REG	S3C2410_USBDREG(0x0174)
22
23#define S3C2410_UDC_EP0_FIFO_REG	S3C2410_USBDREG(0x01c0)
24#define S3C2410_UDC_EP1_FIFO_REG	S3C2410_USBDREG(0x01c4)
25#define S3C2410_UDC_EP2_FIFO_REG	S3C2410_USBDREG(0x01c8)
26#define S3C2410_UDC_EP3_FIFO_REG	S3C2410_USBDREG(0x01cc)
27#define S3C2410_UDC_EP4_FIFO_REG	S3C2410_USBDREG(0x01d0)
28
29#define S3C2410_UDC_EP1_DMA_CON		S3C2410_USBDREG(0x0200)
30#define S3C2410_UDC_EP1_DMA_UNIT	S3C2410_USBDREG(0x0204)
31#define S3C2410_UDC_EP1_DMA_FIFO	S3C2410_USBDREG(0x0208)
32#define S3C2410_UDC_EP1_DMA_TTC_L	S3C2410_USBDREG(0x020c)
33#define S3C2410_UDC_EP1_DMA_TTC_M	S3C2410_USBDREG(0x0210)
34#define S3C2410_UDC_EP1_DMA_TTC_H	S3C2410_USBDREG(0x0214)
35
36#define S3C2410_UDC_EP2_DMA_CON		S3C2410_USBDREG(0x0218)
37#define S3C2410_UDC_EP2_DMA_UNIT	S3C2410_USBDREG(0x021c)
38#define S3C2410_UDC_EP2_DMA_FIFO	S3C2410_USBDREG(0x0220)
39#define S3C2410_UDC_EP2_DMA_TTC_L	S3C2410_USBDREG(0x0224)
40#define S3C2410_UDC_EP2_DMA_TTC_M	S3C2410_USBDREG(0x0228)
41#define S3C2410_UDC_EP2_DMA_TTC_H	S3C2410_USBDREG(0x022c)
42
43#define S3C2410_UDC_EP3_DMA_CON		S3C2410_USBDREG(0x0240)
44#define S3C2410_UDC_EP3_DMA_UNIT	S3C2410_USBDREG(0x0244)
45#define S3C2410_UDC_EP3_DMA_FIFO	S3C2410_USBDREG(0x0248)
46#define S3C2410_UDC_EP3_DMA_TTC_L	S3C2410_USBDREG(0x024c)
47#define S3C2410_UDC_EP3_DMA_TTC_M	S3C2410_USBDREG(0x0250)
48#define S3C2410_UDC_EP3_DMA_TTC_H	S3C2410_USBDREG(0x0254)
49
50#define S3C2410_UDC_EP4_DMA_CON		S3C2410_USBDREG(0x0258)
51#define S3C2410_UDC_EP4_DMA_UNIT	S3C2410_USBDREG(0x025c)
52#define S3C2410_UDC_EP4_DMA_FIFO	S3C2410_USBDREG(0x0260)
53#define S3C2410_UDC_EP4_DMA_TTC_L	S3C2410_USBDREG(0x0264)
54#define S3C2410_UDC_EP4_DMA_TTC_M	S3C2410_USBDREG(0x0268)
55#define S3C2410_UDC_EP4_DMA_TTC_H	S3C2410_USBDREG(0x026c)
56
57#define S3C2410_UDC_INDEX_REG		S3C2410_USBDREG(0x0178)
58
59/* indexed registers */
60
61#define S3C2410_UDC_MAXP_REG		S3C2410_USBDREG(0x0180)
62
63#define S3C2410_UDC_EP0_CSR_REG		S3C2410_USBDREG(0x0184)
64
65#define S3C2410_UDC_IN_CSR1_REG		S3C2410_USBDREG(0x0184)
66#define S3C2410_UDC_IN_CSR2_REG		S3C2410_USBDREG(0x0188)
67
68#define S3C2410_UDC_OUT_CSR1_REG	S3C2410_USBDREG(0x0190)
69#define S3C2410_UDC_OUT_CSR2_REG	S3C2410_USBDREG(0x0194)
70#define S3C2410_UDC_OUT_FIFO_CNT1_REG	S3C2410_USBDREG(0x0198)
71#define S3C2410_UDC_OUT_FIFO_CNT2_REG	S3C2410_USBDREG(0x019c)
72
73#define S3C2410_UDC_FUNCADDR_UPDATE	(1 << 7)
74
75#define S3C2410_UDC_PWR_ISOUP		(1 << 7) /* R/W */
76#define S3C2410_UDC_PWR_RESET		(1 << 3) /* R   */
77#define S3C2410_UDC_PWR_RESUME		(1 << 2) /* R/W */
78#define S3C2410_UDC_PWR_SUSPEND		(1 << 1) /* R   */
79#define S3C2410_UDC_PWR_ENSUSPEND	(1 << 0) /* R/W */
80
81#define S3C2410_UDC_PWR_DEFAULT		(0x00)
82
83#define S3C2410_UDC_INT_EP4		(1 << 4) /* R/W (clear only) */
84#define S3C2410_UDC_INT_EP3		(1 << 3) /* R/W (clear only) */
85#define S3C2410_UDC_INT_EP2		(1 << 2) /* R/W (clear only) */
86#define S3C2410_UDC_INT_EP1		(1 << 1) /* R/W (clear only) */
87#define S3C2410_UDC_INT_EP0		(1 << 0) /* R/W (clear only) */
88
89#define S3C2410_UDC_USBINT_RESET	(1 << 2) /* R/W (clear only) */
90#define S3C2410_UDC_USBINT_RESUME	(1 << 1) /* R/W (clear only) */
91#define S3C2410_UDC_USBINT_SUSPEND	(1 << 0) /* R/W (clear only) */
92
93#define S3C2410_UDC_INTE_EP4		(1 << 4) /* R/W */
94#define S3C2410_UDC_INTE_EP3		(1 << 3) /* R/W */
95#define S3C2410_UDC_INTE_EP2		(1 << 2) /* R/W */
96#define S3C2410_UDC_INTE_EP1		(1 << 1) /* R/W */
97#define S3C2410_UDC_INTE_EP0		(1 << 0) /* R/W */
98
99#define S3C2410_UDC_USBINTE_RESET	(1 << 2) /* R/W */
100#define S3C2410_UDC_USBINTE_SUSPEND	(1 << 0) /* R/W */
101
102#define S3C2410_UDC_INDEX_EP0		(0x00)
103#define S3C2410_UDC_INDEX_EP1		(0x01)
104#define S3C2410_UDC_INDEX_EP2		(0x02)
105#define S3C2410_UDC_INDEX_EP3		(0x03)
106#define S3C2410_UDC_INDEX_EP4		(0x04)
107
108#define S3C2410_UDC_ICSR1_CLRDT		(1 << 6) /* R/W */
109#define S3C2410_UDC_ICSR1_SENTSTL	(1 << 5) /* R/W (clear only) */
110#define S3C2410_UDC_ICSR1_SENDSTL	(1 << 4) /* R/W */
111#define S3C2410_UDC_ICSR1_FFLUSH	(1 << 3) /* W   (set only) */
112#define S3C2410_UDC_ICSR1_UNDRUN	(1 << 2) /* R/W (clear only) */
113#define S3C2410_UDC_ICSR1_PKTRDY	(1 << 0) /* R/W (set only) */
114
115#define S3C2410_UDC_ICSR2_AUTOSET	(1 << 7) /* R/W */
116#define S3C2410_UDC_ICSR2_ISO		(1 << 6) /* R/W */
117#define S3C2410_UDC_ICSR2_MODEIN	(1 << 5) /* R/W */
118#define S3C2410_UDC_ICSR2_DMAIEN	(1 << 4) /* R/W */
119
120#define S3C2410_UDC_OCSR1_CLRDT		(1 << 7) /* R/W */
121#define S3C2410_UDC_OCSR1_SENTSTL	(1 << 6) /* R/W (clear only) */
122#define S3C2410_UDC_OCSR1_SENDSTL	(1 << 5) /* R/W */
123#define S3C2410_UDC_OCSR1_FFLUSH	(1 << 4) /* R/W */
124#define S3C2410_UDC_OCSR1_DERROR	(1 << 3) /* R   */
125#define S3C2410_UDC_OCSR1_OVRRUN	(1 << 2) /* R/W (clear only) */
126#define S3C2410_UDC_OCSR1_PKTRDY	(1 << 0) /* R/W (clear only) */
127
128#define S3C2410_UDC_OCSR2_AUTOCLR	(1 << 7) /* R/W */
129#define S3C2410_UDC_OCSR2_ISO		(1 << 6) /* R/W */
130#define S3C2410_UDC_OCSR2_DMAIEN	(1 << 5) /* R/W */
131
132#define S3C2410_UDC_EP0_CSR_OPKRDY	(1 << 0)
133#define S3C2410_UDC_EP0_CSR_IPKRDY	(1 << 1)
134#define S3C2410_UDC_EP0_CSR_SENTSTL	(1 << 2)
135#define S3C2410_UDC_EP0_CSR_DE		(1 << 3)
136#define S3C2410_UDC_EP0_CSR_SE		(1 << 4)
137#define S3C2410_UDC_EP0_CSR_SENDSTL	(1 << 5)
138#define S3C2410_UDC_EP0_CSR_SOPKTRDY	(1 << 6)
139#define S3C2410_UDC_EP0_CSR_SSE		(1 << 7)
140
141#define S3C2410_UDC_MAXP_8		(1 << 0)
142#define S3C2410_UDC_MAXP_16		(1 << 1)
143#define S3C2410_UDC_MAXP_32		(1 << 2)
144#define S3C2410_UDC_MAXP_64		(1 << 3)
145
146#endif
147