1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2009
4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5 *
6 * Description:
7 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
8 * driver to function correctly on these systems.
9 */
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/fsl_devices.h>
14#include <linux/mod_devicetable.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17
18#include "fsl_usb2_udc.h"
19
20static struct clk *mxc_ahb_clk;
21static struct clk *mxc_per_clk;
22static struct clk *mxc_ipg_clk;
23
24/* workaround ENGcm09152 for i.MX35 */
25#define MX35_USBPHYCTRL_OFFSET		0x600
26#define USBPHYCTRL_OTGBASE_OFFSET	0x8
27#define USBPHYCTRL_EVDO			(1 << 23)
28
29int fsl_udc_clk_init(struct platform_device *pdev)
30{
31	struct fsl_usb2_platform_data *pdata;
32	unsigned long freq;
33	int ret;
34
35	pdata = dev_get_platdata(&pdev->dev);
36
37	mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
38	if (IS_ERR(mxc_ipg_clk)) {
39		dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
40		return PTR_ERR(mxc_ipg_clk);
41	}
42
43	mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
44	if (IS_ERR(mxc_ahb_clk)) {
45		dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
46		return PTR_ERR(mxc_ahb_clk);
47	}
48
49	mxc_per_clk = devm_clk_get(&pdev->dev, "per");
50	if (IS_ERR(mxc_per_clk)) {
51		dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
52		return PTR_ERR(mxc_per_clk);
53	}
54
55	clk_prepare_enable(mxc_ipg_clk);
56	clk_prepare_enable(mxc_ahb_clk);
57	clk_prepare_enable(mxc_per_clk);
58
59	/* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
60	if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
61		freq = clk_get_rate(mxc_per_clk);
62		if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
63		    (freq < 59999000 || freq > 60001000)) {
64			dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
65			ret = -EINVAL;
66			goto eclkrate;
67		}
68	}
69
70	return 0;
71
72eclkrate:
73	clk_disable_unprepare(mxc_ipg_clk);
74	clk_disable_unprepare(mxc_ahb_clk);
75	clk_disable_unprepare(mxc_per_clk);
76	mxc_per_clk = NULL;
77	return ret;
78}
79
80int fsl_udc_clk_finalize(struct platform_device *pdev)
81{
82	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
83	int ret = 0;
84
85	/* workaround ENGcm09152 for i.MX35 */
86	if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
87		unsigned int v;
88		struct resource *res = platform_get_resource
89			(pdev, IORESOURCE_MEM, 0);
90		void __iomem *phy_regs = ioremap(res->start +
91						MX35_USBPHYCTRL_OFFSET, 512);
92		if (!phy_regs) {
93			dev_err(&pdev->dev, "ioremap for phy address fails\n");
94			ret = -EINVAL;
95			goto ioremap_err;
96		}
97
98		v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
99		writel(v | USBPHYCTRL_EVDO,
100			phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
101
102		iounmap(phy_regs);
103	}
104
105
106ioremap_err:
107	/* ULPI transceivers don't need usbpll */
108	if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
109		clk_disable_unprepare(mxc_per_clk);
110		mxc_per_clk = NULL;
111	}
112
113	return ret;
114}
115
116void fsl_udc_clk_release(void)
117{
118	if (mxc_per_clk)
119		clk_disable_unprepare(mxc_per_clk);
120	clk_disable_unprepare(mxc_ahb_clk);
121	clk_disable_unprepare(mxc_ipg_clk);
122}
123