1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11#include <linux/kernel.h> 12#include <linux/slab.h> 13#include <linux/spinlock.h> 14#include <linux/platform_device.h> 15#include <linux/pm_runtime.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/list.h> 19#include <linux/dma-mapping.h> 20 21#include <linux/usb/ch9.h> 22#include <linux/usb/gadget.h> 23#include <linux/usb/composite.h> 24 25#include "core.h" 26#include "debug.h" 27#include "gadget.h" 28#include "io.h" 29 30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 35 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 36{ 37 struct dwc3_trb *trb; 38 struct dwc3 *dwc; 39 40 dwc = dep->dwc; 41 trb = &dwc->ep0_trb[dep->trb_enqueue]; 42 43 if (chain) 44 dep->trb_enqueue++; 45 46 trb->bpl = lower_32_bits(buf_dma); 47 trb->bph = upper_32_bits(buf_dma); 48 trb->size = len; 49 trb->ctrl = type; 50 51 trb->ctrl |= (DWC3_TRB_CTRL_HWO 52 | DWC3_TRB_CTRL_ISP_IMI); 53 54 if (chain) 55 trb->ctrl |= DWC3_TRB_CTRL_CHN; 56 else 57 trb->ctrl |= (DWC3_TRB_CTRL_IOC 58 | DWC3_TRB_CTRL_LST); 59 60 trace_dwc3_prepare_trb(dep, trb); 61} 62 63static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 64{ 65 struct dwc3_gadget_ep_cmd_params params; 66 struct dwc3 *dwc; 67 int ret; 68 69 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 70 return 0; 71 72 dwc = dep->dwc; 73 74 memset(¶ms, 0, sizeof(params)); 75 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 76 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 77 78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 79 if (ret < 0) 80 return ret; 81 82 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 83 84 return 0; 85} 86 87static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 88 struct dwc3_request *req) 89{ 90 struct dwc3 *dwc = dep->dwc; 91 92 req->request.actual = 0; 93 req->request.status = -EINPROGRESS; 94 req->epnum = dep->number; 95 96 list_add_tail(&req->list, &dep->pending_list); 97 98 /* 99 * Gadget driver might not be quick enough to queue a request 100 * before we get a Transfer Not Ready event on this endpoint. 101 * 102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 103 * flag is set, it's telling us that as soon as Gadget queues the 104 * required request, we should kick the transfer here because the 105 * IRQ we were waiting for is long gone. 106 */ 107 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 108 unsigned int direction; 109 110 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 111 112 if (dwc->ep0state != EP0_DATA_PHASE) { 113 dev_WARN(dwc->dev, "Unexpected pending request\n"); 114 return 0; 115 } 116 117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 118 119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 120 DWC3_EP0_DIR_IN); 121 122 return 0; 123 } 124 125 /* 126 * In case gadget driver asked us to delay the STATUS phase, 127 * handle it here. 128 */ 129 if (dwc->delayed_status) { 130 unsigned int direction; 131 132 direction = !dwc->ep0_expect_in; 133 dwc->delayed_status = false; 134 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); 135 136 if (dwc->ep0state == EP0_STATUS_PHASE) 137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 138 139 return 0; 140 } 141 142 /* 143 * Unfortunately we have uncovered a limitation wrt the Data Phase. 144 * 145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 146 * come before issueing Start Transfer command, but if we do, we will 147 * miss situations where the host starts another SETUP phase instead of 148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 149 * Layer Compliance Suite. 150 * 151 * The problem surfaces due to the fact that in case of back-to-back 152 * SETUP packets there will be no XferNotReady(DATA) generated and we 153 * will be stuck waiting for XferNotReady(DATA) forever. 154 * 155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 156 * it tells us to start Data Phase right away. It also mentions that if 157 * we receive a SETUP phase instead of the DATA phase, core will issue 158 * XferComplete for the DATA phase, before actually initiating it in 159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 160 * can only be used to print some debugging logs, as the core expects 161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 162 * just so it completes right away, without transferring anything and, 163 * only then, we can go back to the SETUP phase. 164 * 165 * Because of this scenario, SNPS decided to change the programming 166 * model of control transfers and support on-demand transfers only for 167 * the STATUS phase. To fix the issue we have now, we will always wait 168 * for gadget driver to queue the DATA phase's struct usb_request, then 169 * start it right away. 170 * 171 * If we're actually in a 2-stage transfer, we will wait for 172 * XferNotReady(STATUS). 173 */ 174 if (dwc->three_stage_setup) { 175 unsigned int direction; 176 177 direction = dwc->ep0_expect_in; 178 dwc->ep0state = EP0_DATA_PHASE; 179 180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 181 182 dep->flags &= ~DWC3_EP0_DIR_IN; 183 } 184 185 return 0; 186} 187 188int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 189 gfp_t gfp_flags) 190{ 191 struct dwc3_request *req = to_dwc3_request(request); 192 struct dwc3_ep *dep = to_dwc3_ep(ep); 193 struct dwc3 *dwc = dep->dwc; 194 195 unsigned long flags; 196 197 int ret; 198 199 spin_lock_irqsave(&dwc->lock, flags); 200 if (!dep->endpoint.desc || !dwc->pullups_connected) { 201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 202 dep->name); 203 ret = -ESHUTDOWN; 204 goto out; 205 } 206 207 /* we share one TRB for ep0/1 */ 208 if (!list_empty(&dep->pending_list)) { 209 ret = -EBUSY; 210 goto out; 211 } 212 213 ret = __dwc3_gadget_ep0_queue(dep, req); 214 215out: 216 spin_unlock_irqrestore(&dwc->lock, flags); 217 218 return ret; 219} 220 221static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 222{ 223 struct dwc3_ep *dep; 224 225 /* reinitialize physical ep1 */ 226 dep = dwc->eps[1]; 227 dep->flags = DWC3_EP_ENABLED; 228 229 /* stall is always issued on EP0 */ 230 dep = dwc->eps[0]; 231 __dwc3_gadget_ep_set_halt(dep, 1, false); 232 dep->flags = DWC3_EP_ENABLED; 233 dwc->delayed_status = false; 234 235 if (!list_empty(&dep->pending_list)) { 236 struct dwc3_request *req; 237 238 req = next_request(&dep->pending_list); 239 if (!dwc->connected) 240 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 241 else 242 dwc3_gadget_giveback(dep, req, -ECONNRESET); 243 } 244 245 dwc->ep0state = EP0_SETUP_PHASE; 246 dwc3_ep0_out_start(dwc); 247} 248 249int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 250{ 251 struct dwc3_ep *dep = to_dwc3_ep(ep); 252 struct dwc3 *dwc = dep->dwc; 253 254 dwc3_ep0_stall_and_restart(dwc); 255 256 return 0; 257} 258 259int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 260{ 261 struct dwc3_ep *dep = to_dwc3_ep(ep); 262 struct dwc3 *dwc = dep->dwc; 263 unsigned long flags; 264 int ret; 265 266 spin_lock_irqsave(&dwc->lock, flags); 267 ret = __dwc3_gadget_ep0_set_halt(ep, value); 268 spin_unlock_irqrestore(&dwc->lock, flags); 269 270 return ret; 271} 272 273void dwc3_ep0_out_start(struct dwc3 *dwc) 274{ 275 struct dwc3_ep *dep; 276 int ret; 277 278 complete(&dwc->ep0_in_setup); 279 280 dep = dwc->eps[0]; 281 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 282 DWC3_TRBCTL_CONTROL_SETUP, false); 283 ret = dwc3_ep0_start_trans(dep); 284 WARN_ON(ret < 0); 285} 286 287static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 288{ 289 struct dwc3_ep *dep; 290 u32 windex = le16_to_cpu(wIndex_le); 291 u32 epnum; 292 293 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 294 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 295 epnum |= 1; 296 297 dep = dwc->eps[epnum]; 298 if (dep == NULL) 299 return NULL; 300 301 if (dep->flags & DWC3_EP_ENABLED) 302 return dep; 303 304 return NULL; 305} 306 307static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 308{ 309} 310/* 311 * ch 9.4.5 312 */ 313static int dwc3_ep0_handle_status(struct dwc3 *dwc, 314 struct usb_ctrlrequest *ctrl) 315{ 316 struct dwc3_ep *dep; 317 u32 recip; 318 u32 value; 319 u32 reg; 320 u16 usb_status = 0; 321 __le16 *response_pkt; 322 323 /* We don't support PTM_STATUS */ 324 value = le16_to_cpu(ctrl->wValue); 325 if (value != 0) 326 return -EINVAL; 327 328 recip = ctrl->bRequestType & USB_RECIP_MASK; 329 switch (recip) { 330 case USB_RECIP_DEVICE: 331 /* 332 * LTM will be set once we know how to set this in HW. 333 */ 334 usb_status |= dwc->gadget->is_selfpowered; 335 336 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 337 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 338 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 339 if (reg & DWC3_DCTL_INITU1ENA) 340 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 341 if (reg & DWC3_DCTL_INITU2ENA) 342 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 343 } 344 345 break; 346 347 case USB_RECIP_INTERFACE: 348 /* 349 * Function Remote Wake Capable D0 350 * Function Remote Wakeup D1 351 */ 352 break; 353 354 case USB_RECIP_ENDPOINT: 355 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 356 if (!dep) 357 return -EINVAL; 358 359 if (dep->flags & DWC3_EP_STALL) 360 usb_status = 1 << USB_ENDPOINT_HALT; 361 break; 362 default: 363 return -EINVAL; 364 } 365 366 response_pkt = (__le16 *) dwc->setup_buf; 367 *response_pkt = cpu_to_le16(usb_status); 368 369 dep = dwc->eps[0]; 370 dwc->ep0_usb_req.dep = dep; 371 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 372 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 373 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 374 375 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 376} 377 378static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 379 int set) 380{ 381 u32 reg; 382 383 if (state != USB_STATE_CONFIGURED) 384 return -EINVAL; 385 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 386 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 387 return -EINVAL; 388 if (set && dwc->dis_u1_entry_quirk) 389 return -EINVAL; 390 391 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 392 if (set) 393 reg |= DWC3_DCTL_INITU1ENA; 394 else 395 reg &= ~DWC3_DCTL_INITU1ENA; 396 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 397 398 return 0; 399} 400 401static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 402 int set) 403{ 404 u32 reg; 405 406 407 if (state != USB_STATE_CONFIGURED) 408 return -EINVAL; 409 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 410 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 411 return -EINVAL; 412 if (set && dwc->dis_u2_entry_quirk) 413 return -EINVAL; 414 415 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 416 if (set) 417 reg |= DWC3_DCTL_INITU2ENA; 418 else 419 reg &= ~DWC3_DCTL_INITU2ENA; 420 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 421 422 return 0; 423} 424 425static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 426 u32 wIndex, int set) 427{ 428 if ((wIndex & 0xff) != 0) 429 return -EINVAL; 430 if (!set) 431 return -EINVAL; 432 433 switch (wIndex >> 8) { 434 case USB_TEST_J: 435 case USB_TEST_K: 436 case USB_TEST_SE0_NAK: 437 case USB_TEST_PACKET: 438 case USB_TEST_FORCE_ENABLE: 439 dwc->test_mode_nr = wIndex >> 8; 440 dwc->test_mode = true; 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 return 0; 447} 448 449static int dwc3_ep0_handle_device(struct dwc3 *dwc, 450 struct usb_ctrlrequest *ctrl, int set) 451{ 452 enum usb_device_state state; 453 u32 wValue; 454 u32 wIndex; 455 int ret = 0; 456 457 wValue = le16_to_cpu(ctrl->wValue); 458 wIndex = le16_to_cpu(ctrl->wIndex); 459 state = dwc->gadget->state; 460 461 switch (wValue) { 462 case USB_DEVICE_REMOTE_WAKEUP: 463 break; 464 /* 465 * 9.4.1 says only only for SS, in AddressState only for 466 * default control pipe 467 */ 468 case USB_DEVICE_U1_ENABLE: 469 ret = dwc3_ep0_handle_u1(dwc, state, set); 470 break; 471 case USB_DEVICE_U2_ENABLE: 472 ret = dwc3_ep0_handle_u2(dwc, state, set); 473 break; 474 case USB_DEVICE_LTM_ENABLE: 475 ret = -EINVAL; 476 break; 477 case USB_DEVICE_TEST_MODE: 478 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 479 break; 480 default: 481 ret = -EINVAL; 482 } 483 484 return ret; 485} 486 487static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 488 struct usb_ctrlrequest *ctrl, int set) 489{ 490 u32 wValue; 491 int ret = 0; 492 493 wValue = le16_to_cpu(ctrl->wValue); 494 495 switch (wValue) { 496 case USB_INTRF_FUNC_SUSPEND: 497 /* 498 * REVISIT: Ideally we would enable some low power mode here, 499 * however it's unclear what we should be doing here. 500 * 501 * For now, we're not doing anything, just making sure we return 502 * 0 so USB Command Verifier tests pass without any errors. 503 */ 504 break; 505 default: 506 ret = -EINVAL; 507 } 508 509 return ret; 510} 511 512static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 513 struct usb_ctrlrequest *ctrl, int set) 514{ 515 struct dwc3_ep *dep; 516 u32 wValue; 517 int ret; 518 519 wValue = le16_to_cpu(ctrl->wValue); 520 521 switch (wValue) { 522 case USB_ENDPOINT_HALT: 523 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 524 if (!dep) 525 return -EINVAL; 526 527 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 528 break; 529 530 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 531 if (ret) 532 return -EINVAL; 533 534 /* ClearFeature(Halt) may need delayed status */ 535 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) 536 return USB_GADGET_DELAYED_STATUS; 537 538 break; 539 default: 540 return -EINVAL; 541 } 542 543 return 0; 544} 545 546static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 547 struct usb_ctrlrequest *ctrl, int set) 548{ 549 u32 recip; 550 int ret; 551 552 recip = ctrl->bRequestType & USB_RECIP_MASK; 553 554 switch (recip) { 555 case USB_RECIP_DEVICE: 556 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 557 break; 558 case USB_RECIP_INTERFACE: 559 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 560 break; 561 case USB_RECIP_ENDPOINT: 562 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 563 break; 564 default: 565 ret = -EINVAL; 566 } 567 568 return ret; 569} 570 571static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 572{ 573 enum usb_device_state state = dwc->gadget->state; 574 u32 addr; 575 u32 reg; 576 577 addr = le16_to_cpu(ctrl->wValue); 578 if (addr > 127) { 579 dev_err(dwc->dev, "invalid device address %d\n", addr); 580 return -EINVAL; 581 } 582 583 if (state == USB_STATE_CONFIGURED) { 584 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 585 return -EINVAL; 586 } 587 588 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 589 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 590 reg |= DWC3_DCFG_DEVADDR(addr); 591 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 592 593 if (addr) 594 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); 595 else 596 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); 597 598 return 0; 599} 600 601static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 602{ 603 int ret; 604 605 spin_unlock(&dwc->lock); 606 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); 607 spin_lock(&dwc->lock); 608 return ret; 609} 610 611static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 612{ 613 enum usb_device_state state = dwc->gadget->state; 614 u32 cfg; 615 int ret; 616 u32 reg; 617 618 cfg = le16_to_cpu(ctrl->wValue); 619 620 switch (state) { 621 case USB_STATE_DEFAULT: 622 return -EINVAL; 623 624 case USB_STATE_ADDRESS: 625 ret = dwc3_ep0_delegate_req(dwc, ctrl); 626 /* if the cfg matches and the cfg is non zero */ 627 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 628 629 /* 630 * only change state if set_config has already 631 * been processed. If gadget driver returns 632 * USB_GADGET_DELAYED_STATUS, we will wait 633 * to change the state on the next usb_ep_queue() 634 */ 635 if (ret == 0) 636 usb_gadget_set_state(dwc->gadget, 637 USB_STATE_CONFIGURED); 638 639 /* 640 * Enable transition to U1/U2 state when 641 * nothing is pending from application. 642 */ 643 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 644 if (!dwc->dis_u1_entry_quirk) 645 reg |= DWC3_DCTL_ACCEPTU1ENA; 646 if (!dwc->dis_u2_entry_quirk) 647 reg |= DWC3_DCTL_ACCEPTU2ENA; 648 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 649 } 650 break; 651 652 case USB_STATE_CONFIGURED: 653 ret = dwc3_ep0_delegate_req(dwc, ctrl); 654 if (!cfg && !ret) 655 usb_gadget_set_state(dwc->gadget, 656 USB_STATE_ADDRESS); 657 break; 658 default: 659 ret = -EINVAL; 660 } 661 return ret; 662} 663 664static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 665{ 666 struct dwc3_ep *dep = to_dwc3_ep(ep); 667 struct dwc3 *dwc = dep->dwc; 668 669 u32 param = 0; 670 u32 reg; 671 672 struct timing { 673 u8 u1sel; 674 u8 u1pel; 675 __le16 u2sel; 676 __le16 u2pel; 677 } __packed timing; 678 679 int ret; 680 681 memcpy(&timing, req->buf, sizeof(timing)); 682 683 dwc->u1sel = timing.u1sel; 684 dwc->u1pel = timing.u1pel; 685 dwc->u2sel = le16_to_cpu(timing.u2sel); 686 dwc->u2pel = le16_to_cpu(timing.u2pel); 687 688 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 689 if (reg & DWC3_DCTL_INITU2ENA) 690 param = dwc->u2pel; 691 if (reg & DWC3_DCTL_INITU1ENA) 692 param = dwc->u1pel; 693 694 /* 695 * According to Synopsys Databook, if parameter is 696 * greater than 125, a value of zero should be 697 * programmed in the register. 698 */ 699 if (param > 125) 700 param = 0; 701 702 /* now that we have the time, issue DGCMD Set Sel */ 703 ret = dwc3_send_gadget_generic_command(dwc, 704 DWC3_DGCMD_SET_PERIODIC_PAR, param); 705 WARN_ON(ret < 0); 706} 707 708static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 709{ 710 struct dwc3_ep *dep; 711 enum usb_device_state state = dwc->gadget->state; 712 u16 wLength; 713 714 if (state == USB_STATE_DEFAULT) 715 return -EINVAL; 716 717 wLength = le16_to_cpu(ctrl->wLength); 718 719 if (wLength != 6) { 720 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 721 wLength); 722 return -EINVAL; 723 } 724 725 /* 726 * To handle Set SEL we need to receive 6 bytes from Host. So let's 727 * queue a usb_request for 6 bytes. 728 * 729 * Remember, though, this controller can't handle non-wMaxPacketSize 730 * aligned transfers on the OUT direction, so we queue a request for 731 * wMaxPacketSize instead. 732 */ 733 dep = dwc->eps[0]; 734 dwc->ep0_usb_req.dep = dep; 735 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 736 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 737 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 738 739 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 740} 741 742static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 743{ 744 u16 wLength; 745 u16 wValue; 746 u16 wIndex; 747 748 wValue = le16_to_cpu(ctrl->wValue); 749 wLength = le16_to_cpu(ctrl->wLength); 750 wIndex = le16_to_cpu(ctrl->wIndex); 751 752 if (wIndex || wLength) 753 return -EINVAL; 754 755 dwc->gadget->isoch_delay = wValue; 756 757 return 0; 758} 759 760static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 761{ 762 int ret; 763 764 switch (ctrl->bRequest) { 765 case USB_REQ_GET_STATUS: 766 ret = dwc3_ep0_handle_status(dwc, ctrl); 767 break; 768 case USB_REQ_CLEAR_FEATURE: 769 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 770 break; 771 case USB_REQ_SET_FEATURE: 772 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 773 break; 774 case USB_REQ_SET_ADDRESS: 775 ret = dwc3_ep0_set_address(dwc, ctrl); 776 break; 777 case USB_REQ_SET_CONFIGURATION: 778 ret = dwc3_ep0_set_config(dwc, ctrl); 779 break; 780 case USB_REQ_SET_SEL: 781 ret = dwc3_ep0_set_sel(dwc, ctrl); 782 break; 783 case USB_REQ_SET_ISOCH_DELAY: 784 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 785 break; 786 default: 787 ret = dwc3_ep0_delegate_req(dwc, ctrl); 788 break; 789 } 790 791 return ret; 792} 793 794static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 795 const struct dwc3_event_depevt *event) 796{ 797 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 798 int ret = -EINVAL; 799 u32 len; 800 801 if (!dwc->gadget_driver) 802 goto out; 803 804 trace_dwc3_ctrl_req(ctrl); 805 806 len = le16_to_cpu(ctrl->wLength); 807 if (!len) { 808 dwc->three_stage_setup = false; 809 dwc->ep0_expect_in = false; 810 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 811 } else { 812 dwc->three_stage_setup = true; 813 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 814 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 815 } 816 817 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 818 ret = dwc3_ep0_std_request(dwc, ctrl); 819 else 820 ret = dwc3_ep0_delegate_req(dwc, ctrl); 821 822 if (ret == USB_GADGET_DELAYED_STATUS) 823 dwc->delayed_status = true; 824 825out: 826 if (ret < 0) 827 dwc3_ep0_stall_and_restart(dwc); 828} 829 830static void dwc3_ep0_complete_data(struct dwc3 *dwc, 831 const struct dwc3_event_depevt *event) 832{ 833 struct dwc3_request *r; 834 struct usb_request *ur; 835 struct dwc3_trb *trb; 836 struct dwc3_ep *ep0; 837 u32 transferred = 0; 838 u32 status; 839 u32 length; 840 u8 epnum; 841 842 epnum = event->endpoint_number; 843 ep0 = dwc->eps[0]; 844 845 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 846 trb = dwc->ep0_trb; 847 trace_dwc3_complete_trb(ep0, trb); 848 849 r = next_request(&ep0->pending_list); 850 if (!r) 851 return; 852 853 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 854 if (status == DWC3_TRBSTS_SETUP_PENDING) { 855 dwc->setup_packet_pending = true; 856 if (r) 857 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 858 859 return; 860 } 861 862 ur = &r->request; 863 864 length = trb->size & DWC3_TRB_SIZE_MASK; 865 transferred = ur->length - length; 866 ur->actual += transferred; 867 868 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 869 ur->length && ur->zero) || dwc->ep0_bounced) { 870 trb++; 871 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 872 trace_dwc3_complete_trb(ep0, trb); 873 874 if (r->direction) 875 dwc->eps[1]->trb_enqueue = 0; 876 else 877 dwc->eps[0]->trb_enqueue = 0; 878 879 dwc->ep0_bounced = false; 880 } 881 882 if ((epnum & 1) && ur->actual < ur->length) 883 dwc3_ep0_stall_and_restart(dwc); 884 else 885 dwc3_gadget_giveback(ep0, r, 0); 886} 887 888static void dwc3_ep0_complete_status(struct dwc3 *dwc, 889 const struct dwc3_event_depevt *event) 890{ 891 struct dwc3_request *r; 892 struct dwc3_ep *dep; 893 struct dwc3_trb *trb; 894 u32 status; 895 896 dep = dwc->eps[0]; 897 trb = dwc->ep0_trb; 898 899 trace_dwc3_complete_trb(dep, trb); 900 901 if (!list_empty(&dep->pending_list)) { 902 r = next_request(&dep->pending_list); 903 904 dwc3_gadget_giveback(dep, r, 0); 905 } 906 907 if (dwc->test_mode) { 908 int ret; 909 910 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 911 if (ret < 0) { 912 dev_err(dwc->dev, "invalid test #%d\n", 913 dwc->test_mode_nr); 914 dwc3_ep0_stall_and_restart(dwc); 915 return; 916 } 917 } 918 919 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 920 if (status == DWC3_TRBSTS_SETUP_PENDING) 921 dwc->setup_packet_pending = true; 922 923 dwc->ep0state = EP0_SETUP_PHASE; 924 dwc3_ep0_out_start(dwc); 925} 926 927static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 928 const struct dwc3_event_depevt *event) 929{ 930 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 931 932 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 933 dep->resource_index = 0; 934 dwc->setup_packet_pending = false; 935 936 switch (dwc->ep0state) { 937 case EP0_SETUP_PHASE: 938 dwc3_ep0_inspect_setup(dwc, event); 939 break; 940 941 case EP0_DATA_PHASE: 942 dwc3_ep0_complete_data(dwc, event); 943 break; 944 945 case EP0_STATUS_PHASE: 946 dwc3_ep0_complete_status(dwc, event); 947 break; 948 default: 949 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 950 } 951} 952 953static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 954 struct dwc3_ep *dep, struct dwc3_request *req) 955{ 956 unsigned int trb_length = 0; 957 int ret; 958 959 req->direction = !!dep->number; 960 961 if (req->request.length == 0) { 962 if (!req->direction) 963 trb_length = dep->endpoint.maxpacket; 964 965 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, 966 DWC3_TRBCTL_CONTROL_DATA, false); 967 ret = dwc3_ep0_start_trans(dep); 968 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 969 && (dep->number == 0)) { 970 u32 maxpacket; 971 u32 rem; 972 973 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 974 &req->request, dep->number); 975 if (ret) 976 return; 977 978 maxpacket = dep->endpoint.maxpacket; 979 rem = req->request.length % maxpacket; 980 dwc->ep0_bounced = true; 981 982 /* prepare normal TRB */ 983 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 984 req->request.length, 985 DWC3_TRBCTL_CONTROL_DATA, 986 true); 987 988 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 989 990 /* Now prepare one extra TRB to align transfer size */ 991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 992 maxpacket - rem, 993 DWC3_TRBCTL_CONTROL_DATA, 994 false); 995 ret = dwc3_ep0_start_trans(dep); 996 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 997 req->request.length && req->request.zero) { 998 999 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1000 &req->request, dep->number); 1001 if (ret) 1002 return; 1003 1004 /* prepare normal TRB */ 1005 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1006 req->request.length, 1007 DWC3_TRBCTL_CONTROL_DATA, 1008 true); 1009 1010 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1011 1012 if (!req->direction) 1013 trb_length = dep->endpoint.maxpacket; 1014 1015 /* Now prepare one extra TRB to align transfer size */ 1016 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1017 trb_length, DWC3_TRBCTL_CONTROL_DATA, 1018 false); 1019 ret = dwc3_ep0_start_trans(dep); 1020 } else { 1021 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1022 &req->request, dep->number); 1023 if (ret) 1024 return; 1025 1026 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1027 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1028 false); 1029 1030 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1031 1032 ret = dwc3_ep0_start_trans(dep); 1033 } 1034 1035 WARN_ON(ret < 0); 1036} 1037 1038static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1039{ 1040 struct dwc3 *dwc = dep->dwc; 1041 u32 type; 1042 1043 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1044 : DWC3_TRBCTL_CONTROL_STATUS2; 1045 1046 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1047 return dwc3_ep0_start_trans(dep); 1048} 1049 1050static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1051{ 1052 WARN_ON(dwc3_ep0_start_control_status(dep)); 1053} 1054 1055static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1056 const struct dwc3_event_depevt *event) 1057{ 1058 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1059 1060 __dwc3_ep0_do_control_status(dwc, dep); 1061} 1062 1063void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) 1064{ 1065 unsigned int direction = !dwc->ep0_expect_in; 1066 1067 dwc->delayed_status = false; 1068 1069 if (dwc->ep0state != EP0_STATUS_PHASE) 1070 return; 1071 1072 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 1073} 1074 1075static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1076{ 1077 struct dwc3_gadget_ep_cmd_params params; 1078 u32 cmd; 1079 int ret; 1080 1081 if (!dep->resource_index) 1082 return; 1083 1084 cmd = DWC3_DEPCMD_ENDTRANSFER; 1085 cmd |= DWC3_DEPCMD_CMDIOC; 1086 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1087 memset(¶ms, 0, sizeof(params)); 1088 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1089 WARN_ON_ONCE(ret); 1090 dep->resource_index = 0; 1091} 1092 1093static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1094 const struct dwc3_event_depevt *event) 1095{ 1096 switch (event->status) { 1097 case DEPEVT_STATUS_CONTROL_DATA: 1098 /* 1099 * We already have a DATA transfer in the controller's cache, 1100 * if we receive a XferNotReady(DATA) we will ignore it, unless 1101 * it's for the wrong direction. 1102 * 1103 * In that case, we must issue END_TRANSFER command to the Data 1104 * Phase we already have started and issue SetStall on the 1105 * control endpoint. 1106 */ 1107 if (dwc->ep0_expect_in != event->endpoint_number) { 1108 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1109 1110 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1111 dwc3_ep0_end_control_data(dwc, dep); 1112 dwc3_ep0_stall_and_restart(dwc); 1113 return; 1114 } 1115 1116 break; 1117 1118 case DEPEVT_STATUS_CONTROL_STATUS: 1119 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1120 return; 1121 1122 dwc->ep0state = EP0_STATUS_PHASE; 1123 1124 if (dwc->delayed_status) { 1125 struct dwc3_ep *dep = dwc->eps[0]; 1126 1127 WARN_ON_ONCE(event->endpoint_number != 1); 1128 /* 1129 * We should handle the delay STATUS phase here if the 1130 * request for handling delay STATUS has been queued 1131 * into the list. 1132 */ 1133 if (!list_empty(&dep->pending_list)) { 1134 dwc->delayed_status = false; 1135 usb_gadget_set_state(dwc->gadget, 1136 USB_STATE_CONFIGURED); 1137 dwc3_ep0_do_control_status(dwc, event); 1138 } 1139 1140 return; 1141 } 1142 1143 dwc3_ep0_do_control_status(dwc, event); 1144 } 1145} 1146 1147void dwc3_ep0_interrupt(struct dwc3 *dwc, 1148 const struct dwc3_event_depevt *event) 1149{ 1150 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1151 u8 cmd; 1152 1153 switch (event->endpoint_event) { 1154 case DWC3_DEPEVT_XFERCOMPLETE: 1155 dwc3_ep0_xfer_complete(dwc, event); 1156 break; 1157 1158 case DWC3_DEPEVT_XFERNOTREADY: 1159 dwc3_ep0_xfernotready(dwc, event); 1160 break; 1161 1162 case DWC3_DEPEVT_XFERINPROGRESS: 1163 case DWC3_DEPEVT_RXTXFIFOEVT: 1164 case DWC3_DEPEVT_STREAMEVT: 1165 break; 1166 case DWC3_DEPEVT_EPCMDCMPLT: 1167 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 1168 1169 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 1170 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; 1171 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 1172 } 1173 break; 1174 } 1175} 1176