1// SPDX-License-Identifier: GPL-2.0 2/** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/slab.h> 14#include <linux/pci.h> 15#include <linux/workqueue.h> 16#include <linux/pm_runtime.h> 17#include <linux/platform_device.h> 18#include <linux/gpio/consumer.h> 19#include <linux/gpio/machine.h> 20#include <linux/acpi.h> 21#include <linux/delay.h> 22 23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34#define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 44 45#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 46#define PCI_INTEL_BXT_FUNC_PMU_PWR 4 47#define PCI_INTEL_BXT_STATE_D0 0 48#define PCI_INTEL_BXT_STATE_D3 3 49 50#define GP_RWBAR 1 51#define GP_RWREG1 0xa0 52#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 53 54/** 55 * struct dwc3_pci - Driver private structure 56 * @dwc3: child dwc3 platform_device 57 * @pci: our link to PCI bus 58 * @guid: _DSM GUID 59 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 60 * @wakeup_work: work for asynchronous resume 61 */ 62struct dwc3_pci { 63 struct platform_device *dwc3; 64 struct pci_dev *pci; 65 66 guid_t guid; 67 68 unsigned int has_dsm_for_pm:1; 69 struct work_struct wakeup_work; 70}; 71 72static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 73static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 74 75static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 76 { "reset-gpios", &reset_gpios, 1 }, 77 { "cs-gpios", &cs_gpios, 1 }, 78 { }, 79}; 80 81static struct gpiod_lookup_table platform_bytcr_gpios = { 82 .dev_id = "0000:00:16.0", 83 .table = { 84 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 85 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 86 {} 87 }, 88}; 89 90static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 91{ 92 void __iomem *reg; 93 u32 value; 94 95 reg = pcim_iomap(pci, GP_RWBAR, 0); 96 if (!reg) 97 return -ENOMEM; 98 99 value = readl(reg + GP_RWREG1); 100 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 101 goto unmap; /* ULPI refclk already enabled */ 102 103 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 104 writel(value, reg + GP_RWREG1); 105 /* This comes from the Intel Android x86 tree w/o any explanation */ 106 msleep(100); 107unmap: 108 pcim_iounmap(pci, reg); 109 return 0; 110} 111 112static const struct property_entry dwc3_pci_intel_properties[] = { 113 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 114 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 115 {} 116}; 117 118static const struct property_entry dwc3_pci_mrfld_properties[] = { 119 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 120 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 121 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 122 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 123 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 124 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 125 {} 126}; 127 128static const struct property_entry dwc3_pci_amd_properties[] = { 129 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 130 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 131 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 133 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 134 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 135 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 136 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 137 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 138 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 139 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 140 /* FIXME these quirks should be removed when AMD NL tapes out */ 141 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 142 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 143 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 144 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 145 {} 146}; 147 148static int dwc3_pci_quirks(struct dwc3_pci *dwc) 149{ 150 struct pci_dev *pdev = dwc->pci; 151 152 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 153 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 154 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 155 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) { 156 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 157 dwc->has_dsm_for_pm = true; 158 } 159 160 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 161 struct gpio_desc *gpio; 162 int ret; 163 164 /* On BYT the FW does not always enable the refclock */ 165 ret = dwc3_byt_enable_ulpi_refclock(pdev); 166 if (ret) 167 return ret; 168 169 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 170 acpi_dwc3_byt_gpios); 171 if (ret) 172 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 173 174 /* 175 * A lot of BYT devices lack ACPI resource entries for 176 * the GPIOs. If the ACPI entry for the GPIO controller 177 * is present add a fallback mapping to the reference 178 * design GPIOs which all boards seem to use. 179 */ 180 if (acpi_dev_present("INT33FC", NULL, -1)) 181 gpiod_add_lookup_table(&platform_bytcr_gpios); 182 183 /* 184 * These GPIOs will turn on the USB2 PHY. Note that we have to 185 * put the gpio descriptors again here because the phy driver 186 * might want to grab them, too. 187 */ 188 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 189 if (IS_ERR(gpio)) 190 return PTR_ERR(gpio); 191 192 gpiod_set_value_cansleep(gpio, 1); 193 gpiod_put(gpio); 194 195 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 196 if (IS_ERR(gpio)) 197 return PTR_ERR(gpio); 198 199 if (gpio) { 200 gpiod_set_value_cansleep(gpio, 1); 201 gpiod_put(gpio); 202 usleep_range(10000, 11000); 203 } 204 } 205 } 206 207 return 0; 208} 209 210#ifdef CONFIG_PM 211static void dwc3_pci_resume_work(struct work_struct *work) 212{ 213 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 214 struct platform_device *dwc3 = dwc->dwc3; 215 int ret; 216 217 ret = pm_runtime_get_sync(&dwc3->dev); 218 if (ret < 0) { 219 pm_runtime_put_sync_autosuspend(&dwc3->dev); 220 return; 221 } 222 223 pm_runtime_mark_last_busy(&dwc3->dev); 224 pm_runtime_put_sync_autosuspend(&dwc3->dev); 225} 226#endif 227 228static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 229{ 230 struct property_entry *p = (struct property_entry *)id->driver_data; 231 struct dwc3_pci *dwc; 232 struct resource res[2]; 233 int ret; 234 struct device *dev = &pci->dev; 235 236 ret = pcim_enable_device(pci); 237 if (ret) { 238 dev_err(dev, "failed to enable pci device\n"); 239 return -ENODEV; 240 } 241 242 pci_set_master(pci); 243 244 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 245 if (!dwc) 246 return -ENOMEM; 247 248 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 249 if (!dwc->dwc3) 250 return -ENOMEM; 251 252 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 253 254 res[0].start = pci_resource_start(pci, 0); 255 res[0].end = pci_resource_end(pci, 0); 256 res[0].name = "dwc_usb3"; 257 res[0].flags = IORESOURCE_MEM; 258 259 res[1].start = pci->irq; 260 res[1].name = "dwc_usb3"; 261 res[1].flags = IORESOURCE_IRQ; 262 263 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 264 if (ret) { 265 dev_err(dev, "couldn't add resources to dwc3 device\n"); 266 goto err; 267 } 268 269 dwc->pci = pci; 270 dwc->dwc3->dev.parent = dev; 271 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 272 273 ret = platform_device_add_properties(dwc->dwc3, p); 274 if (ret < 0) 275 goto err; 276 277 ret = dwc3_pci_quirks(dwc); 278 if (ret) 279 goto err; 280 281 ret = platform_device_add(dwc->dwc3); 282 if (ret) { 283 dev_err(dev, "failed to register dwc3 device\n"); 284 goto err; 285 } 286 287 device_init_wakeup(dev, true); 288 pci_set_drvdata(pci, dwc); 289 pm_runtime_put(dev); 290#ifdef CONFIG_PM 291 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 292#endif 293 294 return 0; 295err: 296 platform_device_put(dwc->dwc3); 297 return ret; 298} 299 300static void dwc3_pci_remove(struct pci_dev *pci) 301{ 302 struct dwc3_pci *dwc = pci_get_drvdata(pci); 303 struct pci_dev *pdev = dwc->pci; 304 305 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 306 gpiod_remove_lookup_table(&platform_bytcr_gpios); 307#ifdef CONFIG_PM 308 cancel_work_sync(&dwc->wakeup_work); 309#endif 310 device_init_wakeup(&pci->dev, false); 311 pm_runtime_get(&pci->dev); 312 platform_device_unregister(dwc->dwc3); 313} 314 315static const struct pci_device_id dwc3_pci_id_table[] = { 316 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 317 (kernel_ulong_t) &dwc3_pci_intel_properties }, 318 319 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 320 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 321 322 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 323 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 324 325 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 326 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 327 328 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 329 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 330 331 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 332 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 333 334 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 335 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 336 337 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 338 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 339 340 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 341 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 342 343 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 344 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 345 346 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 347 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 348 349 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 350 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 351 352 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 353 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 354 355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 356 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 357 358 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 359 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 360 361 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 362 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 363 364 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 365 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 366 367 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 368 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 369 370 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 371 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 372 373 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 374 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 375 376 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 377 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 378 379 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 380 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 381 { } /* Terminating Entry */ 382}; 383MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 384 385#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 386static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 387{ 388 union acpi_object *obj; 389 union acpi_object tmp; 390 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 391 392 if (!dwc->has_dsm_for_pm) 393 return 0; 394 395 tmp.type = ACPI_TYPE_INTEGER; 396 tmp.integer.value = param; 397 398 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 399 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 400 if (!obj) { 401 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 402 return -EIO; 403 } 404 405 ACPI_FREE(obj); 406 407 return 0; 408} 409#endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 410 411#ifdef CONFIG_PM 412static int dwc3_pci_runtime_suspend(struct device *dev) 413{ 414 struct dwc3_pci *dwc = dev_get_drvdata(dev); 415 416 if (device_can_wakeup(dev)) 417 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 418 419 return -EBUSY; 420} 421 422static int dwc3_pci_runtime_resume(struct device *dev) 423{ 424 struct dwc3_pci *dwc = dev_get_drvdata(dev); 425 int ret; 426 427 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 428 if (ret) 429 return ret; 430 431 queue_work(pm_wq, &dwc->wakeup_work); 432 433 return 0; 434} 435#endif /* CONFIG_PM */ 436 437#ifdef CONFIG_PM_SLEEP 438static int dwc3_pci_suspend(struct device *dev) 439{ 440 struct dwc3_pci *dwc = dev_get_drvdata(dev); 441 442 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 443} 444 445static int dwc3_pci_resume(struct device *dev) 446{ 447 struct dwc3_pci *dwc = dev_get_drvdata(dev); 448 449 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 450} 451#endif /* CONFIG_PM_SLEEP */ 452 453static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 454 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 455 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 456 NULL) 457}; 458 459static struct pci_driver dwc3_pci_driver = { 460 .name = "dwc3-pci", 461 .id_table = dwc3_pci_id_table, 462 .probe = dwc3_pci_probe, 463 .remove = dwc3_pci_remove, 464 .driver = { 465 .pm = &dwc3_pci_dev_pm_ops, 466 } 467}; 468 469MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 470MODULE_LICENSE("GPL v2"); 471MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 472 473module_pci_driver(dwc3_pci_driver); 474