1// SPDX-License-Identifier: GPL-2.0 2/* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11#include <linux/clk.h> 12#include <linux/version.h> 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/slab.h> 16#include <linux/spinlock.h> 17#include <linux/platform_device.h> 18#include <linux/pm_runtime.h> 19#include <linux/interrupt.h> 20#include <linux/ioport.h> 21#include <linux/io.h> 22#include <linux/list.h> 23#include <linux/delay.h> 24#include <linux/dma-mapping.h> 25#include <linux/of.h> 26#include <linux/acpi.h> 27#include <linux/pinctrl/consumer.h> 28#include <linux/reset.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32#include <linux/usb/of.h> 33#include <linux/usb/otg.h> 34 35#include "core.h" 36#include "gadget.h" 37#include "io.h" 38 39#include "debug.h" 40 41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 42 43/** 44 * dwc3_get_dr_mode - Validates and sets dr_mode 45 * @dwc: pointer to our context structure 46 */ 47static int dwc3_get_dr_mode(struct dwc3 *dwc) 48{ 49 enum usb_dr_mode mode; 50 struct device *dev = dwc->dev; 51 unsigned int hw_mode; 52 53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 54 dwc->dr_mode = USB_DR_MODE_OTG; 55 56 mode = dwc->dr_mode; 57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 58 59 switch (hw_mode) { 60 case DWC3_GHWPARAMS0_MODE_GADGET: 61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 62 dev_err(dev, 63 "Controller does not support host mode.\n"); 64 return -EINVAL; 65 } 66 mode = USB_DR_MODE_PERIPHERAL; 67 break; 68 case DWC3_GHWPARAMS0_MODE_HOST: 69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 70 dev_err(dev, 71 "Controller does not support device mode.\n"); 72 return -EINVAL; 73 } 74 mode = USB_DR_MODE_HOST; 75 break; 76 default: 77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 82 /* 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 84 * mode. If the controller supports DRD but the dr_mode is not 85 * specified or set to OTG, then set the mode to peripheral. 86 */ 87 if (mode == USB_DR_MODE_OTG && 88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 89 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 91 mode = USB_DR_MODE_PERIPHERAL; 92 } 93 94 if (mode != dwc->dr_mode) { 95 dev_warn(dev, 96 "Configuration mismatch. dr_mode forced to %s\n", 97 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 98 99 dwc->dr_mode = mode; 100 } 101 102 return 0; 103} 104 105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 106{ 107 u32 reg; 108 109 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 111 reg |= DWC3_GCTL_PRTCAPDIR(mode); 112 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113 114 dwc->current_dr_role = mode; 115} 116 117static void __dwc3_set_mode(struct work_struct *work) 118{ 119 struct dwc3 *dwc = work_to_dwc(work); 120 unsigned long flags; 121 int ret; 122 u32 reg; 123 u32 desired_dr_role; 124 125 mutex_lock(&dwc->mutex); 126 spin_lock_irqsave(&dwc->lock, flags); 127 desired_dr_role = dwc->desired_dr_role; 128 spin_unlock_irqrestore(&dwc->lock, flags); 129 130 pm_runtime_get_sync(dwc->dev); 131 132 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 133 dwc3_otg_update(dwc, 0); 134 135 if (!desired_dr_role) 136 goto out; 137 138 if (desired_dr_role == dwc->current_dr_role) 139 goto out; 140 141 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 142 goto out; 143 144 switch (dwc->current_dr_role) { 145 case DWC3_GCTL_PRTCAP_HOST: 146 dwc3_host_exit(dwc); 147 break; 148 case DWC3_GCTL_PRTCAP_DEVICE: 149 dwc3_gadget_exit(dwc); 150 dwc3_event_buffers_cleanup(dwc); 151 break; 152 case DWC3_GCTL_PRTCAP_OTG: 153 dwc3_otg_exit(dwc); 154 spin_lock_irqsave(&dwc->lock, flags); 155 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 156 spin_unlock_irqrestore(&dwc->lock, flags); 157 dwc3_otg_update(dwc, 1); 158 break; 159 default: 160 break; 161 } 162 163 /* 164 * When current_dr_role is not set, there's no role switching. 165 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 166 */ 167 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 168 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 169 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 170 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 171 reg |= DWC3_GCTL_CORESOFTRESET; 172 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 173 174 /* 175 * Wait for internal clocks to synchronized. DWC_usb31 and 176 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 177 * keep it consistent across different IPs, let's wait up to 178 * 100ms before clearing GCTL.CORESOFTRESET. 179 */ 180 msleep(100); 181 182 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 183 reg &= ~DWC3_GCTL_CORESOFTRESET; 184 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 185 } 186 187 spin_lock_irqsave(&dwc->lock, flags); 188 189 dwc3_set_prtcap(dwc, desired_dr_role); 190 191 spin_unlock_irqrestore(&dwc->lock, flags); 192 193 switch (desired_dr_role) { 194 case DWC3_GCTL_PRTCAP_HOST: 195 ret = dwc3_host_init(dwc); 196 if (ret) { 197 dev_err(dwc->dev, "failed to initialize host\n"); 198 } else { 199 if (dwc->usb2_phy) 200 otg_set_vbus(dwc->usb2_phy->otg, true); 201 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 202 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 203 if (dwc->dis_split_quirk) { 204 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 205 reg |= DWC3_GUCTL3_SPLITDISABLE; 206 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 207 } 208 } 209 break; 210 case DWC3_GCTL_PRTCAP_DEVICE: 211 dwc3_core_soft_reset(dwc); 212 213 dwc3_event_buffers_setup(dwc); 214 215 if (dwc->usb2_phy) 216 otg_set_vbus(dwc->usb2_phy->otg, false); 217 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 218 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 219 220 ret = dwc3_gadget_init(dwc); 221 if (ret) 222 dev_err(dwc->dev, "failed to initialize peripheral\n"); 223 break; 224 case DWC3_GCTL_PRTCAP_OTG: 225 dwc3_otg_init(dwc); 226 dwc3_otg_update(dwc, 0); 227 break; 228 default: 229 break; 230 } 231 232out: 233 pm_runtime_mark_last_busy(dwc->dev); 234 pm_runtime_put_autosuspend(dwc->dev); 235 mutex_unlock(&dwc->mutex); 236} 237 238void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 239{ 240 unsigned long flags; 241 242 if (dwc->dr_mode != USB_DR_MODE_OTG) 243 return; 244 245 spin_lock_irqsave(&dwc->lock, flags); 246 dwc->desired_dr_role = mode; 247 spin_unlock_irqrestore(&dwc->lock, flags); 248 249 queue_work(system_freezable_wq, &dwc->drd_work); 250} 251 252u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 253{ 254 struct dwc3 *dwc = dep->dwc; 255 u32 reg; 256 257 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 258 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 259 DWC3_GDBGFIFOSPACE_TYPE(type)); 260 261 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 262 263 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 264} 265 266/** 267 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 268 * @dwc: pointer to our context structure 269 */ 270int dwc3_core_soft_reset(struct dwc3 *dwc) 271{ 272 u32 reg; 273 int retries = 1000; 274 275 /* 276 * We're resetting only the device side because, if we're in host mode, 277 * XHCI driver will reset the host block. If dwc3 was configured for 278 * host-only mode, then we can return early. 279 */ 280 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 281 return 0; 282 283 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 284 reg |= DWC3_DCTL_CSFTRST; 285 reg &= ~DWC3_DCTL_RUN_STOP; 286 dwc3_gadget_dctl_write_safe(dwc, reg); 287 288 /* 289 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 290 * is cleared only after all the clocks are synchronized. This can 291 * take a little more than 50ms. Set the polling rate at 20ms 292 * for 10 times instead. 293 */ 294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 295 retries = 10; 296 297 do { 298 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 299 if (!(reg & DWC3_DCTL_CSFTRST)) 300 goto done; 301 302 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 303 msleep(20); 304 else 305 udelay(1); 306 } while (--retries); 307 308 return -ETIMEDOUT; 309 310done: 311 /* 312 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 313 * is cleared, we must wait at least 50ms before accessing the PHY 314 * domain (synchronization delay). 315 */ 316 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 317 msleep(50); 318 319 return 0; 320} 321 322/* 323 * dwc3_frame_length_adjustment - Adjusts frame length if required 324 * @dwc3: Pointer to our controller context structure 325 */ 326static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 327{ 328 u32 reg; 329 u32 dft; 330 331 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 332 return; 333 334 if (dwc->fladj == 0) 335 return; 336 337 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 338 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 339 if (dft != dwc->fladj) { 340 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 341 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 342 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 343 } 344} 345 346/** 347 * dwc3_free_one_event_buffer - Frees one event buffer 348 * @dwc: Pointer to our controller context structure 349 * @evt: Pointer to event buffer to be freed 350 */ 351static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 352 struct dwc3_event_buffer *evt) 353{ 354 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 355} 356 357/** 358 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 359 * @dwc: Pointer to our controller context structure 360 * @length: size of the event buffer 361 * 362 * Returns a pointer to the allocated event buffer structure on success 363 * otherwise ERR_PTR(errno). 364 */ 365static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 366 unsigned length) 367{ 368 struct dwc3_event_buffer *evt; 369 370 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 371 if (!evt) 372 return ERR_PTR(-ENOMEM); 373 374 evt->dwc = dwc; 375 evt->length = length; 376 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 377 if (!evt->cache) 378 return ERR_PTR(-ENOMEM); 379 380 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 381 &evt->dma, GFP_KERNEL); 382 if (!evt->buf) 383 return ERR_PTR(-ENOMEM); 384 385 return evt; 386} 387 388/** 389 * dwc3_free_event_buffers - frees all allocated event buffers 390 * @dwc: Pointer to our controller context structure 391 */ 392static void dwc3_free_event_buffers(struct dwc3 *dwc) 393{ 394 struct dwc3_event_buffer *evt; 395 396 evt = dwc->ev_buf; 397 if (evt) 398 dwc3_free_one_event_buffer(dwc, evt); 399} 400 401/** 402 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 403 * @dwc: pointer to our controller context structure 404 * @length: size of event buffer 405 * 406 * Returns 0 on success otherwise negative errno. In the error case, dwc 407 * may contain some buffers allocated but not all which were requested. 408 */ 409static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 410{ 411 struct dwc3_event_buffer *evt; 412 413 evt = dwc3_alloc_one_event_buffer(dwc, length); 414 if (IS_ERR(evt)) { 415 dev_err(dwc->dev, "can't allocate event buffer\n"); 416 return PTR_ERR(evt); 417 } 418 dwc->ev_buf = evt; 419 420 return 0; 421} 422 423/** 424 * dwc3_event_buffers_setup - setup our allocated event buffers 425 * @dwc: pointer to our controller context structure 426 * 427 * Returns 0 on success otherwise negative errno. 428 */ 429int dwc3_event_buffers_setup(struct dwc3 *dwc) 430{ 431 struct dwc3_event_buffer *evt; 432 433 evt = dwc->ev_buf; 434 evt->lpos = 0; 435 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 436 lower_32_bits(evt->dma)); 437 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 438 upper_32_bits(evt->dma)); 439 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 440 DWC3_GEVNTSIZ_SIZE(evt->length)); 441 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 442 443 return 0; 444} 445 446void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 447{ 448 struct dwc3_event_buffer *evt; 449 450 evt = dwc->ev_buf; 451 452 evt->lpos = 0; 453 454 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 455 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 456 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 457 | DWC3_GEVNTSIZ_SIZE(0)); 458 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 459} 460 461static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 462{ 463 if (!dwc->has_hibernation) 464 return 0; 465 466 if (!dwc->nr_scratch) 467 return 0; 468 469 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 470 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 471 if (!dwc->scratchbuf) 472 return -ENOMEM; 473 474 return 0; 475} 476 477static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 478{ 479 dma_addr_t scratch_addr; 480 u32 param; 481 int ret; 482 483 if (!dwc->has_hibernation) 484 return 0; 485 486 if (!dwc->nr_scratch) 487 return 0; 488 489 /* should never fall here */ 490 if (!WARN_ON(dwc->scratchbuf)) 491 return 0; 492 493 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 494 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 495 DMA_BIDIRECTIONAL); 496 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 497 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 498 ret = -EFAULT; 499 goto err0; 500 } 501 502 dwc->scratch_addr = scratch_addr; 503 504 param = lower_32_bits(scratch_addr); 505 506 ret = dwc3_send_gadget_generic_command(dwc, 507 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 508 if (ret < 0) 509 goto err1; 510 511 param = upper_32_bits(scratch_addr); 512 513 ret = dwc3_send_gadget_generic_command(dwc, 514 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 515 if (ret < 0) 516 goto err1; 517 518 return 0; 519 520err1: 521 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 522 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 523 524err0: 525 return ret; 526} 527 528static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 529{ 530 if (!dwc->has_hibernation) 531 return; 532 533 if (!dwc->nr_scratch) 534 return; 535 536 /* should never fall here */ 537 if (!WARN_ON(dwc->scratchbuf)) 538 return; 539 540 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 541 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 542 kfree(dwc->scratchbuf); 543} 544 545static void dwc3_core_num_eps(struct dwc3 *dwc) 546{ 547 struct dwc3_hwparams *parms = &dwc->hwparams; 548 549 dwc->num_eps = DWC3_NUM_EPS(parms); 550} 551 552static void dwc3_cache_hwparams(struct dwc3 *dwc) 553{ 554 struct dwc3_hwparams *parms = &dwc->hwparams; 555 556 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 557 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 558 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 559 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 560 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 561 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 562 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 563 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 564 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 565} 566 567static int dwc3_core_ulpi_init(struct dwc3 *dwc) 568{ 569 int intf; 570 int ret = 0; 571 572 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 573 574 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 575 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 576 dwc->hsphy_interface && 577 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 578 ret = dwc3_ulpi_init(dwc); 579 580 return ret; 581} 582 583/** 584 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 585 * @dwc: Pointer to our controller context structure 586 * 587 * Returns 0 on success. The USB PHY interfaces are configured but not 588 * initialized. The PHY interfaces and the PHYs get initialized together with 589 * the core in dwc3_core_init. 590 */ 591static int dwc3_phy_setup(struct dwc3 *dwc) 592{ 593 unsigned int hw_mode; 594 u32 reg; 595 596 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 597 598 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 599 600 /* 601 * Make sure UX_EXIT_PX is cleared as that causes issues with some 602 * PHYs. Also, this bit is not supposed to be used in normal operation. 603 */ 604 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 605 606 /* 607 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 608 * to '0' during coreConsultant configuration. So default value 609 * will be '0' when the core is reset. Application needs to set it 610 * to '1' after the core initialization is completed. 611 */ 612 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 613 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 614 615 /* 616 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 617 * power-on reset, and it can be set after core initialization, which is 618 * after device soft-reset during initialization. 619 */ 620 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 621 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 622 623 if (dwc->u2ss_inp3_quirk) 624 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 625 626 if (dwc->dis_rxdet_inp3_quirk) 627 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 628 629 if (dwc->req_p1p2p3_quirk) 630 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 631 632 if (dwc->del_p1p2p3_quirk) 633 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 634 635 if (dwc->del_phy_power_chg_quirk) 636 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 637 638 if (dwc->lfps_filter_quirk) 639 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 640 641 if (dwc->rx_detect_poll_quirk) 642 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 643 644 if (dwc->tx_de_emphasis_quirk) 645 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 646 647 if (dwc->dis_u3_susphy_quirk) 648 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 649 650 if (dwc->dis_del_phy_power_chg_quirk) 651 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 652 653 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 654 655 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 656 657 /* Select the HS PHY interface */ 658 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 659 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 660 if (dwc->hsphy_interface && 661 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 662 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 663 break; 664 } else if (dwc->hsphy_interface && 665 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 666 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 667 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 668 } else { 669 /* Relying on default value. */ 670 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 671 break; 672 } 673 fallthrough; 674 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 675 default: 676 break; 677 } 678 679 switch (dwc->hsphy_mode) { 680 case USBPHY_INTERFACE_MODE_UTMI: 681 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 682 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 683 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 684 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 685 break; 686 case USBPHY_INTERFACE_MODE_UTMIW: 687 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 688 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 689 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 690 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 691 break; 692 default: 693 break; 694 } 695 696 /* 697 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 698 * '0' during coreConsultant configuration. So default value will 699 * be '0' when the core is reset. Application needs to set it to 700 * '1' after the core initialization is completed. 701 */ 702 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 703 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 704 705 /* 706 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 707 * power-on reset, and it can be set after core initialization, which is 708 * after device soft-reset during initialization. 709 */ 710 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 711 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 712 713 if (dwc->dis_u2_susphy_quirk) 714 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 715 716 if (dwc->dis_enblslpm_quirk) 717 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 718 else 719 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 720 721 if (dwc->dis_u2_freeclk_exists_quirk) 722 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 723 724 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 725 726 return 0; 727} 728 729static void dwc3_core_exit(struct dwc3 *dwc) 730{ 731 dwc3_event_buffers_cleanup(dwc); 732 733 usb_phy_set_suspend(dwc->usb2_phy, 1); 734 usb_phy_set_suspend(dwc->usb3_phy, 1); 735 phy_power_off(dwc->usb2_generic_phy); 736 phy_power_off(dwc->usb3_generic_phy); 737 738 usb_phy_shutdown(dwc->usb2_phy); 739 usb_phy_shutdown(dwc->usb3_phy); 740 phy_exit(dwc->usb2_generic_phy); 741 phy_exit(dwc->usb3_generic_phy); 742 743 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 744 reset_control_assert(dwc->reset); 745} 746 747static bool dwc3_core_is_valid(struct dwc3 *dwc) 748{ 749 u32 reg; 750 751 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 752 dwc->ip = DWC3_GSNPS_ID(reg); 753 754 /* This should read as U3 followed by revision number */ 755 if (DWC3_IP_IS(DWC3)) { 756 dwc->revision = reg; 757 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 758 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 759 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 760 } else { 761 return false; 762 } 763 764 return true; 765} 766 767static void dwc3_core_setup_global_control(struct dwc3 *dwc) 768{ 769 u32 hwparams4 = dwc->hwparams.hwparams4; 770 u32 reg; 771 772 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 773 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 774 775 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 776 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 777 /** 778 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 779 * issue which would cause xHCI compliance tests to fail. 780 * 781 * Because of that we cannot enable clock gating on such 782 * configurations. 783 * 784 * Refers to: 785 * 786 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 787 * SOF/ITP Mode Used 788 */ 789 if ((dwc->dr_mode == USB_DR_MODE_HOST || 790 dwc->dr_mode == USB_DR_MODE_OTG) && 791 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 792 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 793 else 794 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 795 break; 796 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 797 /* enable hibernation here */ 798 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 799 800 /* 801 * REVISIT Enabling this bit so that host-mode hibernation 802 * will work. Device-mode hibernation is not yet implemented. 803 */ 804 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 805 break; 806 default: 807 /* nothing */ 808 break; 809 } 810 811 /* check if current dwc3 is on simulation board */ 812 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 813 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 814 dwc->is_fpga = true; 815 } 816 817 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 818 "disable_scramble cannot be used on non-FPGA builds\n"); 819 820 if (dwc->disable_scramble_quirk && dwc->is_fpga) 821 reg |= DWC3_GCTL_DISSCRAMBLE; 822 else 823 reg &= ~DWC3_GCTL_DISSCRAMBLE; 824 825 if (dwc->u2exit_lfps_quirk) 826 reg |= DWC3_GCTL_U2EXIT_LFPS; 827 828 /* 829 * WORKAROUND: DWC3 revisions <1.90a have a bug 830 * where the device can fail to connect at SuperSpeed 831 * and falls back to high-speed mode which causes 832 * the device to enter a Connect/Disconnect loop 833 */ 834 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 835 reg |= DWC3_GCTL_U2RSTECN; 836 837 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 838} 839 840static int dwc3_core_get_phy(struct dwc3 *dwc); 841static int dwc3_core_ulpi_init(struct dwc3 *dwc); 842 843/* set global incr burst type configuration registers */ 844static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 845{ 846 struct device *dev = dwc->dev; 847 /* incrx_mode : for INCR burst type. */ 848 bool incrx_mode; 849 /* incrx_size : for size of INCRX burst. */ 850 u32 incrx_size; 851 u32 *vals; 852 u32 cfg; 853 int ntype; 854 int ret; 855 int i; 856 857 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 858 859 /* 860 * Handle property "snps,incr-burst-type-adjustment". 861 * Get the number of value from this property: 862 * result <= 0, means this property is not supported. 863 * result = 1, means INCRx burst mode supported. 864 * result > 1, means undefined length burst mode supported. 865 */ 866 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 867 if (ntype <= 0) 868 return; 869 870 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 871 if (!vals) { 872 dev_err(dev, "Error to get memory\n"); 873 return; 874 } 875 876 /* Get INCR burst type, and parse it */ 877 ret = device_property_read_u32_array(dev, 878 "snps,incr-burst-type-adjustment", vals, ntype); 879 if (ret) { 880 kfree(vals); 881 dev_err(dev, "Error to get property\n"); 882 return; 883 } 884 885 incrx_size = *vals; 886 887 if (ntype > 1) { 888 /* INCRX (undefined length) burst mode */ 889 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 890 for (i = 1; i < ntype; i++) { 891 if (vals[i] > incrx_size) 892 incrx_size = vals[i]; 893 } 894 } else { 895 /* INCRX burst mode */ 896 incrx_mode = INCRX_BURST_MODE; 897 } 898 899 kfree(vals); 900 901 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 902 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 903 if (incrx_mode) 904 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 905 switch (incrx_size) { 906 case 256: 907 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 908 break; 909 case 128: 910 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 911 break; 912 case 64: 913 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 914 break; 915 case 32: 916 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 917 break; 918 case 16: 919 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 920 break; 921 case 8: 922 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 923 break; 924 case 4: 925 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 926 break; 927 case 1: 928 break; 929 default: 930 dev_err(dev, "Invalid property\n"); 931 break; 932 } 933 934 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 935} 936 937/** 938 * dwc3_core_init - Low-level initialization of DWC3 Core 939 * @dwc: Pointer to our controller context structure 940 * 941 * Returns 0 on success otherwise negative errno. 942 */ 943static int dwc3_core_init(struct dwc3 *dwc) 944{ 945 unsigned int hw_mode; 946 u32 reg; 947 int ret; 948 949 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 950 951 /* 952 * Write Linux Version Code to our GUID register so it's easy to figure 953 * out which kernel version a bug was found. 954 */ 955 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 956 957 ret = dwc3_phy_setup(dwc); 958 if (ret) 959 goto err0; 960 961 if (!dwc->ulpi_ready) { 962 ret = dwc3_core_ulpi_init(dwc); 963 if (ret) { 964 if (ret == -ETIMEDOUT) { 965 dwc3_core_soft_reset(dwc); 966 ret = -EPROBE_DEFER; 967 } 968 goto err0; 969 } 970 dwc->ulpi_ready = true; 971 } 972 973 if (!dwc->phys_ready) { 974 ret = dwc3_core_get_phy(dwc); 975 if (ret) 976 goto err0a; 977 dwc->phys_ready = true; 978 } 979 980 usb_phy_init(dwc->usb2_phy); 981 usb_phy_init(dwc->usb3_phy); 982 ret = phy_init(dwc->usb2_generic_phy); 983 if (ret < 0) 984 goto err0a; 985 986 ret = phy_init(dwc->usb3_generic_phy); 987 if (ret < 0) { 988 phy_exit(dwc->usb2_generic_phy); 989 goto err0a; 990 } 991 992 ret = dwc3_core_soft_reset(dwc); 993 if (ret) 994 goto err1; 995 996 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 997 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 998 if (!dwc->dis_u3_susphy_quirk) { 999 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1000 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1001 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1002 } 1003 1004 if (!dwc->dis_u2_susphy_quirk) { 1005 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1006 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1007 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1008 } 1009 } 1010 1011 dwc3_core_setup_global_control(dwc); 1012 dwc3_core_num_eps(dwc); 1013 1014 ret = dwc3_setup_scratch_buffers(dwc); 1015 if (ret) 1016 goto err1; 1017 1018 /* Adjust Frame Length */ 1019 dwc3_frame_length_adjustment(dwc); 1020 1021 dwc3_set_incr_burst_type(dwc); 1022 1023 usb_phy_set_suspend(dwc->usb2_phy, 0); 1024 usb_phy_set_suspend(dwc->usb3_phy, 0); 1025 ret = phy_power_on(dwc->usb2_generic_phy); 1026 if (ret < 0) 1027 goto err2; 1028 1029 ret = phy_power_on(dwc->usb3_generic_phy); 1030 if (ret < 0) 1031 goto err3; 1032 1033 ret = dwc3_event_buffers_setup(dwc); 1034 if (ret) { 1035 dev_err(dwc->dev, "failed to setup event buffers\n"); 1036 goto err4; 1037 } 1038 1039 /* 1040 * ENDXFER polling is available on version 3.10a and later of 1041 * the DWC_usb3 controller. It is NOT available in the 1042 * DWC_usb31 controller. 1043 */ 1044 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1045 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1046 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1047 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1048 } 1049 1050 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1051 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1052 1053 /* 1054 * Enable hardware control of sending remote wakeup 1055 * in HS when the device is in the L1 state. 1056 */ 1057 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1058 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1059 1060 if (dwc->dis_tx_ipgap_linecheck_quirk) 1061 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1062 1063 if (dwc->parkmode_disable_ss_quirk) 1064 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1065 1066 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1067 } 1068 1069 /* 1070 * Must config both number of packets and max burst settings to enable 1071 * RX and/or TX threshold. 1072 */ 1073 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1074 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1075 u8 rx_maxburst = dwc->rx_max_burst_prd; 1076 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1077 u8 tx_maxburst = dwc->tx_max_burst_prd; 1078 1079 if (rx_thr_num && rx_maxburst) { 1080 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1081 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1082 1083 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1084 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1085 1086 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1087 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1088 1089 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1090 } 1091 1092 if (tx_thr_num && tx_maxburst) { 1093 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1094 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1095 1096 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1097 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1098 1099 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1100 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1101 1102 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1103 } 1104 } 1105 1106 return 0; 1107 1108err4: 1109 phy_power_off(dwc->usb3_generic_phy); 1110 1111err3: 1112 phy_power_off(dwc->usb2_generic_phy); 1113 1114err2: 1115 usb_phy_set_suspend(dwc->usb2_phy, 1); 1116 usb_phy_set_suspend(dwc->usb3_phy, 1); 1117 1118err1: 1119 usb_phy_shutdown(dwc->usb2_phy); 1120 usb_phy_shutdown(dwc->usb3_phy); 1121 phy_exit(dwc->usb2_generic_phy); 1122 phy_exit(dwc->usb3_generic_phy); 1123 1124err0a: 1125 dwc3_ulpi_exit(dwc); 1126 1127err0: 1128 return ret; 1129} 1130 1131static int dwc3_core_get_phy(struct dwc3 *dwc) 1132{ 1133 struct device *dev = dwc->dev; 1134 struct device_node *node = dev->of_node; 1135 int ret; 1136 1137 if (node) { 1138 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1139 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1140 } else { 1141 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1142 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1143 } 1144 1145 if (IS_ERR(dwc->usb2_phy)) { 1146 ret = PTR_ERR(dwc->usb2_phy); 1147 if (ret == -ENXIO || ret == -ENODEV) { 1148 dwc->usb2_phy = NULL; 1149 } else if (ret == -EPROBE_DEFER) { 1150 return ret; 1151 } else { 1152 dev_err(dev, "no usb2 phy configured\n"); 1153 return ret; 1154 } 1155 } 1156 1157 if (IS_ERR(dwc->usb3_phy)) { 1158 ret = PTR_ERR(dwc->usb3_phy); 1159 if (ret == -ENXIO || ret == -ENODEV) { 1160 dwc->usb3_phy = NULL; 1161 } else if (ret == -EPROBE_DEFER) { 1162 return ret; 1163 } else { 1164 dev_err(dev, "no usb3 phy configured\n"); 1165 return ret; 1166 } 1167 } 1168 1169 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1170 if (IS_ERR(dwc->usb2_generic_phy)) { 1171 ret = PTR_ERR(dwc->usb2_generic_phy); 1172 if (ret == -ENOSYS || ret == -ENODEV) { 1173 dwc->usb2_generic_phy = NULL; 1174 } else if (ret == -EPROBE_DEFER) { 1175 return ret; 1176 } else { 1177 dev_err(dev, "no usb2 phy configured\n"); 1178 return ret; 1179 } 1180 } 1181 1182 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1183 if (IS_ERR(dwc->usb3_generic_phy)) { 1184 ret = PTR_ERR(dwc->usb3_generic_phy); 1185 if (ret == -ENOSYS || ret == -ENODEV) { 1186 dwc->usb3_generic_phy = NULL; 1187 } else if (ret == -EPROBE_DEFER) { 1188 return ret; 1189 } else { 1190 dev_err(dev, "no usb3 phy configured\n"); 1191 return ret; 1192 } 1193 } 1194 1195 return 0; 1196} 1197 1198static int dwc3_core_init_mode(struct dwc3 *dwc) 1199{ 1200 struct device *dev = dwc->dev; 1201 int ret; 1202 1203 switch (dwc->dr_mode) { 1204 case USB_DR_MODE_PERIPHERAL: 1205 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1206 1207 if (dwc->usb2_phy) 1208 otg_set_vbus(dwc->usb2_phy->otg, false); 1209 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1210 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1211 1212 ret = dwc3_gadget_init(dwc); 1213 if (ret) { 1214 if (ret != -EPROBE_DEFER) 1215 dev_err(dev, "failed to initialize gadget\n"); 1216 return ret; 1217 } 1218 break; 1219 case USB_DR_MODE_HOST: 1220 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1221 1222 if (dwc->usb2_phy) 1223 otg_set_vbus(dwc->usb2_phy->otg, true); 1224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1226 1227 ret = dwc3_host_init(dwc); 1228 if (ret) { 1229 if (ret != -EPROBE_DEFER) 1230 dev_err(dev, "failed to initialize host\n"); 1231 return ret; 1232 } 1233 break; 1234 case USB_DR_MODE_OTG: 1235 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1236 ret = dwc3_drd_init(dwc); 1237 if (ret) { 1238 if (ret != -EPROBE_DEFER) 1239 dev_err(dev, "failed to initialize dual-role\n"); 1240 return ret; 1241 } 1242 break; 1243 default: 1244 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1245 return -EINVAL; 1246 } 1247 1248 return 0; 1249} 1250 1251static void dwc3_core_exit_mode(struct dwc3 *dwc) 1252{ 1253 switch (dwc->dr_mode) { 1254 case USB_DR_MODE_PERIPHERAL: 1255 dwc3_gadget_exit(dwc); 1256 break; 1257 case USB_DR_MODE_HOST: 1258 dwc3_host_exit(dwc); 1259 break; 1260 case USB_DR_MODE_OTG: 1261 dwc3_drd_exit(dwc); 1262 break; 1263 default: 1264 /* do nothing */ 1265 break; 1266 } 1267 1268 /* de-assert DRVVBUS for HOST and OTG mode */ 1269 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1270} 1271 1272static void dwc3_get_properties(struct dwc3 *dwc) 1273{ 1274 struct device *dev = dwc->dev; 1275 u8 lpm_nyet_threshold; 1276 u8 tx_de_emphasis; 1277 u8 hird_threshold; 1278 u8 rx_thr_num_pkt_prd = 0; 1279 u8 rx_max_burst_prd = 0; 1280 u8 tx_thr_num_pkt_prd = 0; 1281 u8 tx_max_burst_prd = 0; 1282 1283 /* default to highest possible threshold */ 1284 lpm_nyet_threshold = 0xf; 1285 1286 /* default to -3.5dB de-emphasis */ 1287 tx_de_emphasis = 1; 1288 1289 /* 1290 * default to assert utmi_sleep_n and use maximum allowed HIRD 1291 * threshold value of 0b1100 1292 */ 1293 hird_threshold = 12; 1294 1295 dwc->maximum_speed = usb_get_maximum_speed(dev); 1296 dwc->dr_mode = usb_get_dr_mode(dev); 1297 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1298 1299 dwc->sysdev_is_parent = device_property_read_bool(dev, 1300 "linux,sysdev_is_parent"); 1301 if (dwc->sysdev_is_parent) 1302 dwc->sysdev = dwc->dev->parent; 1303 else 1304 dwc->sysdev = dwc->dev; 1305 1306 dwc->has_lpm_erratum = device_property_read_bool(dev, 1307 "snps,has-lpm-erratum"); 1308 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1309 &lpm_nyet_threshold); 1310 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1311 "snps,is-utmi-l1-suspend"); 1312 device_property_read_u8(dev, "snps,hird-threshold", 1313 &hird_threshold); 1314 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1315 "snps,dis-start-transfer-quirk"); 1316 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1317 "snps,usb3_lpm_capable"); 1318 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1319 "snps,usb2-lpm-disable"); 1320 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1321 "snps,usb2-gadget-lpm-disable"); 1322 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1323 &rx_thr_num_pkt_prd); 1324 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1325 &rx_max_burst_prd); 1326 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1327 &tx_thr_num_pkt_prd); 1328 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1329 &tx_max_burst_prd); 1330 1331 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1332 "snps,disable_scramble_quirk"); 1333 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1334 "snps,u2exit_lfps_quirk"); 1335 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1336 "snps,u2ss_inp3_quirk"); 1337 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1338 "snps,req_p1p2p3_quirk"); 1339 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1340 "snps,del_p1p2p3_quirk"); 1341 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1342 "snps,del_phy_power_chg_quirk"); 1343 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1344 "snps,lfps_filter_quirk"); 1345 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1346 "snps,rx_detect_poll_quirk"); 1347 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1348 "snps,dis_u3_susphy_quirk"); 1349 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1350 "snps,dis_u2_susphy_quirk"); 1351 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1352 "snps,dis_enblslpm_quirk"); 1353 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1354 "snps,dis-u1-entry-quirk"); 1355 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1356 "snps,dis-u2-entry-quirk"); 1357 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1358 "snps,dis_rxdet_inp3_quirk"); 1359 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1360 "snps,dis-u2-freeclk-exists-quirk"); 1361 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1362 "snps,dis-del-phy-power-chg-quirk"); 1363 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1364 "snps,dis-tx-ipgap-linecheck-quirk"); 1365 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1366 "snps,parkmode-disable-ss-quirk"); 1367 1368 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1369 "snps,tx_de_emphasis_quirk"); 1370 device_property_read_u8(dev, "snps,tx_de_emphasis", 1371 &tx_de_emphasis); 1372 device_property_read_string(dev, "snps,hsphy_interface", 1373 &dwc->hsphy_interface); 1374 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1375 &dwc->fladj); 1376 1377 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1378 "snps,dis_metastability_quirk"); 1379 1380 dwc->dis_split_quirk = device_property_read_bool(dev, 1381 "snps,dis-split-quirk"); 1382 1383 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1384 dwc->tx_de_emphasis = tx_de_emphasis; 1385 1386 dwc->hird_threshold = hird_threshold; 1387 1388 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1389 dwc->rx_max_burst_prd = rx_max_burst_prd; 1390 1391 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1392 dwc->tx_max_burst_prd = tx_max_burst_prd; 1393 1394 dwc->imod_interval = 0; 1395} 1396 1397/* check whether the core supports IMOD */ 1398bool dwc3_has_imod(struct dwc3 *dwc) 1399{ 1400 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1401 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1402 DWC3_IP_IS(DWC32); 1403} 1404 1405static void dwc3_check_params(struct dwc3 *dwc) 1406{ 1407 struct device *dev = dwc->dev; 1408 unsigned int hwparam_gen = 1409 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1410 1411 /* Check for proper value of imod_interval */ 1412 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1413 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1414 dwc->imod_interval = 0; 1415 } 1416 1417 /* 1418 * Workaround for STAR 9000961433 which affects only version 1419 * 3.00a of the DWC_usb3 core. This prevents the controller 1420 * interrupt from being masked while handling events. IMOD 1421 * allows us to work around this issue. Enable it for the 1422 * affected version. 1423 */ 1424 if (!dwc->imod_interval && 1425 DWC3_VER_IS(DWC3, 300A)) 1426 dwc->imod_interval = 1; 1427 1428 /* Check the maximum_speed parameter */ 1429 switch (dwc->maximum_speed) { 1430 case USB_SPEED_LOW: 1431 case USB_SPEED_FULL: 1432 case USB_SPEED_HIGH: 1433 break; 1434 case USB_SPEED_SUPER: 1435 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1436 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1437 break; 1438 case USB_SPEED_SUPER_PLUS: 1439 if ((DWC3_IP_IS(DWC32) && 1440 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1441 (!DWC3_IP_IS(DWC32) && 1442 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1443 dev_warn(dev, "UDC doesn't support SSP\n"); 1444 break; 1445 default: 1446 dev_err(dev, "invalid maximum_speed parameter %d\n", 1447 dwc->maximum_speed); 1448 fallthrough; 1449 case USB_SPEED_UNKNOWN: 1450 switch (hwparam_gen) { 1451 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1452 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1453 break; 1454 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1455 if (DWC3_IP_IS(DWC32)) 1456 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1457 else 1458 dwc->maximum_speed = USB_SPEED_SUPER; 1459 break; 1460 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1461 dwc->maximum_speed = USB_SPEED_HIGH; 1462 break; 1463 default: 1464 dwc->maximum_speed = USB_SPEED_SUPER; 1465 break; 1466 } 1467 break; 1468 } 1469} 1470 1471static int dwc3_probe(struct platform_device *pdev) 1472{ 1473 struct device *dev = &pdev->dev; 1474 struct resource *res, dwc_res; 1475 struct dwc3 *dwc; 1476 1477 int ret; 1478 1479 void __iomem *regs; 1480 1481 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1482 if (!dwc) 1483 return -ENOMEM; 1484 1485 dwc->dev = dev; 1486 1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1488 if (!res) { 1489 dev_err(dev, "missing memory resource\n"); 1490 return -ENODEV; 1491 } 1492 1493 dwc->xhci_resources[0].start = res->start; 1494 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1495 DWC3_XHCI_REGS_END; 1496 dwc->xhci_resources[0].flags = res->flags; 1497 dwc->xhci_resources[0].name = res->name; 1498 1499 /* 1500 * Request memory region but exclude xHCI regs, 1501 * since it will be requested by the xhci-plat driver. 1502 */ 1503 dwc_res = *res; 1504 dwc_res.start += DWC3_GLOBALS_REGS_START; 1505 1506 regs = devm_ioremap_resource(dev, &dwc_res); 1507 if (IS_ERR(regs)) 1508 return PTR_ERR(regs); 1509 1510 dwc->regs = regs; 1511 dwc->regs_size = resource_size(&dwc_res); 1512 1513 dwc3_get_properties(dwc); 1514 1515 dwc->reset = devm_reset_control_array_get(dev, true, true); 1516 if (IS_ERR(dwc->reset)) 1517 return PTR_ERR(dwc->reset); 1518 1519 if (dev->of_node) { 1520 ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1521 if (ret == -EPROBE_DEFER) 1522 return ret; 1523 /* 1524 * Clocks are optional, but new DT platforms should support all 1525 * clocks as required by the DT-binding. 1526 */ 1527 if (ret < 0) 1528 dwc->num_clks = 0; 1529 else 1530 dwc->num_clks = ret; 1531 1532 } 1533 1534 ret = reset_control_deassert(dwc->reset); 1535 if (ret) 1536 return ret; 1537 1538 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1539 if (ret) 1540 goto assert_reset; 1541 1542 if (!dwc3_core_is_valid(dwc)) { 1543 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1544 ret = -ENODEV; 1545 goto disable_clks; 1546 } 1547 1548 platform_set_drvdata(pdev, dwc); 1549 dwc3_cache_hwparams(dwc); 1550 1551 spin_lock_init(&dwc->lock); 1552 mutex_init(&dwc->mutex); 1553 1554 pm_runtime_get_noresume(dev); 1555 pm_runtime_set_active(dev); 1556 pm_runtime_use_autosuspend(dev); 1557 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1558 pm_runtime_enable(dev); 1559 1560 pm_runtime_forbid(dev); 1561 1562 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1563 if (ret) { 1564 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1565 ret = -ENOMEM; 1566 goto err2; 1567 } 1568 1569 ret = dwc3_get_dr_mode(dwc); 1570 if (ret) 1571 goto err3; 1572 1573 ret = dwc3_alloc_scratch_buffers(dwc); 1574 if (ret) 1575 goto err3; 1576 1577 ret = dwc3_core_init(dwc); 1578 if (ret) { 1579 if (ret != -EPROBE_DEFER) 1580 dev_err(dev, "failed to initialize core: %d\n", ret); 1581 goto err4; 1582 } 1583 1584 dwc3_check_params(dwc); 1585 dwc3_debugfs_init(dwc); 1586 1587 ret = dwc3_core_init_mode(dwc); 1588 if (ret) 1589 goto err5; 1590 1591 pm_runtime_put(dev); 1592 1593 dma_set_max_seg_size(dev, UINT_MAX); 1594 1595 return 0; 1596 1597err5: 1598 dwc3_debugfs_exit(dwc); 1599 dwc3_event_buffers_cleanup(dwc); 1600 1601 usb_phy_set_suspend(dwc->usb2_phy, 1); 1602 usb_phy_set_suspend(dwc->usb3_phy, 1); 1603 phy_power_off(dwc->usb2_generic_phy); 1604 phy_power_off(dwc->usb3_generic_phy); 1605 1606 usb_phy_shutdown(dwc->usb2_phy); 1607 usb_phy_shutdown(dwc->usb3_phy); 1608 phy_exit(dwc->usb2_generic_phy); 1609 phy_exit(dwc->usb3_generic_phy); 1610 1611 dwc3_ulpi_exit(dwc); 1612 1613err4: 1614 dwc3_free_scratch_buffers(dwc); 1615 1616err3: 1617 dwc3_free_event_buffers(dwc); 1618 1619err2: 1620 pm_runtime_allow(dev); 1621 pm_runtime_disable(dev); 1622 pm_runtime_set_suspended(dev); 1623 pm_runtime_put_noidle(dev); 1624disable_clks: 1625 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1626assert_reset: 1627 reset_control_assert(dwc->reset); 1628 1629 return ret; 1630} 1631 1632static int dwc3_remove(struct platform_device *pdev) 1633{ 1634 struct dwc3 *dwc = platform_get_drvdata(pdev); 1635 1636 pm_runtime_get_sync(&pdev->dev); 1637 1638 dwc3_core_exit_mode(dwc); 1639 dwc3_debugfs_exit(dwc); 1640 1641 dwc3_core_exit(dwc); 1642 dwc3_ulpi_exit(dwc); 1643 1644 pm_runtime_allow(&pdev->dev); 1645 pm_runtime_disable(&pdev->dev); 1646 pm_runtime_put_noidle(&pdev->dev); 1647 pm_runtime_set_suspended(&pdev->dev); 1648 1649 dwc3_free_event_buffers(dwc); 1650 dwc3_free_scratch_buffers(dwc); 1651 1652 return 0; 1653} 1654 1655#ifdef CONFIG_PM 1656static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1657{ 1658 int ret; 1659 1660 ret = reset_control_deassert(dwc->reset); 1661 if (ret) 1662 return ret; 1663 1664 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1665 if (ret) 1666 goto assert_reset; 1667 1668 ret = dwc3_core_init(dwc); 1669 if (ret) 1670 goto disable_clks; 1671 1672 return 0; 1673 1674disable_clks: 1675 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1676assert_reset: 1677 reset_control_assert(dwc->reset); 1678 1679 return ret; 1680} 1681 1682static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1683{ 1684 unsigned long flags; 1685 u32 reg; 1686 1687 switch (dwc->current_dr_role) { 1688 case DWC3_GCTL_PRTCAP_DEVICE: 1689 if (pm_runtime_suspended(dwc->dev)) 1690 break; 1691 spin_lock_irqsave(&dwc->lock, flags); 1692 dwc3_gadget_suspend(dwc); 1693 spin_unlock_irqrestore(&dwc->lock, flags); 1694 synchronize_irq(dwc->irq_gadget); 1695 dwc3_core_exit(dwc); 1696 break; 1697 case DWC3_GCTL_PRTCAP_HOST: 1698 if (!PMSG_IS_AUTO(msg)) { 1699 dwc3_core_exit(dwc); 1700 break; 1701 } 1702 1703 /* Let controller to suspend HSPHY before PHY driver suspends */ 1704 if (dwc->dis_u2_susphy_quirk || 1705 dwc->dis_enblslpm_quirk) { 1706 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1707 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1708 DWC3_GUSB2PHYCFG_SUSPHY; 1709 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1710 1711 /* Give some time for USB2 PHY to suspend */ 1712 usleep_range(5000, 6000); 1713 } 1714 1715 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1716 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1717 break; 1718 case DWC3_GCTL_PRTCAP_OTG: 1719 /* do nothing during runtime_suspend */ 1720 if (PMSG_IS_AUTO(msg)) 1721 break; 1722 1723 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1724 spin_lock_irqsave(&dwc->lock, flags); 1725 dwc3_gadget_suspend(dwc); 1726 spin_unlock_irqrestore(&dwc->lock, flags); 1727 synchronize_irq(dwc->irq_gadget); 1728 } 1729 1730 dwc3_otg_exit(dwc); 1731 dwc3_core_exit(dwc); 1732 break; 1733 default: 1734 /* do nothing */ 1735 break; 1736 } 1737 1738 return 0; 1739} 1740 1741static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1742{ 1743 unsigned long flags; 1744 int ret; 1745 u32 reg; 1746 1747 switch (dwc->current_dr_role) { 1748 case DWC3_GCTL_PRTCAP_DEVICE: 1749 ret = dwc3_core_init_for_resume(dwc); 1750 if (ret) 1751 return ret; 1752 1753 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1754 spin_lock_irqsave(&dwc->lock, flags); 1755 dwc3_gadget_resume(dwc); 1756 spin_unlock_irqrestore(&dwc->lock, flags); 1757 break; 1758 case DWC3_GCTL_PRTCAP_HOST: 1759 if (!PMSG_IS_AUTO(msg)) { 1760 ret = dwc3_core_init_for_resume(dwc); 1761 if (ret) 1762 return ret; 1763 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1764 break; 1765 } 1766 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1767 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1768 if (dwc->dis_u2_susphy_quirk) 1769 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1770 1771 if (dwc->dis_enblslpm_quirk) 1772 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1773 1774 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1775 1776 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1777 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1778 break; 1779 case DWC3_GCTL_PRTCAP_OTG: 1780 /* nothing to do on runtime_resume */ 1781 if (PMSG_IS_AUTO(msg)) 1782 break; 1783 1784 ret = dwc3_core_init_for_resume(dwc); 1785 if (ret) 1786 return ret; 1787 1788 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1789 1790 dwc3_otg_init(dwc); 1791 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1792 dwc3_otg_host_init(dwc); 1793 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1794 spin_lock_irqsave(&dwc->lock, flags); 1795 dwc3_gadget_resume(dwc); 1796 spin_unlock_irqrestore(&dwc->lock, flags); 1797 } 1798 1799 break; 1800 default: 1801 /* do nothing */ 1802 break; 1803 } 1804 1805 return 0; 1806} 1807 1808static int dwc3_runtime_checks(struct dwc3 *dwc) 1809{ 1810 switch (dwc->current_dr_role) { 1811 case DWC3_GCTL_PRTCAP_DEVICE: 1812 if (dwc->connected) 1813 return -EBUSY; 1814 break; 1815 case DWC3_GCTL_PRTCAP_HOST: 1816 default: 1817 /* do nothing */ 1818 break; 1819 } 1820 1821 return 0; 1822} 1823 1824static int dwc3_runtime_suspend(struct device *dev) 1825{ 1826 struct dwc3 *dwc = dev_get_drvdata(dev); 1827 int ret; 1828 1829 if (dwc3_runtime_checks(dwc)) 1830 return -EBUSY; 1831 1832 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1833 if (ret) 1834 return ret; 1835 1836 device_init_wakeup(dev, true); 1837 1838 return 0; 1839} 1840 1841static int dwc3_runtime_resume(struct device *dev) 1842{ 1843 struct dwc3 *dwc = dev_get_drvdata(dev); 1844 int ret; 1845 1846 device_init_wakeup(dev, false); 1847 1848 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1849 if (ret) 1850 return ret; 1851 1852 switch (dwc->current_dr_role) { 1853 case DWC3_GCTL_PRTCAP_DEVICE: 1854 dwc3_gadget_process_pending_events(dwc); 1855 break; 1856 case DWC3_GCTL_PRTCAP_HOST: 1857 default: 1858 /* do nothing */ 1859 break; 1860 } 1861 1862 pm_runtime_mark_last_busy(dev); 1863 1864 return 0; 1865} 1866 1867static int dwc3_runtime_idle(struct device *dev) 1868{ 1869 struct dwc3 *dwc = dev_get_drvdata(dev); 1870 1871 switch (dwc->current_dr_role) { 1872 case DWC3_GCTL_PRTCAP_DEVICE: 1873 if (dwc3_runtime_checks(dwc)) 1874 return -EBUSY; 1875 break; 1876 case DWC3_GCTL_PRTCAP_HOST: 1877 default: 1878 /* do nothing */ 1879 break; 1880 } 1881 1882 pm_runtime_mark_last_busy(dev); 1883 pm_runtime_autosuspend(dev); 1884 1885 return 0; 1886} 1887#endif /* CONFIG_PM */ 1888 1889#ifdef CONFIG_PM_SLEEP 1890static int dwc3_suspend(struct device *dev) 1891{ 1892 struct dwc3 *dwc = dev_get_drvdata(dev); 1893 int ret; 1894 1895 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1896 if (ret) 1897 return ret; 1898 1899 pinctrl_pm_select_sleep_state(dev); 1900 1901 return 0; 1902} 1903 1904static int dwc3_resume(struct device *dev) 1905{ 1906 struct dwc3 *dwc = dev_get_drvdata(dev); 1907 int ret; 1908 1909 pinctrl_pm_select_default_state(dev); 1910 1911 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1912 if (ret) 1913 return ret; 1914 1915 pm_runtime_disable(dev); 1916 pm_runtime_set_active(dev); 1917 pm_runtime_enable(dev); 1918 1919 return 0; 1920} 1921 1922static void dwc3_complete(struct device *dev) 1923{ 1924 struct dwc3 *dwc = dev_get_drvdata(dev); 1925 u32 reg; 1926 1927 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 1928 dwc->dis_split_quirk) { 1929 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 1930 reg |= DWC3_GUCTL3_SPLITDISABLE; 1931 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 1932 } 1933} 1934#else 1935#define dwc3_complete NULL 1936#endif /* CONFIG_PM_SLEEP */ 1937 1938static const struct dev_pm_ops dwc3_dev_pm_ops = { 1939 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1940 .complete = dwc3_complete, 1941 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1942 dwc3_runtime_idle) 1943}; 1944 1945#ifdef CONFIG_OF 1946static const struct of_device_id of_dwc3_match[] = { 1947 { 1948 .compatible = "snps,dwc3" 1949 }, 1950 { 1951 .compatible = "synopsys,dwc3" 1952 }, 1953 { }, 1954}; 1955MODULE_DEVICE_TABLE(of, of_dwc3_match); 1956#endif 1957 1958#ifdef CONFIG_ACPI 1959 1960#define ACPI_ID_INTEL_BSW "808622B7" 1961 1962static const struct acpi_device_id dwc3_acpi_match[] = { 1963 { ACPI_ID_INTEL_BSW, 0 }, 1964 { }, 1965}; 1966MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1967#endif 1968 1969static struct platform_driver dwc3_driver = { 1970 .probe = dwc3_probe, 1971 .remove = dwc3_remove, 1972 .driver = { 1973 .name = "dwc3", 1974 .of_match_table = of_match_ptr(of_dwc3_match), 1975 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1976 .pm = &dwc3_dev_pm_ops, 1977 }, 1978}; 1979 1980module_platform_driver(dwc3_driver); 1981 1982MODULE_ALIAS("platform:dwc3"); 1983MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1984MODULE_LICENSE("GPL v2"); 1985MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1986