1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/of_device.h> 39 40#include "core.h" 41 42static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 43{ 44 struct dwc2_core_params *p = &hsotg->params; 45 46 p->host_rx_fifo_size = 774; 47 p->max_transfer_size = 65535; 48 p->max_packet_count = 511; 49 p->ahbcfg = 0x10; 50} 51 52static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53{ 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->change_speed_quirk = true; 71 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 72} 73 74static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 75{ 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 79 p->phy_utmi_width = 8; 80} 81 82static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 83{ 84 struct dwc2_core_params *p = &hsotg->params; 85 86 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 87 p->host_rx_fifo_size = 525; 88 p->host_nperio_tx_fifo_size = 128; 89 p->host_perio_tx_fifo_size = 256; 90 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 91 GAHBCFG_HBSTLEN_SHIFT; 92 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 93} 94 95static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 96{ 97 struct dwc2_core_params *p = &hsotg->params; 98 99 p->otg_cap = 2; 100 p->host_rx_fifo_size = 288; 101 p->host_nperio_tx_fifo_size = 128; 102 p->host_perio_tx_fifo_size = 96; 103 p->max_transfer_size = 65535; 104 p->max_packet_count = 511; 105 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 106 GAHBCFG_HBSTLEN_SHIFT; 107} 108 109static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 110{ 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 114 p->speed = DWC2_SPEED_PARAM_HIGH; 115 p->host_rx_fifo_size = 512; 116 p->host_nperio_tx_fifo_size = 500; 117 p->host_perio_tx_fifo_size = 500; 118 p->host_channels = 16; 119 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 121 GAHBCFG_HBSTLEN_SHIFT; 122 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 123} 124 125static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 126{ 127 struct dwc2_core_params *p = &hsotg->params; 128 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133} 134 135static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 136{ 137 struct dwc2_core_params *p = &hsotg->params; 138 139 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 140} 141 142static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 143{ 144 struct dwc2_core_params *p = &hsotg->params; 145 146 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 147 p->speed = DWC2_SPEED_PARAM_FULL; 148 p->host_rx_fifo_size = 128; 149 p->host_nperio_tx_fifo_size = 96; 150 p->host_perio_tx_fifo_size = 96; 151 p->max_packet_count = 256; 152 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 153 p->i2c_enable = false; 154 p->activate_stm_fs_transceiver = true; 155} 156 157static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 158{ 159 struct dwc2_core_params *p = &hsotg->params; 160 161 p->host_rx_fifo_size = 622; 162 p->host_nperio_tx_fifo_size = 128; 163 p->host_perio_tx_fifo_size = 256; 164} 165 166static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 167{ 168 struct dwc2_core_params *p = &hsotg->params; 169 170 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 171 p->speed = DWC2_SPEED_PARAM_FULL; 172 p->host_rx_fifo_size = 128; 173 p->host_nperio_tx_fifo_size = 96; 174 p->host_perio_tx_fifo_size = 96; 175 p->max_packet_count = 256; 176 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 177 p->i2c_enable = false; 178 p->activate_stm_fs_transceiver = true; 179 p->activate_stm_id_vb_detection = true; 180 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 181} 182 183static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 184{ 185 struct dwc2_core_params *p = &hsotg->params; 186 187 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 188 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 189 p->host_rx_fifo_size = 440; 190 p->host_nperio_tx_fifo_size = 256; 191 p->host_perio_tx_fifo_size = 256; 192 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 193} 194 195const struct of_device_id dwc2_of_match_table[] = { 196 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 197 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 198 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 199 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 200 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 201 { .compatible = "snps,dwc2" }, 202 { .compatible = "samsung,s3c6400-hsotg", 203 .data = dwc2_set_s3c6400_params }, 204 { .compatible = "amlogic,meson8-usb", 205 .data = dwc2_set_amlogic_params }, 206 { .compatible = "amlogic,meson8b-usb", 207 .data = dwc2_set_amlogic_params }, 208 { .compatible = "amlogic,meson-gxbb-usb", 209 .data = dwc2_set_amlogic_params }, 210 { .compatible = "amlogic,meson-g12a-usb", 211 .data = dwc2_set_amlogic_g12a_params }, 212 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 213 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 214 { .compatible = "st,stm32f4x9-fsotg", 215 .data = dwc2_set_stm32f4x9_fsotg_params }, 216 { .compatible = "st,stm32f4x9-hsotg" }, 217 { .compatible = "st,stm32f7-hsotg", 218 .data = dwc2_set_stm32f7_hsotg_params }, 219 { .compatible = "st,stm32mp15-fsotg", 220 .data = dwc2_set_stm32mp15_fsotg_params }, 221 { .compatible = "st,stm32mp15-hsotg", 222 .data = dwc2_set_stm32mp15_hsotg_params }, 223 {}, 224}; 225MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 226 227static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 228{ 229 u8 val; 230 231 switch (hsotg->hw_params.op_mode) { 232 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 233 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 234 break; 235 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 236 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 237 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 238 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 239 break; 240 default: 241 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 242 break; 243 } 244 245 hsotg->params.otg_cap = val; 246} 247 248static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 249{ 250 int val; 251 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 252 253 val = DWC2_PHY_TYPE_PARAM_FS; 254 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 255 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 256 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 257 val = DWC2_PHY_TYPE_PARAM_UTMI; 258 else 259 val = DWC2_PHY_TYPE_PARAM_ULPI; 260 } 261 262 if (dwc2_is_fs_iot(hsotg)) 263 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 264 265 hsotg->params.phy_type = val; 266} 267 268static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 269{ 270 int val; 271 272 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 273 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 274 275 if (dwc2_is_fs_iot(hsotg)) 276 val = DWC2_SPEED_PARAM_FULL; 277 278 if (dwc2_is_hs_iot(hsotg)) 279 val = DWC2_SPEED_PARAM_HIGH; 280 281 hsotg->params.speed = val; 282} 283 284static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 285{ 286 int val; 287 288 val = (hsotg->hw_params.utmi_phy_data_width == 289 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 290 291 if (hsotg->phy) { 292 /* 293 * If using the generic PHY framework, check if the PHY bus 294 * width is 8-bit and set the phyif appropriately. 295 */ 296 if (phy_get_bus_width(hsotg->phy) == 8) 297 val = 8; 298 } 299 300 hsotg->params.phy_utmi_width = val; 301} 302 303static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 304{ 305 struct dwc2_core_params *p = &hsotg->params; 306 int depth_average; 307 int fifo_count; 308 int i; 309 310 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 311 312 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 313 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 314 for (i = 1; i <= fifo_count; i++) 315 p->g_tx_fifo_size[i] = depth_average; 316} 317 318static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 319{ 320 int val; 321 322 if (hsotg->hw_params.hibernation) 323 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 324 else if (hsotg->hw_params.power_optimized) 325 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 326 else 327 val = DWC2_POWER_DOWN_PARAM_NONE; 328 329 hsotg->params.power_down = val; 330} 331 332static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 333{ 334 struct dwc2_core_params *p = &hsotg->params; 335 336 p->lpm = hsotg->hw_params.lpm_mode; 337 if (p->lpm) { 338 p->lpm_clock_gating = true; 339 p->besl = true; 340 p->hird_threshold_en = true; 341 p->hird_threshold = 4; 342 } else { 343 p->lpm_clock_gating = false; 344 p->besl = false; 345 p->hird_threshold_en = false; 346 } 347} 348 349/** 350 * dwc2_set_default_params() - Set all core parameters to their 351 * auto-detected default values. 352 * 353 * @hsotg: Programming view of the DWC_otg controller 354 * 355 */ 356static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 357{ 358 struct dwc2_hw_params *hw = &hsotg->hw_params; 359 struct dwc2_core_params *p = &hsotg->params; 360 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 361 362 dwc2_set_param_otg_cap(hsotg); 363 dwc2_set_param_phy_type(hsotg); 364 dwc2_set_param_speed(hsotg); 365 dwc2_set_param_phy_utmi_width(hsotg); 366 dwc2_set_param_power_down(hsotg); 367 dwc2_set_param_lpm(hsotg); 368 p->phy_ulpi_ddr = false; 369 p->phy_ulpi_ext_vbus = false; 370 371 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 372 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 373 p->i2c_enable = hw->i2c_enable; 374 p->acg_enable = hw->acg_enable; 375 p->ulpi_fs_ls = false; 376 p->ts_dline = false; 377 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 378 p->uframe_sched = true; 379 p->external_id_pin_ctl = false; 380 p->ipg_isoc_en = false; 381 p->service_interval = false; 382 p->max_packet_count = hw->max_packet_count; 383 p->max_transfer_size = hw->max_transfer_size; 384 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 385 p->ref_clk_per = 33333; 386 p->sof_cnt_wkup_alert = 100; 387 388 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 389 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 390 p->host_dma = dma_capable; 391 p->dma_desc_enable = false; 392 p->dma_desc_fs_enable = false; 393 p->host_support_fs_ls_low_power = false; 394 p->host_ls_low_power_phy_clk = false; 395 p->host_channels = hw->host_channels; 396 p->host_rx_fifo_size = hw->rx_fifo_size; 397 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 398 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 399 } 400 401 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 402 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 403 p->g_dma = dma_capable; 404 p->g_dma_desc = hw->dma_desc_enable; 405 406 /* 407 * The values for g_rx_fifo_size (2048) and 408 * g_np_tx_fifo_size (1024) come from the legacy s3c 409 * gadget driver. These defaults have been hard-coded 410 * for some time so many platforms depend on these 411 * values. Leave them as defaults for now and only 412 * auto-detect if the hardware does not support the 413 * default. 414 */ 415 p->g_rx_fifo_size = 2048; 416 p->g_np_tx_fifo_size = 1024; 417 dwc2_set_param_tx_fifo_sizes(hsotg); 418 } 419} 420 421/** 422 * dwc2_get_device_properties() - Read in device properties. 423 * 424 * @hsotg: Programming view of the DWC_otg controller 425 * 426 * Read in the device properties and adjust core parameters if needed. 427 */ 428static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 429{ 430 struct dwc2_core_params *p = &hsotg->params; 431 int num; 432 433 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 434 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 435 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 436 &p->g_rx_fifo_size); 437 438 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 439 &p->g_np_tx_fifo_size); 440 441 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 442 if (num > 0) { 443 num = min(num, 15); 444 memset(p->g_tx_fifo_size, 0, 445 sizeof(p->g_tx_fifo_size)); 446 device_property_read_u32_array(hsotg->dev, 447 "g-tx-fifo-size", 448 &p->g_tx_fifo_size[1], 449 num); 450 } 451 } 452 453 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 454 p->oc_disable = true; 455} 456 457static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 458{ 459 int valid = 1; 460 461 switch (hsotg->params.otg_cap) { 462 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 463 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 464 valid = 0; 465 break; 466 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 467 switch (hsotg->hw_params.op_mode) { 468 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 469 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 470 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 471 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 472 break; 473 default: 474 valid = 0; 475 break; 476 } 477 break; 478 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 479 /* always valid */ 480 break; 481 default: 482 valid = 0; 483 break; 484 } 485 486 if (!valid) 487 dwc2_set_param_otg_cap(hsotg); 488} 489 490static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 491{ 492 int valid = 0; 493 u32 hs_phy_type; 494 u32 fs_phy_type; 495 496 hs_phy_type = hsotg->hw_params.hs_phy_type; 497 fs_phy_type = hsotg->hw_params.fs_phy_type; 498 499 switch (hsotg->params.phy_type) { 500 case DWC2_PHY_TYPE_PARAM_FS: 501 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 502 valid = 1; 503 break; 504 case DWC2_PHY_TYPE_PARAM_UTMI: 505 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 506 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 507 valid = 1; 508 break; 509 case DWC2_PHY_TYPE_PARAM_ULPI: 510 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 511 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 512 valid = 1; 513 break; 514 default: 515 break; 516 } 517 518 if (!valid) 519 dwc2_set_param_phy_type(hsotg); 520} 521 522static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 523{ 524 int valid = 1; 525 int phy_type = hsotg->params.phy_type; 526 int speed = hsotg->params.speed; 527 528 switch (speed) { 529 case DWC2_SPEED_PARAM_HIGH: 530 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 531 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 532 valid = 0; 533 break; 534 case DWC2_SPEED_PARAM_FULL: 535 case DWC2_SPEED_PARAM_LOW: 536 break; 537 default: 538 valid = 0; 539 break; 540 } 541 542 if (!valid) 543 dwc2_set_param_speed(hsotg); 544} 545 546static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 547{ 548 int valid = 0; 549 int param = hsotg->params.phy_utmi_width; 550 int width = hsotg->hw_params.utmi_phy_data_width; 551 552 switch (width) { 553 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 554 valid = (param == 8); 555 break; 556 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 557 valid = (param == 16); 558 break; 559 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 560 valid = (param == 8 || param == 16); 561 break; 562 } 563 564 if (!valid) 565 dwc2_set_param_phy_utmi_width(hsotg); 566} 567 568static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 569{ 570 int param = hsotg->params.power_down; 571 572 switch (param) { 573 case DWC2_POWER_DOWN_PARAM_NONE: 574 break; 575 case DWC2_POWER_DOWN_PARAM_PARTIAL: 576 if (hsotg->hw_params.power_optimized) 577 break; 578 dev_dbg(hsotg->dev, 579 "Partial power down isn't supported by HW\n"); 580 param = DWC2_POWER_DOWN_PARAM_NONE; 581 break; 582 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 583 if (hsotg->hw_params.hibernation) 584 break; 585 dev_dbg(hsotg->dev, 586 "Hibernation isn't supported by HW\n"); 587 param = DWC2_POWER_DOWN_PARAM_NONE; 588 break; 589 default: 590 dev_err(hsotg->dev, 591 "%s: Invalid parameter power_down=%d\n", 592 __func__, param); 593 param = DWC2_POWER_DOWN_PARAM_NONE; 594 break; 595 } 596 597 hsotg->params.power_down = param; 598} 599 600static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 601{ 602 int fifo_count; 603 int fifo; 604 int min; 605 u32 total = 0; 606 u32 dptxfszn; 607 608 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 609 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 610 611 for (fifo = 1; fifo <= fifo_count; fifo++) 612 total += hsotg->params.g_tx_fifo_size[fifo]; 613 614 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 615 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 616 __func__); 617 dwc2_set_param_tx_fifo_sizes(hsotg); 618 } 619 620 for (fifo = 1; fifo <= fifo_count; fifo++) { 621 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 622 623 if (hsotg->params.g_tx_fifo_size[fifo] < min || 624 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 625 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 626 __func__, fifo, 627 hsotg->params.g_tx_fifo_size[fifo]); 628 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 629 } 630 } 631} 632 633#define CHECK_RANGE(_param, _min, _max, _def) do { \ 634 if ((int)(hsotg->params._param) < (_min) || \ 635 (hsotg->params._param) > (_max)) { \ 636 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 637 __func__, #_param, hsotg->params._param); \ 638 hsotg->params._param = (_def); \ 639 } \ 640 } while (0) 641 642#define CHECK_BOOL(_param, _check) do { \ 643 if (hsotg->params._param && !(_check)) { \ 644 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 645 __func__, #_param, hsotg->params._param); \ 646 hsotg->params._param = false; \ 647 } \ 648 } while (0) 649 650static void dwc2_check_params(struct dwc2_hsotg *hsotg) 651{ 652 struct dwc2_hw_params *hw = &hsotg->hw_params; 653 struct dwc2_core_params *p = &hsotg->params; 654 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 655 656 dwc2_check_param_otg_cap(hsotg); 657 dwc2_check_param_phy_type(hsotg); 658 dwc2_check_param_speed(hsotg); 659 dwc2_check_param_phy_utmi_width(hsotg); 660 dwc2_check_param_power_down(hsotg); 661 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 662 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 663 CHECK_BOOL(i2c_enable, hw->i2c_enable); 664 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 665 CHECK_BOOL(acg_enable, hw->acg_enable); 666 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 667 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 668 CHECK_BOOL(lpm, hw->lpm_mode); 669 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 670 CHECK_BOOL(besl, hsotg->params.lpm); 671 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 672 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 673 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 674 CHECK_BOOL(service_interval, hw->service_interval_mode); 675 CHECK_RANGE(max_packet_count, 676 15, hw->max_packet_count, 677 hw->max_packet_count); 678 CHECK_RANGE(max_transfer_size, 679 2047, hw->max_transfer_size, 680 hw->max_transfer_size); 681 682 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 683 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 684 CHECK_BOOL(host_dma, dma_capable); 685 CHECK_BOOL(dma_desc_enable, p->host_dma); 686 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 687 CHECK_BOOL(host_ls_low_power_phy_clk, 688 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 689 CHECK_RANGE(host_channels, 690 1, hw->host_channels, 691 hw->host_channels); 692 CHECK_RANGE(host_rx_fifo_size, 693 16, hw->rx_fifo_size, 694 hw->rx_fifo_size); 695 CHECK_RANGE(host_nperio_tx_fifo_size, 696 16, hw->host_nperio_tx_fifo_size, 697 hw->host_nperio_tx_fifo_size); 698 CHECK_RANGE(host_perio_tx_fifo_size, 699 16, hw->host_perio_tx_fifo_size, 700 hw->host_perio_tx_fifo_size); 701 } 702 703 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 704 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 705 CHECK_BOOL(g_dma, dma_capable); 706 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 707 CHECK_RANGE(g_rx_fifo_size, 708 16, hw->rx_fifo_size, 709 hw->rx_fifo_size); 710 CHECK_RANGE(g_np_tx_fifo_size, 711 16, hw->dev_nperio_tx_fifo_size, 712 hw->dev_nperio_tx_fifo_size); 713 dwc2_check_param_tx_fifo_sizes(hsotg); 714 } 715} 716 717/* 718 * Gets host hardware parameters. Forces host mode if not currently in 719 * host mode. Should be called immediately after a core soft reset in 720 * order to get the reset values. 721 */ 722static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 723{ 724 struct dwc2_hw_params *hw = &hsotg->hw_params; 725 u32 gnptxfsiz; 726 u32 hptxfsiz; 727 728 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 729 return; 730 731 dwc2_force_mode(hsotg, true); 732 733 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 734 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 735 736 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 737 FIFOSIZE_DEPTH_SHIFT; 738 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 739 FIFOSIZE_DEPTH_SHIFT; 740} 741 742/* 743 * Gets device hardware parameters. Forces device mode if not 744 * currently in device mode. Should be called immediately after a core 745 * soft reset in order to get the reset values. 746 */ 747static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 748{ 749 struct dwc2_hw_params *hw = &hsotg->hw_params; 750 u32 gnptxfsiz; 751 int fifo, fifo_count; 752 753 if (hsotg->dr_mode == USB_DR_MODE_HOST) 754 return; 755 756 dwc2_force_mode(hsotg, false); 757 758 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 759 760 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 761 762 for (fifo = 1; fifo <= fifo_count; fifo++) { 763 hw->g_tx_fifo_size[fifo] = 764 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 765 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 766 } 767 768 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 769 FIFOSIZE_DEPTH_SHIFT; 770} 771 772/** 773 * During device initialization, read various hardware configuration 774 * registers and interpret the contents. 775 * 776 * @hsotg: Programming view of the DWC_otg controller 777 * 778 */ 779int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 780{ 781 struct dwc2_hw_params *hw = &hsotg->hw_params; 782 unsigned int width; 783 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 784 u32 grxfsiz; 785 786 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 787 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 788 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 789 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 790 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 791 792 /* hwcfg1 */ 793 hw->dev_ep_dirs = hwcfg1; 794 795 /* hwcfg2 */ 796 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 797 GHWCFG2_OP_MODE_SHIFT; 798 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 799 GHWCFG2_ARCHITECTURE_SHIFT; 800 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 801 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 802 GHWCFG2_NUM_HOST_CHAN_SHIFT); 803 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 804 GHWCFG2_HS_PHY_TYPE_SHIFT; 805 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 806 GHWCFG2_FS_PHY_TYPE_SHIFT; 807 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 808 GHWCFG2_NUM_DEV_EP_SHIFT; 809 hw->nperio_tx_q_depth = 810 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 811 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 812 hw->host_perio_tx_q_depth = 813 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 814 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 815 hw->dev_token_q_depth = 816 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 817 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 818 819 /* hwcfg3 */ 820 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 821 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 822 hw->max_transfer_size = (1 << (width + 11)) - 1; 823 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 824 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 825 hw->max_packet_count = (1 << (width + 4)) - 1; 826 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 827 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 828 GHWCFG3_DFIFO_DEPTH_SHIFT; 829 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 830 831 /* hwcfg4 */ 832 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 833 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 834 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 835 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 836 GHWCFG4_NUM_IN_EPS_SHIFT; 837 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 838 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 839 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 840 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 841 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 842 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 843 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 844 hw->service_interval_mode = !!(hwcfg4 & 845 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 846 847 /* fifo sizes */ 848 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 849 GRXFSIZ_DEPTH_SHIFT; 850 /* 851 * Host specific hardware parameters. Reading these parameters 852 * requires the controller to be in host mode. The mode will 853 * be forced, if necessary, to read these values. 854 */ 855 dwc2_get_host_hwparams(hsotg); 856 dwc2_get_dev_hwparams(hsotg); 857 858 return 0; 859} 860 861int dwc2_init_params(struct dwc2_hsotg *hsotg) 862{ 863 const struct of_device_id *match; 864 void (*set_params)(struct dwc2_hsotg *data); 865 866 dwc2_set_default_params(hsotg); 867 dwc2_get_device_properties(hsotg); 868 869 match = of_match_device(dwc2_of_match_table, hsotg->dev); 870 if (match && match->data) { 871 set_params = match->data; 872 set_params(hsotg); 873 } 874 875 dwc2_check_params(hsotg); 876 877 return 0; 878} 879