1// SPDX-License-Identifier: GPL-2.0 2/* 3 * core.c - ChipIdea USB IP core family device controller 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2020 NXP 7 * 8 * Author: David Lopo 9 * Peter Chen <peter.chen@nxp.com> 10 * 11 * Main Features: 12 * - Four transfers are supported, usbtest is passed 13 * - USB Certification for gadget: CH9 and Mass Storage are passed 14 * - Low power mode 15 * - USB wakeup 16 */ 17#include <linux/delay.h> 18#include <linux/device.h> 19#include <linux/dma-mapping.h> 20#include <linux/extcon.h> 21#include <linux/phy/phy.h> 22#include <linux/platform_device.h> 23#include <linux/module.h> 24#include <linux/idr.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/kernel.h> 28#include <linux/slab.h> 29#include <linux/pm_runtime.h> 30#include <linux/pinctrl/consumer.h> 31#include <linux/usb/ch9.h> 32#include <linux/usb/gadget.h> 33#include <linux/usb/otg.h> 34#include <linux/usb/chipidea.h> 35#include <linux/usb/of.h> 36#include <linux/of.h> 37#include <linux/regulator/consumer.h> 38#include <linux/usb/ehci_def.h> 39 40#include "ci.h" 41#include "udc.h" 42#include "bits.h" 43#include "host.h" 44#include "otg.h" 45#include "otg_fsm.h" 46 47/* Controller register map */ 48static const u8 ci_regs_nolpm[] = { 49 [CAP_CAPLENGTH] = 0x00U, 50 [CAP_HCCPARAMS] = 0x08U, 51 [CAP_DCCPARAMS] = 0x24U, 52 [CAP_TESTMODE] = 0x38U, 53 [OP_USBCMD] = 0x00U, 54 [OP_USBSTS] = 0x04U, 55 [OP_USBINTR] = 0x08U, 56 [OP_DEVICEADDR] = 0x14U, 57 [OP_ENDPTLISTADDR] = 0x18U, 58 [OP_TTCTRL] = 0x1CU, 59 [OP_BURSTSIZE] = 0x20U, 60 [OP_ULPI_VIEWPORT] = 0x30U, 61 [OP_PORTSC] = 0x44U, 62 [OP_DEVLC] = 0x84U, 63 [OP_OTGSC] = 0x64U, 64 [OP_USBMODE] = 0x68U, 65 [OP_ENDPTSETUPSTAT] = 0x6CU, 66 [OP_ENDPTPRIME] = 0x70U, 67 [OP_ENDPTFLUSH] = 0x74U, 68 [OP_ENDPTSTAT] = 0x78U, 69 [OP_ENDPTCOMPLETE] = 0x7CU, 70 [OP_ENDPTCTRL] = 0x80U, 71}; 72 73static const u8 ci_regs_lpm[] = { 74 [CAP_CAPLENGTH] = 0x00U, 75 [CAP_HCCPARAMS] = 0x08U, 76 [CAP_DCCPARAMS] = 0x24U, 77 [CAP_TESTMODE] = 0xFCU, 78 [OP_USBCMD] = 0x00U, 79 [OP_USBSTS] = 0x04U, 80 [OP_USBINTR] = 0x08U, 81 [OP_DEVICEADDR] = 0x14U, 82 [OP_ENDPTLISTADDR] = 0x18U, 83 [OP_TTCTRL] = 0x1CU, 84 [OP_BURSTSIZE] = 0x20U, 85 [OP_ULPI_VIEWPORT] = 0x30U, 86 [OP_PORTSC] = 0x44U, 87 [OP_DEVLC] = 0x84U, 88 [OP_OTGSC] = 0xC4U, 89 [OP_USBMODE] = 0xC8U, 90 [OP_ENDPTSETUPSTAT] = 0xD8U, 91 [OP_ENDPTPRIME] = 0xDCU, 92 [OP_ENDPTFLUSH] = 0xE0U, 93 [OP_ENDPTSTAT] = 0xE4U, 94 [OP_ENDPTCOMPLETE] = 0xE8U, 95 [OP_ENDPTCTRL] = 0xECU, 96}; 97 98static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 99{ 100 int i; 101 102 for (i = 0; i < OP_ENDPTCTRL; i++) 103 ci->hw_bank.regmap[i] = 104 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 105 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 106 107 for (; i <= OP_LAST; i++) 108 ci->hw_bank.regmap[i] = ci->hw_bank.op + 109 4 * (i - OP_ENDPTCTRL) + 110 (is_lpm 111 ? ci_regs_lpm[OP_ENDPTCTRL] 112 : ci_regs_nolpm[OP_ENDPTCTRL]); 113 114} 115 116static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 117{ 118 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 119 enum ci_revision rev = CI_REVISION_UNKNOWN; 120 121 if (ver == 0x2) { 122 rev = hw_read_id_reg(ci, ID_ID, REVISION) 123 >> __ffs(REVISION); 124 rev += CI_REVISION_20; 125 } else if (ver == 0x0) { 126 rev = CI_REVISION_1X; 127 } 128 129 return rev; 130} 131 132/** 133 * hw_read_intr_enable: returns interrupt enable register 134 * 135 * @ci: the controller 136 * 137 * This function returns register data 138 */ 139u32 hw_read_intr_enable(struct ci_hdrc *ci) 140{ 141 return hw_read(ci, OP_USBINTR, ~0); 142} 143 144/** 145 * hw_read_intr_status: returns interrupt status register 146 * 147 * @ci: the controller 148 * 149 * This function returns register data 150 */ 151u32 hw_read_intr_status(struct ci_hdrc *ci) 152{ 153 return hw_read(ci, OP_USBSTS, ~0); 154} 155 156/** 157 * hw_port_test_set: writes port test mode (execute without interruption) 158 * @ci: the controller 159 * @mode: new value 160 * 161 * This function returns an error code 162 */ 163int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 164{ 165 const u8 TEST_MODE_MAX = 7; 166 167 if (mode > TEST_MODE_MAX) 168 return -EINVAL; 169 170 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 171 return 0; 172} 173 174/** 175 * hw_port_test_get: reads port test mode value 176 * 177 * @ci: the controller 178 * 179 * This function returns port test mode value 180 */ 181u8 hw_port_test_get(struct ci_hdrc *ci) 182{ 183 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 184} 185 186static void hw_wait_phy_stable(void) 187{ 188 /* 189 * The phy needs some delay to output the stable status from low 190 * power mode. And for OTGSC, the status inputs are debounced 191 * using a 1 ms time constant, so, delay 2ms for controller to get 192 * the stable status, like vbus and id when the phy leaves low power. 193 */ 194 usleep_range(2000, 2500); 195} 196 197/* The PHY enters/leaves low power mode */ 198static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 199{ 200 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 201 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 202 203 if (enable && !lpm) 204 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 205 PORTSC_PHCD(ci->hw_bank.lpm)); 206 else if (!enable && lpm) 207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 208 0); 209} 210 211static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 212{ 213 u32 reg; 214 215 /* bank is a module variable */ 216 ci->hw_bank.abs = base; 217 218 ci->hw_bank.cap = ci->hw_bank.abs; 219 ci->hw_bank.cap += ci->platdata->capoffset; 220 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 221 222 hw_alloc_regmap(ci, false); 223 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 224 __ffs(HCCPARAMS_LEN); 225 ci->hw_bank.lpm = reg; 226 if (reg) 227 hw_alloc_regmap(ci, !!reg); 228 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 229 ci->hw_bank.size += OP_LAST; 230 ci->hw_bank.size /= sizeof(u32); 231 232 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 233 __ffs(DCCPARAMS_DEN); 234 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 235 236 if (ci->hw_ep_max > ENDPT_MAX) 237 return -ENODEV; 238 239 ci_hdrc_enter_lpm(ci, false); 240 241 /* Disable all interrupts bits */ 242 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 243 244 /* Clear all interrupts status bits*/ 245 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 246 247 ci->rev = ci_get_revision(ci); 248 249 dev_dbg(ci->dev, 250 "revision: %d, lpm: %d; cap: %px op: %px\n", 251 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 252 253 /* setup lock mode ? */ 254 255 /* ENDPTSETUPSTAT is '0' by default */ 256 257 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 258 259 return 0; 260} 261 262void hw_phymode_configure(struct ci_hdrc *ci) 263{ 264 u32 portsc, lpm, sts = 0; 265 266 switch (ci->platdata->phy_mode) { 267 case USBPHY_INTERFACE_MODE_UTMI: 268 portsc = PORTSC_PTS(PTS_UTMI); 269 lpm = DEVLC_PTS(PTS_UTMI); 270 break; 271 case USBPHY_INTERFACE_MODE_UTMIW: 272 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 273 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 274 break; 275 case USBPHY_INTERFACE_MODE_ULPI: 276 portsc = PORTSC_PTS(PTS_ULPI); 277 lpm = DEVLC_PTS(PTS_ULPI); 278 break; 279 case USBPHY_INTERFACE_MODE_SERIAL: 280 portsc = PORTSC_PTS(PTS_SERIAL); 281 lpm = DEVLC_PTS(PTS_SERIAL); 282 sts = 1; 283 break; 284 case USBPHY_INTERFACE_MODE_HSIC: 285 portsc = PORTSC_PTS(PTS_HSIC); 286 lpm = DEVLC_PTS(PTS_HSIC); 287 break; 288 default: 289 return; 290 } 291 292 if (ci->hw_bank.lpm) { 293 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 294 if (sts) 295 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 296 } else { 297 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 298 if (sts) 299 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 300 } 301} 302EXPORT_SYMBOL_GPL(hw_phymode_configure); 303 304/** 305 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 306 * interfaces 307 * @ci: the controller 308 * 309 * This function returns an error code if the phy failed to init 310 */ 311static int _ci_usb_phy_init(struct ci_hdrc *ci) 312{ 313 int ret; 314 315 if (ci->phy) { 316 ret = phy_init(ci->phy); 317 if (ret) 318 return ret; 319 320 ret = phy_power_on(ci->phy); 321 if (ret) { 322 phy_exit(ci->phy); 323 return ret; 324 } 325 } else { 326 ret = usb_phy_init(ci->usb_phy); 327 } 328 329 return ret; 330} 331 332/** 333 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 334 * interfaces 335 * @ci: the controller 336 */ 337static void ci_usb_phy_exit(struct ci_hdrc *ci) 338{ 339 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 340 return; 341 342 if (ci->phy) { 343 phy_power_off(ci->phy); 344 phy_exit(ci->phy); 345 } else { 346 usb_phy_shutdown(ci->usb_phy); 347 } 348} 349 350/** 351 * ci_usb_phy_init: initialize phy according to different phy type 352 * @ci: the controller 353 * 354 * This function returns an error code if usb_phy_init has failed 355 */ 356static int ci_usb_phy_init(struct ci_hdrc *ci) 357{ 358 int ret; 359 360 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 361 return 0; 362 363 switch (ci->platdata->phy_mode) { 364 case USBPHY_INTERFACE_MODE_UTMI: 365 case USBPHY_INTERFACE_MODE_UTMIW: 366 case USBPHY_INTERFACE_MODE_HSIC: 367 ret = _ci_usb_phy_init(ci); 368 if (!ret) 369 hw_wait_phy_stable(); 370 else 371 return ret; 372 hw_phymode_configure(ci); 373 break; 374 case USBPHY_INTERFACE_MODE_ULPI: 375 case USBPHY_INTERFACE_MODE_SERIAL: 376 hw_phymode_configure(ci); 377 ret = _ci_usb_phy_init(ci); 378 if (ret) 379 return ret; 380 break; 381 default: 382 ret = _ci_usb_phy_init(ci); 383 if (!ret) 384 hw_wait_phy_stable(); 385 } 386 387 return ret; 388} 389 390 391/** 392 * ci_platform_configure: do controller configure 393 * @ci: the controller 394 * 395 */ 396void ci_platform_configure(struct ci_hdrc *ci) 397{ 398 bool is_device_mode, is_host_mode; 399 400 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 401 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 402 403 if (is_device_mode) { 404 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); 405 406 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) 407 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 408 USBMODE_CI_SDIS); 409 } 410 411 if (is_host_mode) { 412 phy_set_mode(ci->phy, PHY_MODE_USB_HOST); 413 414 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) 415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 416 USBMODE_CI_SDIS); 417 } 418 419 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 420 if (ci->hw_bank.lpm) 421 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 422 else 423 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 424 } 425 426 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 427 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 428 429 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 430 431 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 432 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 433 ci->platdata->ahb_burst_config); 434 435 /* override burst size, take effect only when ahb_burst_config is 0 */ 436 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 437 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 438 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 439 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 440 441 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 442 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 443 ci->platdata->rx_burst_size); 444 } 445} 446 447/** 448 * hw_controller_reset: do controller reset 449 * @ci: the controller 450 * 451 * This function returns an error code 452 */ 453static int hw_controller_reset(struct ci_hdrc *ci) 454{ 455 int count = 0; 456 457 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 458 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 459 udelay(10); 460 if (count++ > 1000) 461 return -ETIMEDOUT; 462 } 463 464 return 0; 465} 466 467/** 468 * hw_device_reset: resets chip (execute without interruption) 469 * @ci: the controller 470 * 471 * This function returns an error code 472 */ 473int hw_device_reset(struct ci_hdrc *ci) 474{ 475 int ret; 476 477 /* should flush & stop before reset */ 478 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 479 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 480 481 ret = hw_controller_reset(ci); 482 if (ret) { 483 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 484 return ret; 485 } 486 487 if (ci->platdata->notify_event) { 488 ret = ci->platdata->notify_event(ci, 489 CI_HDRC_CONTROLLER_RESET_EVENT); 490 if (ret) 491 return ret; 492 } 493 494 /* USBMODE should be configured step by step */ 495 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 496 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 497 /* HW >= 2.3 */ 498 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 499 500 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 501 dev_err(ci->dev, "cannot enter in %s device mode\n", 502 ci_role(ci)->name); 503 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm); 504 return -ENODEV; 505 } 506 507 ci_platform_configure(ci); 508 509 return 0; 510} 511 512static irqreturn_t ci_irq_handler(int irq, void *data) 513{ 514 struct ci_hdrc *ci = data; 515 irqreturn_t ret = IRQ_NONE; 516 u32 otgsc = 0; 517 518 if (ci->in_lpm) { 519 /* 520 * If we already have a wakeup irq pending there, 521 * let's just return to wait resume finished firstly. 522 */ 523 if (ci->wakeup_int) 524 return IRQ_HANDLED; 525 526 disable_irq_nosync(irq); 527 ci->wakeup_int = true; 528 pm_runtime_get(ci->dev); 529 return IRQ_HANDLED; 530 } 531 532 if (ci->is_otg) { 533 otgsc = hw_read_otgsc(ci, ~0); 534 if (ci_otg_is_fsm_mode(ci)) { 535 ret = ci_otg_fsm_irq(ci); 536 if (ret == IRQ_HANDLED) 537 return ret; 538 } 539 } 540 541 /* 542 * Handle id change interrupt, it indicates device/host function 543 * switch. 544 */ 545 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 546 ci->id_event = true; 547 /* Clear ID change irq status */ 548 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 549 ci_otg_queue_work(ci); 550 return IRQ_HANDLED; 551 } 552 553 /* 554 * Handle vbus change interrupt, it indicates device connection 555 * and disconnection events. 556 */ 557 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 558 ci->b_sess_valid_event = true; 559 /* Clear BSV irq */ 560 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 561 ci_otg_queue_work(ci); 562 return IRQ_HANDLED; 563 } 564 565 /* Handle device/host interrupt */ 566 if (ci->role != CI_ROLE_END) 567 ret = ci_role(ci)->irq(ci); 568 569 return ret; 570} 571 572static void ci_irq(struct ci_hdrc *ci) 573{ 574 unsigned long flags; 575 576 local_irq_save(flags); 577 ci_irq_handler(ci->irq, ci); 578 local_irq_restore(flags); 579} 580 581static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, 582 void *ptr) 583{ 584 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); 585 struct ci_hdrc *ci = cbl->ci; 586 587 cbl->connected = event; 588 cbl->changed = true; 589 590 ci_irq(ci); 591 return NOTIFY_DONE; 592} 593 594static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw) 595{ 596 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 597 enum usb_role role; 598 unsigned long flags; 599 600 spin_lock_irqsave(&ci->lock, flags); 601 role = ci_role_to_usb_role(ci); 602 spin_unlock_irqrestore(&ci->lock, flags); 603 604 return role; 605} 606 607static int ci_usb_role_switch_set(struct usb_role_switch *sw, 608 enum usb_role role) 609{ 610 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 611 struct ci_hdrc_cable *cable = NULL; 612 enum usb_role current_role = ci_role_to_usb_role(ci); 613 enum ci_role ci_role = usb_role_to_ci_role(role); 614 unsigned long flags; 615 616 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) || 617 (current_role == role)) 618 return 0; 619 620 pm_runtime_get_sync(ci->dev); 621 /* Stop current role */ 622 spin_lock_irqsave(&ci->lock, flags); 623 if (current_role == USB_ROLE_DEVICE) 624 cable = &ci->platdata->vbus_extcon; 625 else if (current_role == USB_ROLE_HOST) 626 cable = &ci->platdata->id_extcon; 627 628 if (cable) { 629 cable->changed = true; 630 cable->connected = false; 631 ci_irq(ci); 632 spin_unlock_irqrestore(&ci->lock, flags); 633 if (ci->wq && role != USB_ROLE_NONE) 634 flush_workqueue(ci->wq); 635 spin_lock_irqsave(&ci->lock, flags); 636 } 637 638 cable = NULL; 639 640 /* Start target role */ 641 if (role == USB_ROLE_DEVICE) 642 cable = &ci->platdata->vbus_extcon; 643 else if (role == USB_ROLE_HOST) 644 cable = &ci->platdata->id_extcon; 645 646 if (cable) { 647 cable->changed = true; 648 cable->connected = true; 649 ci_irq(ci); 650 } 651 spin_unlock_irqrestore(&ci->lock, flags); 652 pm_runtime_put_sync(ci->dev); 653 654 return 0; 655} 656 657static struct usb_role_switch_desc ci_role_switch = { 658 .set = ci_usb_role_switch_set, 659 .get = ci_usb_role_switch_get, 660 .allow_userspace_control = true, 661}; 662 663static int ci_get_platdata(struct device *dev, 664 struct ci_hdrc_platform_data *platdata) 665{ 666 struct extcon_dev *ext_vbus, *ext_id; 667 struct ci_hdrc_cable *cable; 668 int ret; 669 670 if (!platdata->phy_mode) 671 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 672 673 if (!platdata->dr_mode) 674 platdata->dr_mode = usb_get_dr_mode(dev); 675 676 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 677 platdata->dr_mode = USB_DR_MODE_OTG; 678 679 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 680 /* Get the vbus regulator */ 681 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus"); 682 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 683 return -EPROBE_DEFER; 684 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 685 /* no vbus regulator is needed */ 686 platdata->reg_vbus = NULL; 687 } else if (IS_ERR(platdata->reg_vbus)) { 688 dev_err(dev, "Getting regulator error: %ld\n", 689 PTR_ERR(platdata->reg_vbus)); 690 return PTR_ERR(platdata->reg_vbus); 691 } 692 /* Get TPL support */ 693 if (!platdata->tpl_support) 694 platdata->tpl_support = 695 of_usb_host_tpl_support(dev->of_node); 696 } 697 698 if (platdata->dr_mode == USB_DR_MODE_OTG) { 699 /* We can support HNP and SRP of OTG 2.0 */ 700 platdata->ci_otg_caps.otg_rev = 0x0200; 701 platdata->ci_otg_caps.hnp_support = true; 702 platdata->ci_otg_caps.srp_support = true; 703 704 /* Update otg capabilities by DT properties */ 705 ret = of_usb_update_otg_caps(dev->of_node, 706 &platdata->ci_otg_caps); 707 if (ret) 708 return ret; 709 } 710 711 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 712 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 713 714 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 715 &platdata->phy_clkgate_delay_us); 716 717 platdata->itc_setting = 1; 718 719 of_property_read_u32(dev->of_node, "itc-setting", 720 &platdata->itc_setting); 721 722 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 723 &platdata->ahb_burst_config); 724 if (!ret) { 725 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 726 } else if (ret != -EINVAL) { 727 dev_err(dev, "failed to get ahb-burst-config\n"); 728 return ret; 729 } 730 731 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 732 &platdata->tx_burst_size); 733 if (!ret) { 734 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 735 } else if (ret != -EINVAL) { 736 dev_err(dev, "failed to get tx-burst-size-dword\n"); 737 return ret; 738 } 739 740 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 741 &platdata->rx_burst_size); 742 if (!ret) { 743 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 744 } else if (ret != -EINVAL) { 745 dev_err(dev, "failed to get rx-burst-size-dword\n"); 746 return ret; 747 } 748 749 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) 750 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; 751 752 ext_id = ERR_PTR(-ENODEV); 753 ext_vbus = ERR_PTR(-ENODEV); 754 if (of_property_read_bool(dev->of_node, "extcon")) { 755 /* Each one of them is not mandatory */ 756 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 757 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 758 return PTR_ERR(ext_vbus); 759 760 ext_id = extcon_get_edev_by_phandle(dev, 1); 761 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 762 return PTR_ERR(ext_id); 763 } 764 765 cable = &platdata->vbus_extcon; 766 cable->nb.notifier_call = ci_cable_notifier; 767 cable->edev = ext_vbus; 768 769 if (!IS_ERR(ext_vbus)) { 770 ret = extcon_get_state(cable->edev, EXTCON_USB); 771 if (ret) 772 cable->connected = true; 773 else 774 cable->connected = false; 775 } 776 777 cable = &platdata->id_extcon; 778 cable->nb.notifier_call = ci_cable_notifier; 779 cable->edev = ext_id; 780 781 if (!IS_ERR(ext_id)) { 782 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); 783 if (ret) 784 cable->connected = true; 785 else 786 cable->connected = false; 787 } 788 789 if (device_property_read_bool(dev, "usb-role-switch")) 790 ci_role_switch.fwnode = dev->fwnode; 791 792 platdata->pctl = devm_pinctrl_get(dev); 793 if (!IS_ERR(platdata->pctl)) { 794 struct pinctrl_state *p; 795 796 p = pinctrl_lookup_state(platdata->pctl, "default"); 797 if (!IS_ERR(p)) 798 platdata->pins_default = p; 799 800 p = pinctrl_lookup_state(platdata->pctl, "host"); 801 if (!IS_ERR(p)) 802 platdata->pins_host = p; 803 804 p = pinctrl_lookup_state(platdata->pctl, "device"); 805 if (!IS_ERR(p)) 806 platdata->pins_device = p; 807 } 808 809 return 0; 810} 811 812static int ci_extcon_register(struct ci_hdrc *ci) 813{ 814 struct ci_hdrc_cable *id, *vbus; 815 int ret; 816 817 id = &ci->platdata->id_extcon; 818 id->ci = ci; 819 if (!IS_ERR_OR_NULL(id->edev)) { 820 ret = devm_extcon_register_notifier(ci->dev, id->edev, 821 EXTCON_USB_HOST, &id->nb); 822 if (ret < 0) { 823 dev_err(ci->dev, "register ID failed\n"); 824 return ret; 825 } 826 } 827 828 vbus = &ci->platdata->vbus_extcon; 829 vbus->ci = ci; 830 if (!IS_ERR_OR_NULL(vbus->edev)) { 831 ret = devm_extcon_register_notifier(ci->dev, vbus->edev, 832 EXTCON_USB, &vbus->nb); 833 if (ret < 0) { 834 dev_err(ci->dev, "register VBUS failed\n"); 835 return ret; 836 } 837 } 838 839 return 0; 840} 841 842static DEFINE_IDA(ci_ida); 843 844struct platform_device *ci_hdrc_add_device(struct device *dev, 845 struct resource *res, int nres, 846 struct ci_hdrc_platform_data *platdata) 847{ 848 struct platform_device *pdev; 849 int id, ret; 850 851 ret = ci_get_platdata(dev, platdata); 852 if (ret) 853 return ERR_PTR(ret); 854 855 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 856 if (id < 0) 857 return ERR_PTR(id); 858 859 pdev = platform_device_alloc("ci_hdrc", id); 860 if (!pdev) { 861 ret = -ENOMEM; 862 goto put_id; 863 } 864 865 pdev->dev.parent = dev; 866 867 ret = platform_device_add_resources(pdev, res, nres); 868 if (ret) 869 goto err; 870 871 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 872 if (ret) 873 goto err; 874 875 ret = platform_device_add(pdev); 876 if (ret) 877 goto err; 878 879 return pdev; 880 881err: 882 platform_device_put(pdev); 883put_id: 884 ida_simple_remove(&ci_ida, id); 885 return ERR_PTR(ret); 886} 887EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 888 889void ci_hdrc_remove_device(struct platform_device *pdev) 890{ 891 int id = pdev->id; 892 platform_device_unregister(pdev); 893 ida_simple_remove(&ci_ida, id); 894} 895EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 896 897/** 898 * ci_hdrc_query_available_role: get runtime available operation mode 899 * 900 * The glue layer can get current operation mode (host/peripheral/otg) 901 * This function should be called after ci core device has created. 902 * 903 * @pdev: the platform device of ci core. 904 * 905 * Return runtime usb_dr_mode. 906 */ 907enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev) 908{ 909 struct ci_hdrc *ci = platform_get_drvdata(pdev); 910 911 if (!ci) 912 return USB_DR_MODE_UNKNOWN; 913 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) 914 return USB_DR_MODE_OTG; 915 else if (ci->roles[CI_ROLE_HOST]) 916 return USB_DR_MODE_HOST; 917 else if (ci->roles[CI_ROLE_GADGET]) 918 return USB_DR_MODE_PERIPHERAL; 919 else 920 return USB_DR_MODE_UNKNOWN; 921} 922EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role); 923 924static inline void ci_role_destroy(struct ci_hdrc *ci) 925{ 926 ci_hdrc_gadget_destroy(ci); 927 ci_hdrc_host_destroy(ci); 928 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 929 ci_hdrc_otg_destroy(ci); 930} 931 932static void ci_get_otg_capable(struct ci_hdrc *ci) 933{ 934 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 935 ci->is_otg = false; 936 else 937 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 938 DCCPARAMS_DC | DCCPARAMS_HC) 939 == (DCCPARAMS_DC | DCCPARAMS_HC)); 940 if (ci->is_otg) { 941 dev_dbg(ci->dev, "It is OTG capable controller\n"); 942 /* Disable and clear all OTG irq */ 943 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 944 OTGSC_INT_STATUS_BITS); 945 } 946} 947 948static ssize_t role_show(struct device *dev, struct device_attribute *attr, 949 char *buf) 950{ 951 struct ci_hdrc *ci = dev_get_drvdata(dev); 952 953 if (ci->role != CI_ROLE_END) 954 return sprintf(buf, "%s\n", ci_role(ci)->name); 955 956 return 0; 957} 958 959static ssize_t role_store(struct device *dev, 960 struct device_attribute *attr, const char *buf, size_t n) 961{ 962 struct ci_hdrc *ci = dev_get_drvdata(dev); 963 enum ci_role role; 964 int ret; 965 966 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { 967 dev_warn(dev, "Current configuration is not dual-role, quit\n"); 968 return -EPERM; 969 } 970 971 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 972 if (!strncmp(buf, ci->roles[role]->name, 973 strlen(ci->roles[role]->name))) 974 break; 975 976 if (role == CI_ROLE_END) 977 return -EINVAL; 978 979 mutex_lock(&ci->mutex); 980 981 if (role == ci->role) { 982 mutex_unlock(&ci->mutex); 983 return n; 984 } 985 986 pm_runtime_get_sync(dev); 987 disable_irq(ci->irq); 988 ci_role_stop(ci); 989 ret = ci_role_start(ci, role); 990 if (!ret && ci->role == CI_ROLE_GADGET) 991 ci_handle_vbus_change(ci); 992 enable_irq(ci->irq); 993 pm_runtime_put_sync(dev); 994 mutex_unlock(&ci->mutex); 995 996 return (ret == 0) ? n : ret; 997} 998static DEVICE_ATTR_RW(role); 999 1000static struct attribute *ci_attrs[] = { 1001 &dev_attr_role.attr, 1002 NULL, 1003}; 1004ATTRIBUTE_GROUPS(ci); 1005 1006static int ci_hdrc_probe(struct platform_device *pdev) 1007{ 1008 struct device *dev = &pdev->dev; 1009 struct ci_hdrc *ci; 1010 struct resource *res; 1011 void __iomem *base; 1012 int ret; 1013 enum usb_dr_mode dr_mode; 1014 1015 if (!dev_get_platdata(dev)) { 1016 dev_err(dev, "platform data missing\n"); 1017 return -ENODEV; 1018 } 1019 1020 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1021 base = devm_ioremap_resource(dev, res); 1022 if (IS_ERR(base)) 1023 return PTR_ERR(base); 1024 1025 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 1026 if (!ci) 1027 return -ENOMEM; 1028 1029 spin_lock_init(&ci->lock); 1030 mutex_init(&ci->mutex); 1031 ci->dev = dev; 1032 ci->platdata = dev_get_platdata(dev); 1033 ci->imx28_write_fix = !!(ci->platdata->flags & 1034 CI_HDRC_IMX28_WRITE_FIX); 1035 ci->supports_runtime_pm = !!(ci->platdata->flags & 1036 CI_HDRC_SUPPORTS_RUNTIME_PM); 1037 platform_set_drvdata(pdev, ci); 1038 1039 ret = hw_device_init(ci, base); 1040 if (ret < 0) { 1041 dev_err(dev, "can't initialize hardware\n"); 1042 return -ENODEV; 1043 } 1044 1045 ret = ci_ulpi_init(ci); 1046 if (ret) 1047 return ret; 1048 1049 if (ci->platdata->phy) { 1050 ci->phy = ci->platdata->phy; 1051 } else if (ci->platdata->usb_phy) { 1052 ci->usb_phy = ci->platdata->usb_phy; 1053 } else { 1054 /* Look for a generic PHY first */ 1055 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 1056 1057 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) { 1058 ret = -EPROBE_DEFER; 1059 goto ulpi_exit; 1060 } else if (IS_ERR(ci->phy)) { 1061 ci->phy = NULL; 1062 } 1063 1064 /* Look for a legacy USB PHY from device-tree next */ 1065 if (!ci->phy) { 1066 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, 1067 "phys", 0); 1068 1069 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1070 ret = -EPROBE_DEFER; 1071 goto ulpi_exit; 1072 } else if (IS_ERR(ci->usb_phy)) { 1073 ci->usb_phy = NULL; 1074 } 1075 } 1076 1077 /* Look for any registered legacy USB PHY as last resort */ 1078 if (!ci->phy && !ci->usb_phy) { 1079 ci->usb_phy = devm_usb_get_phy(dev->parent, 1080 USB_PHY_TYPE_USB2); 1081 1082 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1083 ret = -EPROBE_DEFER; 1084 goto ulpi_exit; 1085 } else if (IS_ERR(ci->usb_phy)) { 1086 ci->usb_phy = NULL; 1087 } 1088 } 1089 1090 /* No USB PHY was found in the end */ 1091 if (!ci->phy && !ci->usb_phy) { 1092 ret = -ENXIO; 1093 goto ulpi_exit; 1094 } 1095 } 1096 1097 ret = ci_usb_phy_init(ci); 1098 if (ret) { 1099 dev_err(dev, "unable to init phy: %d\n", ret); 1100 goto ulpi_exit; 1101 } 1102 1103 ci->hw_bank.phys = res->start; 1104 1105 ci->irq = platform_get_irq(pdev, 0); 1106 if (ci->irq < 0) { 1107 ret = ci->irq; 1108 goto deinit_phy; 1109 } 1110 1111 ci_get_otg_capable(ci); 1112 1113 dr_mode = ci->platdata->dr_mode; 1114 /* initialize role(s) before the interrupt is requested */ 1115 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 1116 ret = ci_hdrc_host_init(ci); 1117 if (ret) { 1118 if (ret == -ENXIO) 1119 dev_info(dev, "doesn't support host\n"); 1120 else 1121 goto deinit_phy; 1122 } 1123 } 1124 1125 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 1126 ret = ci_hdrc_gadget_init(ci); 1127 if (ret) { 1128 if (ret == -ENXIO) 1129 dev_info(dev, "doesn't support gadget\n"); 1130 else 1131 goto deinit_host; 1132 } 1133 } 1134 1135 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 1136 dev_err(dev, "no supported roles\n"); 1137 ret = -ENODEV; 1138 goto deinit_gadget; 1139 } 1140 1141 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 1142 ret = ci_hdrc_otg_init(ci); 1143 if (ret) { 1144 dev_err(dev, "init otg fails, ret = %d\n", ret); 1145 goto deinit_gadget; 1146 } 1147 } 1148 1149 if (ci_role_switch.fwnode) { 1150 ci_role_switch.driver_data = ci; 1151 ci->role_switch = usb_role_switch_register(dev, 1152 &ci_role_switch); 1153 if (IS_ERR(ci->role_switch)) { 1154 ret = PTR_ERR(ci->role_switch); 1155 goto deinit_otg; 1156 } 1157 } 1158 1159 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 1160 if (ci->is_otg) { 1161 ci->role = ci_otg_role(ci); 1162 /* Enable ID change irq */ 1163 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 1164 } else { 1165 /* 1166 * If the controller is not OTG capable, but support 1167 * role switch, the defalt role is gadget, and the 1168 * user can switch it through debugfs. 1169 */ 1170 ci->role = CI_ROLE_GADGET; 1171 } 1172 } else { 1173 ci->role = ci->roles[CI_ROLE_HOST] 1174 ? CI_ROLE_HOST 1175 : CI_ROLE_GADGET; 1176 } 1177 1178 if (!ci_otg_is_fsm_mode(ci)) { 1179 /* only update vbus status for peripheral */ 1180 if (ci->role == CI_ROLE_GADGET) { 1181 /* Pull down DP for possible charger detection */ 1182 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 1183 ci_handle_vbus_change(ci); 1184 } 1185 1186 ret = ci_role_start(ci, ci->role); 1187 if (ret) { 1188 dev_err(dev, "can't start %s role\n", 1189 ci_role(ci)->name); 1190 goto stop; 1191 } 1192 } 1193 1194 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED, 1195 ci->platdata->name, ci); 1196 if (ret) 1197 goto stop; 1198 1199 ret = ci_extcon_register(ci); 1200 if (ret) 1201 goto stop; 1202 1203 if (ci->supports_runtime_pm) { 1204 pm_runtime_set_active(&pdev->dev); 1205 pm_runtime_enable(&pdev->dev); 1206 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1207 pm_runtime_mark_last_busy(ci->dev); 1208 pm_runtime_use_autosuspend(&pdev->dev); 1209 } 1210 1211 if (ci_otg_is_fsm_mode(ci)) 1212 ci_hdrc_otg_fsm_start(ci); 1213 1214 device_set_wakeup_capable(&pdev->dev, true); 1215 dbg_create_files(ci); 1216 1217 return 0; 1218 1219stop: 1220 if (ci->role_switch) 1221 usb_role_switch_unregister(ci->role_switch); 1222deinit_otg: 1223 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 1224 ci_hdrc_otg_destroy(ci); 1225deinit_gadget: 1226 ci_hdrc_gadget_destroy(ci); 1227deinit_host: 1228 ci_hdrc_host_destroy(ci); 1229deinit_phy: 1230 ci_usb_phy_exit(ci); 1231ulpi_exit: 1232 ci_ulpi_exit(ci); 1233 1234 return ret; 1235} 1236 1237static int ci_hdrc_remove(struct platform_device *pdev) 1238{ 1239 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1240 1241 if (ci->role_switch) 1242 usb_role_switch_unregister(ci->role_switch); 1243 1244 if (ci->supports_runtime_pm) { 1245 pm_runtime_get_sync(&pdev->dev); 1246 pm_runtime_disable(&pdev->dev); 1247 pm_runtime_put_noidle(&pdev->dev); 1248 } 1249 1250 dbg_remove_files(ci); 1251 ci_role_destroy(ci); 1252 ci_hdrc_enter_lpm(ci, true); 1253 ci_usb_phy_exit(ci); 1254 ci_ulpi_exit(ci); 1255 1256 return 0; 1257} 1258 1259#ifdef CONFIG_PM 1260/* Prepare wakeup by SRP before suspend */ 1261static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1262{ 1263 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1264 !hw_read_otgsc(ci, OTGSC_ID)) { 1265 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1266 PORTSC_PP); 1267 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1268 PORTSC_WKCN); 1269 } 1270} 1271 1272/* Handle SRP when wakeup by data pulse */ 1273static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1274{ 1275 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1276 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1277 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1278 ci->fsm.a_srp_det = 1; 1279 ci->fsm.a_bus_drop = 0; 1280 } else { 1281 ci->fsm.id = 1; 1282 } 1283 ci_otg_queue_work(ci); 1284 } 1285} 1286 1287static void ci_controller_suspend(struct ci_hdrc *ci) 1288{ 1289 disable_irq(ci->irq); 1290 ci_hdrc_enter_lpm(ci, true); 1291 if (ci->platdata->phy_clkgate_delay_us) 1292 usleep_range(ci->platdata->phy_clkgate_delay_us, 1293 ci->platdata->phy_clkgate_delay_us + 50); 1294 usb_phy_set_suspend(ci->usb_phy, 1); 1295 ci->in_lpm = true; 1296 enable_irq(ci->irq); 1297} 1298 1299/* 1300 * Handle the wakeup interrupt triggered by extcon connector 1301 * We need to call ci_irq again for extcon since the first 1302 * interrupt (wakeup int) only let the controller be out of 1303 * low power mode, but not handle any interrupts. 1304 */ 1305static void ci_extcon_wakeup_int(struct ci_hdrc *ci) 1306{ 1307 struct ci_hdrc_cable *cable_id, *cable_vbus; 1308 u32 otgsc = hw_read_otgsc(ci, ~0); 1309 1310 cable_id = &ci->platdata->id_extcon; 1311 cable_vbus = &ci->platdata->vbus_extcon; 1312 1313 if (!IS_ERR(cable_id->edev) && ci->is_otg && 1314 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) 1315 ci_irq(ci); 1316 1317 if (!IS_ERR(cable_vbus->edev) && ci->is_otg && 1318 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) 1319 ci_irq(ci); 1320} 1321 1322static int ci_controller_resume(struct device *dev) 1323{ 1324 struct ci_hdrc *ci = dev_get_drvdata(dev); 1325 int ret; 1326 1327 dev_dbg(dev, "at %s\n", __func__); 1328 1329 if (!ci->in_lpm) { 1330 WARN_ON(1); 1331 return 0; 1332 } 1333 1334 ci_hdrc_enter_lpm(ci, false); 1335 1336 ret = ci_ulpi_resume(ci); 1337 if (ret) 1338 return ret; 1339 1340 if (ci->usb_phy) { 1341 usb_phy_set_suspend(ci->usb_phy, 0); 1342 usb_phy_set_wakeup(ci->usb_phy, false); 1343 hw_wait_phy_stable(); 1344 } 1345 1346 ci->in_lpm = false; 1347 if (ci->wakeup_int) { 1348 ci->wakeup_int = false; 1349 pm_runtime_mark_last_busy(ci->dev); 1350 pm_runtime_put_autosuspend(ci->dev); 1351 enable_irq(ci->irq); 1352 if (ci_otg_is_fsm_mode(ci)) 1353 ci_otg_fsm_wakeup_by_srp(ci); 1354 ci_extcon_wakeup_int(ci); 1355 } 1356 1357 return 0; 1358} 1359 1360#ifdef CONFIG_PM_SLEEP 1361static int ci_suspend(struct device *dev) 1362{ 1363 struct ci_hdrc *ci = dev_get_drvdata(dev); 1364 1365 if (ci->wq) 1366 flush_workqueue(ci->wq); 1367 /* 1368 * Controller needs to be active during suspend, otherwise the core 1369 * may run resume when the parent is at suspend if other driver's 1370 * suspend fails, it occurs before parent's suspend has not started, 1371 * but the core suspend has finished. 1372 */ 1373 if (ci->in_lpm) 1374 pm_runtime_resume(dev); 1375 1376 if (ci->in_lpm) { 1377 WARN_ON(1); 1378 return 0; 1379 } 1380 1381 if (device_may_wakeup(dev)) { 1382 if (ci_otg_is_fsm_mode(ci)) 1383 ci_otg_fsm_suspend_for_srp(ci); 1384 1385 usb_phy_set_wakeup(ci->usb_phy, true); 1386 enable_irq_wake(ci->irq); 1387 } 1388 1389 ci_controller_suspend(ci); 1390 1391 return 0; 1392} 1393 1394static int ci_resume(struct device *dev) 1395{ 1396 struct ci_hdrc *ci = dev_get_drvdata(dev); 1397 int ret; 1398 1399 if (device_may_wakeup(dev)) 1400 disable_irq_wake(ci->irq); 1401 1402 ret = ci_controller_resume(dev); 1403 if (ret) 1404 return ret; 1405 1406 if (ci->supports_runtime_pm) { 1407 pm_runtime_disable(dev); 1408 pm_runtime_set_active(dev); 1409 pm_runtime_enable(dev); 1410 } 1411 1412 return ret; 1413} 1414#endif /* CONFIG_PM_SLEEP */ 1415 1416static int ci_runtime_suspend(struct device *dev) 1417{ 1418 struct ci_hdrc *ci = dev_get_drvdata(dev); 1419 1420 dev_dbg(dev, "at %s\n", __func__); 1421 1422 if (ci->in_lpm) { 1423 WARN_ON(1); 1424 return 0; 1425 } 1426 1427 if (ci_otg_is_fsm_mode(ci)) 1428 ci_otg_fsm_suspend_for_srp(ci); 1429 1430 usb_phy_set_wakeup(ci->usb_phy, true); 1431 ci_controller_suspend(ci); 1432 1433 return 0; 1434} 1435 1436static int ci_runtime_resume(struct device *dev) 1437{ 1438 return ci_controller_resume(dev); 1439} 1440 1441#endif /* CONFIG_PM */ 1442static const struct dev_pm_ops ci_pm_ops = { 1443 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1444 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1445}; 1446 1447static struct platform_driver ci_hdrc_driver = { 1448 .probe = ci_hdrc_probe, 1449 .remove = ci_hdrc_remove, 1450 .driver = { 1451 .name = "ci_hdrc", 1452 .pm = &ci_pm_ops, 1453 .dev_groups = ci_groups, 1454 }, 1455}; 1456 1457static int __init ci_hdrc_platform_register(void) 1458{ 1459 ci_hdrc_host_driver_init(); 1460 return platform_driver_register(&ci_hdrc_driver); 1461} 1462module_init(ci_hdrc_platform_register); 1463 1464static void __exit ci_hdrc_platform_unregister(void) 1465{ 1466 platform_driver_unregister(&ci_hdrc_driver); 1467} 1468module_exit(ci_hdrc_platform_unregister); 1469 1470MODULE_ALIAS("platform:ci_hdrc"); 1471MODULE_LICENSE("GPL v2"); 1472MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1473MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1474