1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * ci.h - common structures, functions, and macros of the ChipIdea driver
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 *
7 * Author: David Lopo
8 */
9
10#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
11#define __DRIVERS_USB_CHIPIDEA_CI_H
12
13#include <linux/list.h>
14#include <linux/irqreturn.h>
15#include <linux/usb.h>
16#include <linux/usb/gadget.h>
17#include <linux/usb/otg-fsm.h>
18#include <linux/usb/otg.h>
19#include <linux/usb/role.h>
20#include <linux/ulpi/interface.h>
21
22/******************************************************************************
23 * DEFINE
24 *****************************************************************************/
25#define TD_PAGE_COUNT      5
26#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
27#define ENDPT_MAX          32
28#define CI_MAX_BUF_SIZE	(TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
29
30/******************************************************************************
31 * REGISTERS
32 *****************************************************************************/
33/* Identification Registers */
34#define ID_ID				0x0
35#define ID_HWGENERAL			0x4
36#define ID_HWHOST			0x8
37#define ID_HWDEVICE			0xc
38#define ID_HWTXBUF			0x10
39#define ID_HWRXBUF			0x14
40#define ID_SBUSCFG			0x90
41
42/* register indices */
43enum ci_hw_regs {
44	CAP_CAPLENGTH,
45	CAP_HCCPARAMS,
46	CAP_DCCPARAMS,
47	CAP_TESTMODE,
48	CAP_LAST = CAP_TESTMODE,
49	OP_USBCMD,
50	OP_USBSTS,
51	OP_USBINTR,
52	OP_DEVICEADDR,
53	OP_ENDPTLISTADDR,
54	OP_TTCTRL,
55	OP_BURSTSIZE,
56	OP_ULPI_VIEWPORT,
57	OP_PORTSC,
58	OP_DEVLC,
59	OP_OTGSC,
60	OP_USBMODE,
61	OP_ENDPTSETUPSTAT,
62	OP_ENDPTPRIME,
63	OP_ENDPTFLUSH,
64	OP_ENDPTSTAT,
65	OP_ENDPTCOMPLETE,
66	OP_ENDPTCTRL,
67	/* endptctrl1..15 follow */
68	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
69};
70
71/******************************************************************************
72 * STRUCTURES
73 *****************************************************************************/
74/**
75 * struct ci_hw_ep - endpoint representation
76 * @ep: endpoint structure for gadget drivers
77 * @dir: endpoint direction (TX/RX)
78 * @num: endpoint number
79 * @type: endpoint type
80 * @name: string description of the endpoint
81 * @qh: queue head for this endpoint
82 * @wedge: is the endpoint wedged
83 * @ci: pointer to the controller
84 * @lock: pointer to controller's spinlock
85 * @td_pool: pointer to controller's TD pool
86 */
87struct ci_hw_ep {
88	struct usb_ep				ep;
89	u8					dir;
90	u8					num;
91	u8					type;
92	char					name[16];
93	struct {
94		struct list_head	queue;
95		struct ci_hw_qh		*ptr;
96		dma_addr_t		dma;
97	}					qh;
98	int					wedge;
99
100	/* global resources */
101	struct ci_hdrc				*ci;
102	spinlock_t				*lock;
103	struct dma_pool				*td_pool;
104	struct td_node				*pending_td;
105};
106
107enum ci_role {
108	CI_ROLE_HOST = 0,
109	CI_ROLE_GADGET,
110	CI_ROLE_END,
111};
112
113enum ci_revision {
114	CI_REVISION_1X = 10,	/* Revision 1.x */
115	CI_REVISION_20 = 20, /* Revision 2.0 */
116	CI_REVISION_21, /* Revision 2.1 */
117	CI_REVISION_22, /* Revision 2.2 */
118	CI_REVISION_23, /* Revision 2.3 */
119	CI_REVISION_24, /* Revision 2.4 */
120	CI_REVISION_25, /* Revision 2.5 */
121	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
122	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
123};
124
125/**
126 * struct ci_role_driver - host/gadget role driver
127 * @start: start this role
128 * @stop: stop this role
129 * @irq: irq handler for this role
130 * @name: role name string (host/gadget)
131 */
132struct ci_role_driver {
133	int		(*start)(struct ci_hdrc *);
134	void		(*stop)(struct ci_hdrc *);
135	irqreturn_t	(*irq)(struct ci_hdrc *);
136	const char	*name;
137};
138
139/**
140 * struct hw_bank - hardware register mapping representation
141 * @lpm: set if the device is LPM capable
142 * @phys: physical address of the controller's registers
143 * @abs: absolute address of the beginning of register window
144 * @cap: capability registers
145 * @op: operational registers
146 * @size: size of the register window
147 * @regmap: register lookup table
148 */
149struct hw_bank {
150	unsigned	lpm;
151	resource_size_t	phys;
152	void __iomem	*abs;
153	void __iomem	*cap;
154	void __iomem	*op;
155	size_t		size;
156	void __iomem	*regmap[OP_LAST + 1];
157};
158
159/**
160 * struct ci_hdrc - chipidea device representation
161 * @dev: pointer to parent device
162 * @lock: access synchronization
163 * @hw_bank: hardware register mapping
164 * @irq: IRQ number
165 * @roles: array of supported roles for this controller
166 * @role: current role
167 * @is_otg: if the device is otg-capable
168 * @fsm: otg finite state machine
169 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
170 * @hr_timeouts: time out list for active otg fsm timers
171 * @enabled_otg_timer_bits: bits of enabled otg timers
172 * @next_otg_timer: next nearest enabled timer to be expired
173 * @work: work for role changing
174 * @wq: workqueue thread
175 * @qh_pool: allocation pool for queue heads
176 * @td_pool: allocation pool for transfer descriptors
177 * @gadget: device side representation for peripheral controller
178 * @driver: gadget driver
179 * @resume_state: save the state of gadget suspend from
180 * @hw_ep_max: total number of endpoints supported by hardware
181 * @ci_hw_ep: array of endpoints
182 * @ep0_dir: ep0 direction
183 * @ep0out: pointer to ep0 OUT endpoint
184 * @ep0in: pointer to ep0 IN endpoint
185 * @status: ep0 status request
186 * @setaddr: if we should set the address on status completion
187 * @address: usb address received from the host
188 * @remote_wakeup: host-enabled remote wakeup
189 * @suspended: suspended by host
190 * @test_mode: the selected test mode
191 * @platdata: platform specific information supplied by parent device
192 * @vbus_active: is VBUS active
193 * @ulpi: pointer to ULPI device, if any
194 * @ulpi_ops: ULPI read/write ops for this device
195 * @phy: pointer to PHY, if any
196 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
197 * @hcd: pointer to usb_hcd for ehci host driver
198 * @debugfs: root dentry for this controller in debugfs
199 * @id_event: indicates there is an id event, and handled at ci_otg_work
200 * @b_sess_valid_event: indicates there is a vbus event, and handled
201 * at ci_otg_work
202 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
203 * @supports_runtime_pm: if runtime pm is supported
204 * @in_lpm: if the core in low power mode
205 * @wakeup_int: if wakeup interrupt occur
206 * @rev: The revision number for controller
207 * @mutex: protect code from concorrent running when doing role switch
208 */
209struct ci_hdrc {
210	struct device			*dev;
211	spinlock_t			lock;
212	struct hw_bank			hw_bank;
213	int				irq;
214	struct ci_role_driver		*roles[CI_ROLE_END];
215	enum ci_role			role;
216	bool				is_otg;
217	struct usb_otg			otg;
218	struct otg_fsm			fsm;
219	struct hrtimer			otg_fsm_hrtimer;
220	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
221	unsigned			enabled_otg_timer_bits;
222	enum otg_fsm_timer		next_otg_timer;
223	struct usb_role_switch		*role_switch;
224	struct work_struct		work;
225	struct workqueue_struct		*wq;
226
227	struct dma_pool			*qh_pool;
228	struct dma_pool			*td_pool;
229
230	struct usb_gadget		gadget;
231	struct usb_gadget_driver	*driver;
232	enum usb_device_state		resume_state;
233	unsigned			hw_ep_max;
234	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
235	u32				ep0_dir;
236	struct ci_hw_ep			*ep0out, *ep0in;
237
238	struct usb_request		*status;
239	bool				setaddr;
240	u8				address;
241	u8				remote_wakeup;
242	u8				suspended;
243	u8				test_mode;
244
245	struct ci_hdrc_platform_data	*platdata;
246	int				vbus_active;
247	struct ulpi			*ulpi;
248	struct ulpi_ops 		ulpi_ops;
249	struct phy			*phy;
250	/* old usb_phy interface */
251	struct usb_phy			*usb_phy;
252	struct usb_hcd			*hcd;
253	struct dentry			*debugfs;
254	bool				id_event;
255	bool				b_sess_valid_event;
256	bool				imx28_write_fix;
257	bool				supports_runtime_pm;
258	bool				in_lpm;
259	bool				wakeup_int;
260	enum ci_revision		rev;
261	struct mutex                    mutex;
262};
263
264static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
265{
266	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
267	return ci->roles[ci->role];
268}
269
270static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
271{
272	int ret;
273
274	if (role >= CI_ROLE_END)
275		return -EINVAL;
276
277	if (!ci->roles[role])
278		return -ENXIO;
279
280	ret = ci->roles[role]->start(ci);
281	if (!ret)
282		ci->role = role;
283	return ret;
284}
285
286static inline void ci_role_stop(struct ci_hdrc *ci)
287{
288	enum ci_role role = ci->role;
289
290	if (role == CI_ROLE_END)
291		return;
292
293	ci->role = CI_ROLE_END;
294
295	ci->roles[role]->stop(ci);
296}
297
298static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
299{
300	if (ci->role == CI_ROLE_HOST)
301		return USB_ROLE_HOST;
302	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
303		return USB_ROLE_DEVICE;
304	else
305		return USB_ROLE_NONE;
306}
307
308static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
309{
310	if (role == USB_ROLE_HOST)
311		return CI_ROLE_HOST;
312	else if (role == USB_ROLE_DEVICE)
313		return CI_ROLE_GADGET;
314	else
315		return CI_ROLE_END;
316}
317
318/**
319 * hw_read_id_reg: reads from a identification register
320 * @ci: the controller
321 * @offset: offset from the beginning of identification registers region
322 * @mask: bitfield mask
323 *
324 * This function returns register contents
325 */
326static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
327{
328	return ioread32(ci->hw_bank.abs + offset) & mask;
329}
330
331/**
332 * hw_write_id_reg: writes to a identification register
333 * @ci: the controller
334 * @offset: offset from the beginning of identification registers region
335 * @mask: bitfield mask
336 * @data: new value
337 */
338static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
339			    u32 mask, u32 data)
340{
341	if (~mask)
342		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
343			| (data & mask);
344
345	iowrite32(data, ci->hw_bank.abs + offset);
346}
347
348/**
349 * hw_read: reads from a hw register
350 * @ci: the controller
351 * @reg:  register index
352 * @mask: bitfield mask
353 *
354 * This function returns register contents
355 */
356static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
357{
358	return ioread32(ci->hw_bank.regmap[reg]) & mask;
359}
360
361#ifdef CONFIG_SOC_IMX28
362static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
363{
364	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
365}
366#else
367static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
368{
369}
370#endif
371
372static inline void __hw_write(struct ci_hdrc *ci, u32 val,
373		void __iomem *addr)
374{
375	if (ci->imx28_write_fix)
376		imx28_ci_writel(val, addr);
377	else
378		iowrite32(val, addr);
379}
380
381/**
382 * hw_write: writes to a hw register
383 * @ci: the controller
384 * @reg:  register index
385 * @mask: bitfield mask
386 * @data: new value
387 */
388static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
389			    u32 mask, u32 data)
390{
391	if (~mask)
392		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
393			| (data & mask);
394
395	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
396}
397
398/**
399 * hw_test_and_clear: tests & clears a hw register
400 * @ci: the controller
401 * @reg:  register index
402 * @mask: bitfield mask
403 *
404 * This function returns register contents
405 */
406static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
407				    u32 mask)
408{
409	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
410
411	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
412	return val;
413}
414
415/**
416 * hw_test_and_write: tests & writes a hw register
417 * @ci: the controller
418 * @reg:  register index
419 * @mask: bitfield mask
420 * @data: new value
421 *
422 * This function returns register contents
423 */
424static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
425				    u32 mask, u32 data)
426{
427	u32 val = hw_read(ci, reg, ~0);
428
429	hw_write(ci, reg, mask, data);
430	return (val & mask) >> __ffs(mask);
431}
432
433/**
434 * ci_otg_is_fsm_mode: runtime check if otg controller
435 * is in otg fsm mode.
436 *
437 * @ci: chipidea device
438 */
439static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
440{
441#ifdef CONFIG_USB_OTG_FSM
442	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
443
444	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
445		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
446		otg_caps->hnp_support || otg_caps->adp_support);
447#else
448	return false;
449#endif
450}
451
452int ci_ulpi_init(struct ci_hdrc *ci);
453void ci_ulpi_exit(struct ci_hdrc *ci);
454int ci_ulpi_resume(struct ci_hdrc *ci);
455
456u32 hw_read_intr_enable(struct ci_hdrc *ci);
457
458u32 hw_read_intr_status(struct ci_hdrc *ci);
459
460int hw_device_reset(struct ci_hdrc *ci);
461
462int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
463
464u8 hw_port_test_get(struct ci_hdrc *ci);
465
466void hw_phymode_configure(struct ci_hdrc *ci);
467
468void ci_platform_configure(struct ci_hdrc *ci);
469
470void dbg_create_files(struct ci_hdrc *ci);
471
472void dbg_remove_files(struct ci_hdrc *ci);
473#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
474