1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * USBSS device controller driver header file 4 * 5 * Copyright (C) 2018-2019 Cadence. 6 * Copyright (C) 2017-2018 NXP 7 * 8 * Author: Pawel Laszczak <pawell@cadence.com> 9 * Pawel Jez <pjez@cadence.com> 10 * Peter Chen <peter.chen@nxp.com> 11 */ 12#ifndef __LINUX_CDNS3_GADGET 13#define __LINUX_CDNS3_GADGET 14#include <linux/usb/gadget.h> 15 16/* 17 * USBSS-DEV register interface. 18 * This corresponds to the USBSS Device Controller Interface 19 */ 20 21/** 22 * struct cdns3_usb_regs - device controller registers. 23 * @usb_conf: Global Configuration. 24 * @usb_sts: Global Status. 25 * @usb_cmd: Global Command. 26 * @usb_itpn: ITP/SOF number. 27 * @usb_lpm: Global Command. 28 * @usb_ien: USB Interrupt Enable. 29 * @usb_ists: USB Interrupt Status. 30 * @ep_sel: Endpoint Select. 31 * @ep_traddr: Endpoint Transfer Ring Address. 32 * @ep_cfg: Endpoint Configuration. 33 * @ep_cmd: Endpoint Command. 34 * @ep_sts: Endpoint Status. 35 * @ep_sts_sid: Endpoint Status. 36 * @ep_sts_en: Endpoint Status Enable. 37 * @drbl: Doorbell. 38 * @ep_ien: EP Interrupt Enable. 39 * @ep_ists: EP Interrupt Status. 40 * @usb_pwr: Global Power Configuration. 41 * @usb_conf2: Global Configuration 2. 42 * @usb_cap1: Capability 1. 43 * @usb_cap2: Capability 2. 44 * @usb_cap3: Capability 3. 45 * @usb_cap4: Capability 4. 46 * @usb_cap5: Capability 5. 47 * @usb_cap6: Capability 6. 48 * @usb_cpkt1: Custom Packet 1. 49 * @usb_cpkt2: Custom Packet 2. 50 * @usb_cpkt3: Custom Packet 3. 51 * @ep_dma_ext_addr: Upper address for DMA operations. 52 * @buf_addr: Address for On-chip Buffer operations. 53 * @buf_data: Data for On-chip Buffer operations. 54 * @buf_ctrl: On-chip Buffer Access Control. 55 * @dtrans: DMA Transfer Mode. 56 * @tdl_from_trb: Source of TD Configuration. 57 * @tdl_beh: TDL Behavior Configuration. 58 * @ep_tdl: Endpoint TDL. 59 * @tdl_beh2: TDL Behavior 2 Configuration. 60 * @dma_adv_td: DMA Advance TD Configuration. 61 * @reserved1: Reserved. 62 * @cfg_regs: Configuration. 63 * @reserved2: Reserved. 64 * @dma_axi_ctrl: AXI Control. 65 * @dma_axi_id: AXI ID register. 66 * @dma_axi_cap: AXI Capability. 67 * @dma_axi_ctrl0: AXI Control 0. 68 * @dma_axi_ctrl1: AXI Control 1. 69 */ 70struct cdns3_usb_regs { 71 __le32 usb_conf; 72 __le32 usb_sts; 73 __le32 usb_cmd; 74 __le32 usb_itpn; 75 __le32 usb_lpm; 76 __le32 usb_ien; 77 __le32 usb_ists; 78 __le32 ep_sel; 79 __le32 ep_traddr; 80 __le32 ep_cfg; 81 __le32 ep_cmd; 82 __le32 ep_sts; 83 __le32 ep_sts_sid; 84 __le32 ep_sts_en; 85 __le32 drbl; 86 __le32 ep_ien; 87 __le32 ep_ists; 88 __le32 usb_pwr; 89 __le32 usb_conf2; 90 __le32 usb_cap1; 91 __le32 usb_cap2; 92 __le32 usb_cap3; 93 __le32 usb_cap4; 94 __le32 usb_cap5; 95 __le32 usb_cap6; 96 __le32 usb_cpkt1; 97 __le32 usb_cpkt2; 98 __le32 usb_cpkt3; 99 __le32 ep_dma_ext_addr; 100 __le32 buf_addr; 101 __le32 buf_data; 102 __le32 buf_ctrl; 103 __le32 dtrans; 104 __le32 tdl_from_trb; 105 __le32 tdl_beh; 106 __le32 ep_tdl; 107 __le32 tdl_beh2; 108 __le32 dma_adv_td; 109 __le32 reserved1[26]; 110 __le32 cfg_reg1; 111 __le32 dbg_link1; 112 __le32 dbg_link2; 113 __le32 cfg_regs[74]; 114 __le32 reserved2[51]; 115 __le32 dma_axi_ctrl; 116 __le32 dma_axi_id; 117 __le32 dma_axi_cap; 118 __le32 dma_axi_ctrl0; 119 __le32 dma_axi_ctrl1; 120}; 121 122/* USB_CONF - bitmasks */ 123/* Reset USB device configuration. */ 124#define USB_CONF_CFGRST BIT(0) 125/* Set Configuration. */ 126#define USB_CONF_CFGSET BIT(1) 127/* Disconnect USB device in SuperSpeed. */ 128#define USB_CONF_USB3DIS BIT(3) 129/* Disconnect USB device in HS/FS */ 130#define USB_CONF_USB2DIS BIT(4) 131/* Little Endian access - default */ 132#define USB_CONF_LENDIAN BIT(5) 133/* 134 * Big Endian access. Driver assume that byte order for 135 * SFRs access always is as Little Endian so this bit 136 * is not used. 137 */ 138#define USB_CONF_BENDIAN BIT(6) 139/* Device software reset. */ 140#define USB_CONF_SWRST BIT(7) 141/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/ 142#define USB_CONF_DSING BIT(8) 143/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */ 144#define USB_CONF_DMULT BIT(9) 145/* DMA clock turn-off enable. */ 146#define USB_CONF_DMAOFFEN BIT(10) 147/* DMA clock turn-off disable. */ 148#define USB_CONF_DMAOFFDS BIT(11) 149/* Clear Force Full Speed. */ 150#define USB_CONF_CFORCE_FS BIT(12) 151/* Set Force Full Speed. */ 152#define USB_CONF_SFORCE_FS BIT(13) 153/* Device enable. */ 154#define USB_CONF_DEVEN BIT(14) 155/* Device disable. */ 156#define USB_CONF_DEVDS BIT(15) 157/* L1 LPM state entry enable (used in HS/FS mode). */ 158#define USB_CONF_L1EN BIT(16) 159/* L1 LPM state entry disable (used in HS/FS mode). */ 160#define USB_CONF_L1DS BIT(17) 161/* USB 2.0 clock gate disable. */ 162#define USB_CONF_CLK2OFFEN BIT(18) 163/* USB 2.0 clock gate enable. */ 164#define USB_CONF_CLK2OFFDS BIT(19) 165/* L0 LPM state entry request (used in HS/FS mode). */ 166#define USB_CONF_LGO_L0 BIT(20) 167/* USB 3.0 clock gate disable. */ 168#define USB_CONF_CLK3OFFEN BIT(21) 169/* USB 3.0 clock gate enable. */ 170#define USB_CONF_CLK3OFFDS BIT(22) 171/* Bit 23 is reserved*/ 172/* U1 state entry enable (used in SS mode). */ 173#define USB_CONF_U1EN BIT(24) 174/* U1 state entry disable (used in SS mode). */ 175#define USB_CONF_U1DS BIT(25) 176/* U2 state entry enable (used in SS mode). */ 177#define USB_CONF_U2EN BIT(26) 178/* U2 state entry disable (used in SS mode). */ 179#define USB_CONF_U2DS BIT(27) 180/* U0 state entry request (used in SS mode). */ 181#define USB_CONF_LGO_U0 BIT(28) 182/* U1 state entry request (used in SS mode). */ 183#define USB_CONF_LGO_U1 BIT(29) 184/* U2 state entry request (used in SS mode). */ 185#define USB_CONF_LGO_U2 BIT(30) 186/* SS.Inactive state entry request (used in SS mode) */ 187#define USB_CONF_LGO_SSINACT BIT(31) 188 189/* USB_STS - bitmasks */ 190/* 191 * Configuration status. 192 * 1 - device is in the configured state. 193 * 0 - device is not configured. 194 */ 195#define USB_STS_CFGSTS_MASK BIT(0) 196#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) 197/* 198 * On-chip memory overflow. 199 * 0 - On-chip memory status OK. 200 * 1 - On-chip memory overflow. 201 */ 202#define USB_STS_OV_MASK BIT(1) 203#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) 204/* 205 * SuperSpeed connection status. 206 * 0 - USB in SuperSpeed mode disconnected. 207 * 1 - USB in SuperSpeed mode connected. 208 */ 209#define USB_STS_USB3CONS_MASK BIT(2) 210#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) 211/* 212 * DMA transfer configuration status. 213 * 0 - single request. 214 * 1 - multiple TRB chain 215 * Supported only for controller version < DEV_VER_V3 216 */ 217#define USB_STS_DTRANS_MASK BIT(3) 218#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) 219/* 220 * Device speed. 221 * 0 - Undefined (value after reset). 222 * 1 - Low speed 223 * 2 - Full speed 224 * 3 - High speed 225 * 4 - Super speed 226 */ 227#define USB_STS_USBSPEED_MASK GENMASK(6, 4) 228#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) 229#define USB_STS_LS (0x1 << 4) 230#define USB_STS_FS (0x2 << 4) 231#define USB_STS_HS (0x3 << 4) 232#define USB_STS_SS (0x4 << 4) 233#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) 234#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) 235#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) 236#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) 237#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) 238/* 239 * Endianness for SFR access. 240 * 0 - Little Endian order (default after hardware reset). 241 * 1 - Big Endian order 242 */ 243#define USB_STS_ENDIAN_MASK BIT(7) 244#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) 245/* 246 * HS/FS clock turn-off status. 247 * 0 - hsfs clock is always on. 248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled 249 * (default after hardware reset). 250 */ 251#define USB_STS_CLK2OFF_MASK BIT(8) 252#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) 253/* 254 * PCLK clock turn-off status. 255 * 0 - pclk clock is always on. 256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled 257 * (default after hardware reset). 258 */ 259#define USB_STS_CLK3OFF_MASK BIT(9) 260#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) 261/* 262 * Controller in reset state. 263 * 0 - Internal reset is active. 264 * 1 - Internal reset is not active and controller is fully operational. 265 */ 266#define USB_STS_IN_RST_MASK BIT(10) 267#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) 268/* 269 * Status of the "TDL calculation basing on TRB" feature. 270 * 0 - disabled 271 * 1 - enabled 272 * Supported only for DEV_VER_V2 controller version. 273 */ 274#define USB_STS_TDL_TRB_ENABLED BIT(11) 275/* 276 * Device enable Status. 277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic). 278 * 1 - USB device is enabled (VBUS input is connected to the internal logic). 279 */ 280#define USB_STS_DEVS_MASK BIT(14) 281#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) 282/* 283 * Address status. 284 * 0 - USB device is default state. 285 * 1 - USB device is at least in address state. 286 */ 287#define USB_STS_ADDRESSED_MASK BIT(15) 288#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) 289/* 290 * L1 LPM state enable status (used in HS/FS mode). 291 * 0 - Entering to L1 LPM state disabled. 292 * 1 - Entering to L1 LPM state enabled. 293 */ 294#define USB_STS_L1ENS_MASK BIT(16) 295#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) 296/* 297 * Internal VBUS connection status (used both in HS/FS and SS mode). 298 * 0 - internal VBUS is not detected. 299 * 1 - internal VBUS is detected. 300 */ 301#define USB_STS_VBUSS_MASK BIT(17) 302#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) 303/* 304 * HS/FS LPM state (used in FS/HS mode). 305 * 0 - L0 State 306 * 1 - L1 State 307 * 2 - L2 State 308 * 3 - L3 State 309 */ 310#define USB_STS_LPMST_MASK GENMASK(19, 18) 311#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) 312#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) 313#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) 314#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) 315/* 316 * Disable HS status (used in FS/HS mode). 317 * 0 - the disconnect bit for HS/FS mode is set . 318 * 1 - the disconnect bit for HS/FS mode is not set. 319 */ 320#define USB_STS_USB2CONS_MASK BIT(20) 321#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) 322/* 323 * HS/FS mode connection status (used in FS/HS mode). 324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled. 325 * 1 - High Speed operations in USB2.0 (FS/HS). 326 */ 327#define USB_STS_DISABLE_HS_MASK BIT(21) 328#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) 329/* 330 * U1 state enable status (used in SS mode). 331 * 0 - Entering to U1 state disabled. 332 * 1 - Entering to U1 state enabled. 333 */ 334#define USB_STS_U1ENS_MASK BIT(24) 335#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) 336/* 337 * U2 state enable status (used in SS mode). 338 * 0 - Entering to U2 state disabled. 339 * 1 - Entering to U2 state enabled. 340 */ 341#define USB_STS_U2ENS_MASK BIT(25) 342#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) 343/* 344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current 345 * SuperSpeed link state 346 */ 347#define USB_STS_LST_MASK GENMASK(29, 26) 348#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26)) 349#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26)) 350#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26)) 351#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26)) 352#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26)) 353#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26)) 354#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26)) 355#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26)) 356#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26)) 357#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26)) 358#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26)) 359#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26)) 360/* 361 * DMA clock turn-off status. 362 * 0 - DMA clock is always on (default after hardware reset). 363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled. 364 */ 365#define USB_STS_DMAOFF_MASK BIT(30) 366#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) 367/* 368 * SFR Endian status. 369 * 0 - Little Endian order (default after hardware reset). 370 * 1 - Big Endian order. 371 */ 372#define USB_STS_ENDIAN2_MASK BIT(31) 373#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK) 374 375/* USB_CMD - bitmasks */ 376/* Set Function Address */ 377#define USB_CMD_SET_ADDR BIT(0) 378/* 379 * Function Address This field is saved to the device only when the field 380 * SET_ADDR is set '1 ' during write to USB_CMD register. 381 * Software is responsible for entering the address of the device during 382 * SET_ADDRESS request service. This field should be set immediately after 383 * the SETUP packet is decoded, and prior to confirmation of the status phase 384 */ 385#define USB_CMD_FADDR_MASK GENMASK(7, 1) 386#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) 387/* Send Function Wake Device Notification TP (used only in SS mode). */ 388#define USB_CMD_SDNFW BIT(8) 389/* Set Test Mode (used only in HS/FS mode). */ 390#define USB_CMD_STMODE BIT(9) 391/* Test mode selector (used only in HS/FS mode) */ 392#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10) 393#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) 394/* 395 * Send Latency Tolerance Message Device Notification TP (used only 396 * in SS mode). 397 */ 398#define USB_CMD_SDNLTM BIT(12) 399/* Send Custom Transaction Packet (used only in SS mode) */ 400#define USB_CMD_SPKT BIT(13) 401/*Device Notification 'Function Wake' - Interface value (only in SS mode. */ 402#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16) 403#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) 404/* 405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0] 406 * (used only in SS mode). 407 */ 408#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16) 409#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK) 410 411/* USB_ITPN - bitmasks */ 412/* 413 * ITP(SS) / SOF (HS/FS) number 414 * In SS mode this field represent number of last ITP received from host. 415 * In HS/FS mode this field represent number of last SOF received from host. 416 */ 417#define USB_ITPN_MASK GENMASK(13, 0) 418#define USB_ITPN(p) ((p) & USB_ITPN_MASK) 419 420/* USB_LPM - bitmasks */ 421/* Host Initiated Resume Duration. */ 422#define USB_LPM_HIRD_MASK GENMASK(3, 0) 423#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK) 424/* Remote Wakeup Enable (bRemoteWake). */ 425#define USB_LPM_BRW BIT(4) 426 427/* USB_IEN - bitmasks */ 428/* SS connection interrupt enable */ 429#define USB_IEN_CONIEN BIT(0) 430/* SS disconnection interrupt enable. */ 431#define USB_IEN_DISIEN BIT(1) 432/* USB SS warm reset interrupt enable. */ 433#define USB_IEN_UWRESIEN BIT(2) 434/* USB SS hot reset interrupt enable */ 435#define USB_IEN_UHRESIEN BIT(3) 436/* SS link U3 state enter interrupt enable (suspend).*/ 437#define USB_IEN_U3ENTIEN BIT(4) 438/* SS link U3 state exit interrupt enable (wakeup). */ 439#define USB_IEN_U3EXTIEN BIT(5) 440/* SS link U2 state enter interrupt enable.*/ 441#define USB_IEN_U2ENTIEN BIT(6) 442/* SS link U2 state exit interrupt enable.*/ 443#define USB_IEN_U2EXTIEN BIT(7) 444/* SS link U1 state enter interrupt enable.*/ 445#define USB_IEN_U1ENTIEN BIT(8) 446/* SS link U1 state exit interrupt enable.*/ 447#define USB_IEN_U1EXTIEN BIT(9) 448/* ITP/SOF packet detected interrupt enable.*/ 449#define USB_IEN_ITPIEN BIT(10) 450/* Wakeup interrupt enable.*/ 451#define USB_IEN_WAKEIEN BIT(11) 452/* Send Custom Packet interrupt enable.*/ 453#define USB_IEN_SPKTIEN BIT(12) 454/* HS/FS mode connection interrupt enable.*/ 455#define USB_IEN_CON2IEN BIT(16) 456/* HS/FS mode disconnection interrupt enable.*/ 457#define USB_IEN_DIS2IEN BIT(17) 458/* USB reset (HS/FS mode) interrupt enable.*/ 459#define USB_IEN_U2RESIEN BIT(18) 460/* LPM L2 state enter interrupt enable.*/ 461#define USB_IEN_L2ENTIEN BIT(20) 462/* LPM L2 state exit interrupt enable.*/ 463#define USB_IEN_L2EXTIEN BIT(21) 464/* LPM L1 state enter interrupt enable.*/ 465#define USB_IEN_L1ENTIEN BIT(24) 466/* LPM L1 state exit interrupt enable.*/ 467#define USB_IEN_L1EXTIEN BIT(25) 468/* Configuration reset interrupt enable.*/ 469#define USB_IEN_CFGRESIEN BIT(26) 470/* Start of the USB SS warm reset interrupt enable.*/ 471#define USB_IEN_UWRESSIEN BIT(28) 472/* End of the USB SS warm reset interrupt enable.*/ 473#define USB_IEN_UWRESEIEN BIT(29) 474 475#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \ 476 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \ 477 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \ 478 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN) 479 480/* USB_ISTS - bitmasks */ 481/* SS Connection detected. */ 482#define USB_ISTS_CONI BIT(0) 483/* SS Disconnection detected. */ 484#define USB_ISTS_DISI BIT(1) 485/* UUSB warm reset detectede. */ 486#define USB_ISTS_UWRESI BIT(2) 487/* USB hot reset detected. */ 488#define USB_ISTS_UHRESI BIT(3) 489/* U3 link state enter detected (suspend).*/ 490#define USB_ISTS_U3ENTI BIT(4) 491/* U3 link state exit detected (wakeup). */ 492#define USB_ISTS_U3EXTI BIT(5) 493/* U2 link state enter detected.*/ 494#define USB_ISTS_U2ENTI BIT(6) 495/* U2 link state exit detected.*/ 496#define USB_ISTS_U2EXTI BIT(7) 497/* U1 link state enter detected.*/ 498#define USB_ISTS_U1ENTI BIT(8) 499/* U1 link state exit detected.*/ 500#define USB_ISTS_U1EXTI BIT(9) 501/* ITP/SOF packet detected.*/ 502#define USB_ISTS_ITPI BIT(10) 503/* Wakeup detected.*/ 504#define USB_ISTS_WAKEI BIT(11) 505/* Send Custom Packet detected.*/ 506#define USB_ISTS_SPKTI BIT(12) 507/* HS/FS mode connection detected.*/ 508#define USB_ISTS_CON2I BIT(16) 509/* HS/FS mode disconnection detected.*/ 510#define USB_ISTS_DIS2I BIT(17) 511/* USB reset (HS/FS mode) detected.*/ 512#define USB_ISTS_U2RESI BIT(18) 513/* LPM L2 state enter detected.*/ 514#define USB_ISTS_L2ENTI BIT(20) 515/* LPM L2 state exit detected.*/ 516#define USB_ISTS_L2EXTI BIT(21) 517/* LPM L1 state enter detected.*/ 518#define USB_ISTS_L1ENTI BIT(24) 519/* LPM L1 state exit detected.*/ 520#define USB_ISTS_L1EXTI BIT(25) 521/* USB configuration reset detected.*/ 522#define USB_ISTS_CFGRESI BIT(26) 523/* Start of the USB warm reset detected.*/ 524#define USB_ISTS_UWRESSI BIT(28) 525/* End of the USB warm reset detected.*/ 526#define USB_ISTS_UWRESEI BIT(29) 527 528/* USB_SEL - bitmasks */ 529#define EP_SEL_EPNO_MASK GENMASK(3, 0) 530/* Endpoint number. */ 531#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK) 532/* Endpoint direction bit - 0 - OUT, 1 - IN. */ 533#define EP_SEL_DIR BIT(7) 534 535#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR) 536#define select_ep_out (EP_SEL_EPNO(p)) 537 538/* EP_TRADDR - bitmasks */ 539/* Transfer Ring address. */ 540#define EP_TRADDR_TRADDR(p) ((p)) 541 542/* EP_CFG - bitmasks */ 543/* Endpoint enable */ 544#define EP_CFG_ENABLE BIT(0) 545/* 546 * Endpoint type. 547 * 1 - isochronous 548 * 2 - bulk 549 * 3 - interrupt 550 */ 551#define EP_CFG_EPTYPE_MASK GENMASK(2, 1) 552#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK) 553/* Stream support enable (only in SS mode). */ 554#define EP_CFG_STREAM_EN BIT(3) 555/* TDL check (only in SS mode for BULK EP). */ 556#define EP_CFG_TDL_CHK BIT(4) 557/* SID check (only in SS mode for BULK OUT EP). */ 558#define EP_CFG_SID_CHK BIT(5) 559/* DMA transfer endianness. */ 560#define EP_CFG_EPENDIAN BIT(7) 561/* Max burst size (used only in SS mode). */ 562#define EP_CFG_MAXBURST_MASK GENMASK(11, 8) 563#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK) 564#define EP_CFG_MAXBURST_MAX 15 565/* ISO max burst. */ 566#define EP_CFG_MULT_MASK GENMASK(15, 14) 567#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK) 568#define EP_CFG_MULT_MAX 2 569/* ISO max burst. */ 570#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16) 571#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK) 572/* Max number of buffered packets. */ 573#define EP_CFG_BUFFERING_MASK GENMASK(31, 27) 574#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK) 575#define EP_CFG_BUFFERING_MAX 15 576 577/* EP_CMD - bitmasks */ 578/* Endpoint reset. */ 579#define EP_CMD_EPRST BIT(0) 580/* Endpoint STALL set. */ 581#define EP_CMD_SSTALL BIT(1) 582/* Endpoint STALL clear. */ 583#define EP_CMD_CSTALL BIT(2) 584/* Send ERDY TP. */ 585#define EP_CMD_ERDY BIT(3) 586/* Request complete. */ 587#define EP_CMD_REQ_CMPL BIT(5) 588/* Transfer descriptor ready. */ 589#define EP_CMD_DRDY BIT(6) 590/* Data flush. */ 591#define EP_CMD_DFLUSH BIT(7) 592/* 593 * Transfer Descriptor Length write (used only for Bulk Stream capable 594 * endpoints in SS mode). 595 * Bit Removed from DEV_VER_V3 controller version. 596 */ 597#define EP_CMD_STDL BIT(8) 598/* 599 * Transfer Descriptor Length (used only in SS mode for bulk endpoints). 600 * Bits Removed from DEV_VER_V3 controller version. 601 */ 602#define EP_CMD_TDL_MASK GENMASK(15, 9) 603#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK) 604#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9) 605#define EP_CMD_TDL_MAX (EP_CMD_TDL_MASK >> 9) 606 607/* ERDY Stream ID value (used in SS mode). */ 608#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16) 609#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK) 610 611/* EP_STS - bitmasks */ 612/* Setup transfer complete. */ 613#define EP_STS_SETUP BIT(0) 614/* Endpoint STALL status. */ 615#define EP_STS_STALL(p) ((p) & BIT(1)) 616/* Interrupt On Complete. */ 617#define EP_STS_IOC BIT(2) 618/* Interrupt on Short Packet. */ 619#define EP_STS_ISP BIT(3) 620/* Transfer descriptor missing. */ 621#define EP_STS_DESCMIS BIT(4) 622/* Stream Rejected (used only in SS mode) */ 623#define EP_STS_STREAMR BIT(5) 624/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */ 625#define EP_STS_MD_EXIT BIT(6) 626/* TRB error. */ 627#define EP_STS_TRBERR BIT(7) 628/* Not ready (used only in SS mode). */ 629#define EP_STS_NRDY BIT(8) 630/* DMA busy bit. */ 631#define EP_STS_DBUSY BIT(9) 632/* Endpoint Buffer Empty */ 633#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) 634/* Current Cycle Status */ 635#define EP_STS_CCS(p) ((p) & BIT(11)) 636/* Prime (used only in SS mode. */ 637#define EP_STS_PRIME BIT(12) 638/* Stream error (used only in SS mode). */ 639#define EP_STS_SIDERR BIT(13) 640/* OUT size mismatch. */ 641#define EP_STS_OUTSMM BIT(14) 642/* ISO transmission error. */ 643#define EP_STS_ISOERR BIT(15) 644/* Host Packet Pending (only for SS mode). */ 645#define EP_STS_HOSTPP(p) ((p) & BIT(16)) 646/* Stream Protocol State Machine State (only for Bulk stream endpoints). */ 647#define EP_STS_SPSMST_MASK GENMASK(18, 17) 648#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 649#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 650#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 651#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17) 652/* Interrupt On Transfer complete. */ 653#define EP_STS_IOT BIT(19) 654/* OUT queue endpoint number. */ 655#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24) 656#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24) 657/* OUT queue valid flag. */ 658#define EP_STS_OUTQ_VAL_MASK BIT(28) 659#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK) 660/* SETUP WAIT. */ 661#define EP_STS_STPWAIT BIT(31) 662 663/* EP_STS_SID - bitmasks */ 664/* Stream ID (used only in SS mode). */ 665#define EP_STS_SID_MASK GENMASK(15, 0) 666#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK) 667 668/* EP_STS_EN - bitmasks */ 669/* SETUP interrupt enable. */ 670#define EP_STS_EN_SETUPEN BIT(0) 671/* OUT transfer missing descriptor enable. */ 672#define EP_STS_EN_DESCMISEN BIT(4) 673/* Stream Rejected enable. */ 674#define EP_STS_EN_STREAMREN BIT(5) 675/* Move Data Exit enable.*/ 676#define EP_STS_EN_MD_EXITEN BIT(6) 677/* TRB enable. */ 678#define EP_STS_EN_TRBERREN BIT(7) 679/* NRDY enable. */ 680#define EP_STS_EN_NRDYEN BIT(8) 681/* Prime enable. */ 682#define EP_STS_EN_PRIMEEEN BIT(12) 683/* Stream error enable. */ 684#define EP_STS_EN_SIDERREN BIT(13) 685/* OUT size mismatch enable. */ 686#define EP_STS_EN_OUTSMMEN BIT(14) 687/* ISO transmission error enable. */ 688#define EP_STS_EN_ISOERREN BIT(15) 689/* Interrupt on Transmission complete enable. */ 690#define EP_STS_EN_IOTEN BIT(19) 691/* Setup Wait interrupt enable. */ 692#define EP_STS_EN_STPWAITEN BIT(31) 693 694/* DRBL- bitmasks */ 695#define DB_VALUE_BY_INDEX(index) (1 << (index)) 696#define DB_VALUE_EP0_OUT BIT(0) 697#define DB_VALUE_EP0_IN BIT(16) 698 699/* EP_IEN - bitmasks */ 700#define EP_IEN(index) (1 << (index)) 701#define EP_IEN_EP_OUT0 BIT(0) 702#define EP_IEN_EP_IN0 BIT(16) 703 704/* EP_ISTS - bitmasks */ 705#define EP_ISTS(index) (1 << (index)) 706#define EP_ISTS_EP_OUT0 BIT(0) 707#define EP_ISTS_EP_IN0 BIT(16) 708 709/* USB_PWR- bitmasks */ 710/*Power Shut Off capability enable*/ 711#define PUSB_PWR_PSO_EN BIT(0) 712/*Power Shut Off capability disable*/ 713#define PUSB_PWR_PSO_DS BIT(1) 714/* 715 * Enables turning-off Reference Clock. 716 * This bit is optional and implemented only when support for OTG is 717 * implemented (indicated by OTG_READY bit set to '1'). 718 */ 719#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8) 720/* 721 * Status bit indicating that operation required by STB_CLK_SWITCH_EN write 722 * is completed 723 */ 724#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9) 725/* This bit informs if Fast Registers Access is enabled. */ 726#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30) 727/* Fast Registers Access Enable. */ 728#define PUSB_PWR_FST_REG_ACCESS BIT(31) 729 730/* USB_CONF2- bitmasks */ 731/* 732 * Writing 1 disables TDL calculation basing on TRB feature in controller 733 * for DMULT mode. 734 * Bit supported only for DEV_VER_V2 version. 735 */ 736#define USB_CONF2_DIS_TDL_TRB BIT(1) 737/* 738 * Writing 1 enables TDL calculation basing on TRB feature in controller 739 * for DMULT mode. 740 * Bit supported only for DEV_VER_V2 version. 741 */ 742#define USB_CONF2_EN_TDL_TRB BIT(2) 743 744/* USB_CAP1- bitmasks */ 745/* 746 * SFR Interface type 747 * These field reflects type of SFR interface implemented: 748 * 0x0 - OCP 749 * 0x1 - AHB, 750 * 0x2 - PLB 751 * 0x3 - AXI 752 * 0x4-0xF - reserved 753 */ 754#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0) 755#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0) 756#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1) 757#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2) 758#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3) 759/* 760 * SFR Interface width 761 * These field reflects width of SFR interface implemented: 762 * 0x0 - 8 bit interface, 763 * 0x1 - 16 bit interface, 764 * 0x2 - 32 bit interface 765 * 0x3 - 64 bit interface 766 * 0x4-0xF - reserved 767 */ 768#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4) 769#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4)) 770#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4)) 771#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4)) 772#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4)) 773/* 774 * DMA Interface type 775 * These field reflects type of DMA interface implemented: 776 * 0x0 - OCP 777 * 0x1 - AHB, 778 * 0x2 - PLB 779 * 0x3 - AXI 780 * 0x4-0xF - reserved 781 */ 782#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8) 783#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8)) 784#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8)) 785#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8)) 786#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8)) 787/* 788 * DMA Interface width 789 * These field reflects width of DMA interface implemented: 790 * 0x0 - reserved, 791 * 0x1 - reserved, 792 * 0x2 - 32 bit interface 793 * 0x3 - 64 bit interface 794 * 0x4-0xF - reserved 795 */ 796#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12) 797#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12)) 798#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12)) 799/* 800 * USB3 PHY Interface type 801 * These field reflects type of USB3 PHY interface implemented: 802 * 0x0 - USB PIPE, 803 * 0x1 - RMMI, 804 * 0x2-0xF - reserved 805 */ 806#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16) 807#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16)) 808#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16)) 809/* 810 * USB3 PHY Interface width 811 * These field reflects width of USB3 PHY interface implemented: 812 * 0x0 - 8 bit PIPE interface, 813 * 0x1 - 16 bit PIPE interface, 814 * 0x2 - 32 bit PIPE interface, 815 * 0x3 - 64 bit PIPE interface 816 * 0x4-0xF - reserved 817 * Note: When SSIC interface is implemented this field shows the width of 818 * internal PIPE interface. The RMMI interface is always 20bit wide. 819 */ 820#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20) 821#define DEV_U3PHY_WIDTH_8(p) \ 822 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20)) 823#define DEV_U3PHY_WIDTH_16(p) \ 824 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16)) 825#define DEV_U3PHY_WIDTH_32(p) \ 826 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20)) 827#define DEV_U3PHY_WIDTH_64(p) \ 828 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16)) 829 830/* 831 * USB2 PHY Interface enable 832 * These field informs if USB2 PHY interface is implemented: 833 * 0x0 - interface NOT implemented, 834 * 0x1 - interface implemented 835 */ 836#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) 837/* 838 * USB2 PHY Interface type 839 * These field reflects type of USB2 PHY interface implemented: 840 * 0x0 - UTMI, 841 * 0x1 - ULPI 842 */ 843#define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) 844/* 845 * USB2 PHY Interface width 846 * These field reflects width of USB2 PHY interface implemented: 847 * 0x0 - 8 bit interface, 848 * 0x1 - 16 bit interface, 849 * Note: The ULPI interface is always 8bit wide. 850 */ 851#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) 852/* 853 * OTG Ready 854 * 0x0 - pure device mode 855 * 0x1 - some features and ports for CDNS USB OTG controller are implemented. 856 */ 857#define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) 858 859/* 860 * When set, indicates that controller supports automatic internal TDL 861 * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode 862 * Supported only for DEV_VER_V2 controller version. 863 */ 864#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) 865 866/* USB_CAP2- bitmasks */ 867/* 868 * The actual size of the connected On-chip RAM memory in kB: 869 * - 0 means 256 kB (max supported mem size) 870 * - value other than 0 reflects the mem size in kB 871 */ 872#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) 873/* 874 * Max supported mem size 875 * These field reflects width of on-chip RAM address bus width, 876 * which determines max supported mem size: 877 * 0x0-0x7 - reserved, 878 * 0x8 - support for 4kB mem, 879 * 0x9 - support for 8kB mem, 880 * 0xA - support for 16kB mem, 881 * 0xB - support for 32kB mem, 882 * 0xC - support for 64kB mem, 883 * 0xD - support for 128kB mem, 884 * 0xE - support for 256kB mem, 885 * 0xF - reserved 886 */ 887#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8)) 888 889/* USB_CAP3- bitmasks */ 890#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index))) 891 892/* USB_CAP4- bitmasks */ 893#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index))) 894 895/* USB_CAP5- bitmasks */ 896#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index))) 897 898/* USB_CAP6- bitmasks */ 899/* The USBSS-DEV Controller Internal build number. */ 900#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0)) 901/* The USBSS-DEV Controller version number. */ 902#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24)) 903 904#define DEV_VER_NXP_V1 0x00024502 905#define DEV_VER_TI_V1 0x00024509 906#define DEV_VER_V2 0x0002450C 907#define DEV_VER_V3 0x0002450d 908 909/* DBG_LINK1- bitmasks */ 910/* 911 * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum 912 * time required for decoding the received LFPS as an LFPS.U1_Exit. 913 */ 914#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) 915/* 916 * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for 917 * phytxelecidle deassertion when LFPS.U1_Exit 918 */ 919#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8) 920#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) 921/* 922 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end 923 * Receiver termination detection sequence: 924 * 0: it is possible that USBSS_DEV will terminate Farend receiver 925 * termination detection sequence 926 * 1: USBSS_DEV will not terminate Far-end receiver termination 927 * detection sequence 928 */ 929#define DBG_LINK1_RXDET_BREAK_DIS BIT(16) 930/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */ 931#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) 932/* 933 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the 934 * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically 935 * cleared. Writing '0' has no effect 936 */ 937#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24) 938/* 939 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the 940 * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically 941 * cleared. Writing '0' has no effect 942 */ 943#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25) 944/* 945 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes 946 * the RXDET_BREAK_DIS field value to the device. This bit is automatically 947 * cleared. Writing '0' has no effect 948 */ 949#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26) 950/* 951 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes 952 * the LFPS_GEN_PING field value to the device. This bit is automatically 953 * cleared. Writing '0' has no effect." 954 */ 955#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27) 956 957/* DMA_AXI_CTRL- bitmasks */ 958/* The mawprot pin configuration. */ 959#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0)) 960/* The marprot pin configuration. */ 961#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16) 962#define DMA_AXI_CTRL_NON_SECURE 0x02 963 964#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget)) 965 966#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint)) 967 968/*-------------------------------------------------------------------------*/ 969/* 970 * USBSS-DEV DMA interface. 971 */ 972#define TRBS_PER_SEGMENT 600 973 974#define ISO_MAX_INTERVAL 10 975 976#define MAX_TRB_LENGTH BIT(16) 977 978#if TRBS_PER_SEGMENT < 2 979#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." 980#endif 981 982#define TRBS_PER_STREAM_SEGMENT 2 983 984#if TRBS_PER_STREAM_SEGMENT < 2 985#error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2." 986#endif 987 988/* 989 *Only for ISOC endpoints - maximum number of TRBs is calculated as 990 * pow(2, bInterval-1) * number of usb requests. It is limitation made by 991 * driver to save memory. Controller must prepare TRB for each ITP even 992 * if bInterval > 1. It's the reason why driver needs so many TRBs for 993 * isochronous endpoints. 994 */ 995#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8) 996 997#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \ 998 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT) 999/** 1000 * struct cdns3_trb - represent Transfer Descriptor block. 1001 * @buffer: pointer to buffer data 1002 * @length: length of data 1003 * @control: control flags. 1004 * 1005 * This structure describes transfer block serviced by DMA module. 1006 */ 1007struct cdns3_trb { 1008 __le32 buffer; 1009 __le32 length; 1010 __le32 control; 1011}; 1012 1013#define TRB_SIZE (sizeof(struct cdns3_trb)) 1014#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT) 1015#define TRB_STREAM_RING_SIZE (TRB_SIZE * TRBS_PER_STREAM_SEGMENT) 1016#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT) 1017#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2) 1018 1019/* TRB bit mask */ 1020#define TRB_TYPE_BITMASK GENMASK(15, 10) 1021#define TRB_TYPE(p) ((p) << 10) 1022#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1023 1024/* TRB type IDs */ 1025/* bulk, interrupt, isoc , and control data stage */ 1026#define TRB_NORMAL 1 1027/* TRB for linking ring segments */ 1028#define TRB_LINK 6 1029 1030/* Cycle bit - indicates TRB ownership by driver or hw*/ 1031#define TRB_CYCLE BIT(0) 1032/* 1033 * When set to '1', the device will toggle its interpretation of the Cycle bit 1034 */ 1035#define TRB_TOGGLE BIT(1) 1036/* 1037 * The controller will set it if OUTSMM (OUT size mismatch) is detected, 1038 * this bit is for normal TRB 1039 */ 1040#define TRB_SMM BIT(1) 1041 1042/* 1043 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was 1044 * processed while USB short packet was received. No more buffers defined by 1045 * the TD will be used. DMA will automatically advance to next TD. 1046 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring 1047 * - Shall be set to 1 by Controller when Short Packet condition for this TRB 1048 * is detected independent if ISP is set or not. 1049 */ 1050#define TRB_SP BIT(1) 1051 1052/* Interrupt on short packet*/ 1053#define TRB_ISP BIT(2) 1054/*Setting this bit enables FIFO DMA operation mode*/ 1055#define TRB_FIFO_MODE BIT(3) 1056/* Set PCIe no snoop attribute */ 1057#define TRB_CHAIN BIT(4) 1058/* Interrupt on completion */ 1059#define TRB_IOC BIT(5) 1060 1061/* stream ID bitmasks. */ 1062#define TRB_STREAM_ID_BITMASK GENMASK(31, 16) 1063#define TRB_STREAM_ID(p) ((p) << 16) 1064#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16) 1065 1066/* Size of TD expressed in USB packets for HS/FS mode. */ 1067#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16)) 1068#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16) 1069 1070/* transfer_len bitmasks. */ 1071#define TRB_LEN(p) ((p) & GENMASK(16, 0)) 1072 1073/* Size of TD expressed in USB packets for SS mode. */ 1074#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17)) 1075#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17) 1076 1077/* transfer_len bitmasks - bits 31:24 */ 1078#define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24)) 1079#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24) 1080 1081/* Data buffer pointer bitmasks*/ 1082#define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) 1083 1084/*-------------------------------------------------------------------------*/ 1085/* Driver numeric constants */ 1086 1087/* Such declaration should be added to ch9.h */ 1088#define USB_DEVICE_MAX_ADDRESS 127 1089 1090/* Endpoint init values */ 1091#define CDNS3_EP_MAX_PACKET_LIMIT 1024 1092#define CDNS3_EP_MAX_STREAMS 15 1093#define CDNS3_EP0_MAX_PACKET_LIMIT 512 1094 1095/* All endpoints including EP0 */ 1096#define CDNS3_ENDPOINTS_MAX_COUNT 32 1097#define CDNS3_EP_ZLP_BUF_SIZE 1024 1098 1099#define CDNS3_MAX_NUM_DESCMISS_BUF 32 1100#define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */ 1101#define CDNS3_WA2_NUM_BUFFERS 128 1102/*-------------------------------------------------------------------------*/ 1103/* Used structs */ 1104 1105struct cdns3_device; 1106 1107/** 1108 * struct cdns3_endpoint - extended device side representation of USB endpoint. 1109 * @endpoint: usb endpoint 1110 * @pending_req_list: list of requests queuing on transfer ring. 1111 * @deferred_req_list: list of requests waiting for queuing on transfer ring. 1112 * @wa2_descmiss_req_list: list of requests internally allocated by driver. 1113 * @trb_pool: transfer ring - array of transaction buffers 1114 * @trb_pool_dma: dma address of transfer ring 1115 * @cdns3_dev: device associated with this endpoint 1116 * @name: a human readable name e.g. ep1out 1117 * @flags: specify the current state of endpoint 1118 * @descmis_req: internal transfer object used for getting data from on-chip 1119 * buffer. It can happen only if function driver doesn't send usb_request 1120 * object on time. 1121 * @dir: endpoint direction 1122 * @num: endpoint number (1 - 15) 1123 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 1124 * @interval: interval between packets used for ISOC endpoint. 1125 * @free_trbs: number of free TRBs in transfer ring 1126 * @num_trbs: number of all TRBs in transfer ring 1127 * @alloc_ring_size: size of the allocated TRB ring 1128 * @pcs: producer cycle state 1129 * @ccs: consumer cycle state 1130 * @enqueue: enqueue index in transfer ring 1131 * @dequeue: dequeue index in transfer ring 1132 * @trb_burst_size: number of burst used in trb. 1133 */ 1134struct cdns3_endpoint { 1135 struct usb_ep endpoint; 1136 struct list_head pending_req_list; 1137 struct list_head deferred_req_list; 1138 struct list_head wa2_descmiss_req_list; 1139 int wa2_counter; 1140 1141 struct cdns3_trb *trb_pool; 1142 dma_addr_t trb_pool_dma; 1143 1144 struct cdns3_device *cdns3_dev; 1145 char name[20]; 1146 1147#define EP_ENABLED BIT(0) 1148#define EP_STALLED BIT(1) 1149#define EP_STALL_PENDING BIT(2) 1150#define EP_WEDGE BIT(3) 1151#define EP_TRANSFER_STARTED BIT(4) 1152#define EP_UPDATE_EP_TRBADDR BIT(5) 1153#define EP_PENDING_REQUEST BIT(6) 1154#define EP_RING_FULL BIT(7) 1155#define EP_CLAIMED BIT(8) 1156#define EP_DEFERRED_DRDY BIT(9) 1157#define EP_QUIRK_ISO_OUT_EN BIT(10) 1158#define EP_QUIRK_END_TRANSFER BIT(11) 1159#define EP_QUIRK_EXTRA_BUF_DET BIT(12) 1160#define EP_QUIRK_EXTRA_BUF_EN BIT(13) 1161#define EP_TDLCHK_EN BIT(15) 1162#define EP_CONFIGURED BIT(16) 1163 u32 flags; 1164 1165 struct cdns3_request *descmis_req; 1166 1167 u8 dir; 1168 u8 num; 1169 u8 type; 1170 u8 mult; 1171 u8 bMaxBurst; 1172 u16 wMaxPacketSize; 1173 int interval; 1174 1175 int free_trbs; 1176 int num_trbs; 1177 int alloc_ring_size; 1178 u8 pcs; 1179 u8 ccs; 1180 int enqueue; 1181 int dequeue; 1182 u8 trb_burst_size; 1183 1184 unsigned int wa1_set:1; 1185 struct cdns3_trb *wa1_trb; 1186 unsigned int wa1_trb_index; 1187 unsigned int wa1_cycle_bit:1; 1188 1189 /* Stream related */ 1190 unsigned int use_streams:1; 1191 unsigned int prime_flag:1; 1192 u32 ep_sts_pending; 1193 u16 last_stream_id; 1194 u16 pending_tdl; 1195 unsigned int stream_sg_idx; 1196}; 1197 1198/** 1199 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer 1200 * @buf: aligned to 8 bytes data buffer. Buffer address used in 1201 * TRB shall be aligned to 8. 1202 * @dma: dma address 1203 * @size: size of buffer 1204 * @in_use: inform if this buffer is associated with usb_request 1205 * @list: used to adding instance of this object to list 1206 */ 1207struct cdns3_aligned_buf { 1208 void *buf; 1209 dma_addr_t dma; 1210 u32 size; 1211 unsigned in_use:1; 1212 struct list_head list; 1213}; 1214 1215/** 1216 * struct cdns3_request - extended device side representation of usb_request 1217 * object . 1218 * @request: generic usb_request object describing single I/O request. 1219 * @priv_ep: extended representation of usb_ep object 1220 * @trb: the first TRB association with this request 1221 * @start_trb: number of the first TRB in transfer ring 1222 * @end_trb: number of the last TRB in transfer ring 1223 * @aligned_buf: object holds information about aligned buffer associated whit 1224 * this endpoint 1225 * @flags: flag specifying special usage of request 1226 * @list: used by internally allocated request to add to wa2_descmiss_req_list. 1227 * @finished_trb: number of trb has already finished per request 1228 * @num_of_trb: how many trbs in this request 1229 */ 1230struct cdns3_request { 1231 struct usb_request request; 1232 struct cdns3_endpoint *priv_ep; 1233 struct cdns3_trb *trb; 1234 int start_trb; 1235 int end_trb; 1236 struct cdns3_aligned_buf *aligned_buf; 1237#define REQUEST_PENDING BIT(0) 1238#define REQUEST_INTERNAL BIT(1) 1239#define REQUEST_INTERNAL_CH BIT(2) 1240#define REQUEST_ZLP BIT(3) 1241#define REQUEST_UNALIGNED BIT(4) 1242 u32 flags; 1243 struct list_head list; 1244 int finished_trb; 1245 int num_of_trb; 1246}; 1247 1248#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request)) 1249 1250/*Stages used during enumeration process.*/ 1251#define CDNS3_SETUP_STAGE 0x0 1252#define CDNS3_DATA_STAGE 0x1 1253#define CDNS3_STATUS_STAGE 0x2 1254 1255/** 1256 * struct cdns3_device - represent USB device. 1257 * @dev: pointer to device structure associated whit this controller 1258 * @sysdev: pointer to the DMA capable device 1259 * @gadget: device side representation of the peripheral controller 1260 * @gadget_driver: pointer to the gadget driver 1261 * @dev_ver: device controller version. 1262 * @lock: for synchronizing 1263 * @regs: base address for device side registers 1264 * @setup_buf: used while processing usb control requests 1265 * @setup_dma: dma address for setup_buf 1266 * @zlp_buf - zlp buffer 1267 * @ep0_stage: ep0 stage during enumeration process. 1268 * @ep0_data_dir: direction for control transfer 1269 * @eps: array of pointers to all endpoints with exclusion ep0 1270 * @aligned_buf_list: list of aligned buffers internally allocated by driver 1271 * @aligned_buf_wq: workqueue freeing no longer used aligned buf. 1272 * @selected_ep: actually selected endpoint. It's used only to improve 1273 * performance. 1274 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP. 1275 * @u1_allowed: allow device transition to u1 state 1276 * @u2_allowed: allow device transition to u2 state 1277 * @is_selfpowered: device is self powered 1278 * @setup_pending: setup packet is processing by gadget driver 1279 * @hw_configured_flag: hardware endpoint configuration was set. 1280 * @wake_up_flag: allow device to remote up the host 1281 * @status_completion_no_call: indicate that driver is waiting for status s 1282 * stage completion. It's used in deferred SET_CONFIGURATION request. 1283 * @onchip_buffers: number of available on-chip buffers. 1284 * @onchip_used_size: actual size of on-chip memory assigned to endpoints. 1285 * @pending_status_wq: workqueue handling status stage for deferred requests. 1286 * @pending_status_request: request for which status stage was deferred 1287 */ 1288struct cdns3_device { 1289 struct device *dev; 1290 struct device *sysdev; 1291 1292 struct usb_gadget gadget; 1293 struct usb_gadget_driver *gadget_driver; 1294 1295#define CDNS_REVISION_V0 0x00024501 1296#define CDNS_REVISION_V1 0x00024509 1297 u32 dev_ver; 1298 1299 /* generic spin-lock for drivers */ 1300 spinlock_t lock; 1301 1302 struct cdns3_usb_regs __iomem *regs; 1303 1304 struct usb_ctrlrequest *setup_buf; 1305 dma_addr_t setup_dma; 1306 void *zlp_buf; 1307 1308 u8 ep0_stage; 1309 int ep0_data_dir; 1310 1311 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT]; 1312 1313 struct list_head aligned_buf_list; 1314 struct work_struct aligned_buf_wq; 1315 1316 u32 selected_ep; 1317 u16 isoch_delay; 1318 1319 unsigned wait_for_setup:1; 1320 unsigned u1_allowed:1; 1321 unsigned u2_allowed:1; 1322 unsigned is_selfpowered:1; 1323 unsigned setup_pending:1; 1324 unsigned hw_configured_flag:1; 1325 unsigned wake_up_flag:1; 1326 unsigned status_completion_no_call:1; 1327 unsigned using_streams:1; 1328 int out_mem_is_allocated; 1329 1330 struct work_struct pending_status_wq; 1331 struct usb_request *pending_status_request; 1332 1333 /*in KB */ 1334 u16 onchip_buffers; 1335 u16 onchip_used_size; 1336 1337 u16 ep_buf_size; 1338 u16 ep_iso_burst; 1339}; 1340 1341void cdns3_set_register_bit(void __iomem *ptr, u32 mask); 1342dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, 1343 struct cdns3_trb *trb); 1344enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev); 1345void cdns3_pending_setup_status_handler(struct work_struct *work); 1346void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev); 1347void cdns3_set_hw_configuration(struct cdns3_device *priv_dev); 1348void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep); 1349void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable); 1350struct usb_request *cdns3_next_request(struct list_head *list); 1351void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm); 1352int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep); 1353u8 cdns3_ep_addr_to_index(u8 ep_addr); 1354int cdns3_gadget_ep_set_wedge(struct usb_ep *ep); 1355int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value); 1356void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep); 1357int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep); 1358struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, 1359 gfp_t gfp_flags); 1360void cdns3_gadget_ep_free_request(struct usb_ep *ep, 1361 struct usb_request *request); 1362int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request); 1363void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, 1364 struct cdns3_request *priv_req, 1365 int status); 1366 1367int cdns3_init_ep0(struct cdns3_device *priv_dev, 1368 struct cdns3_endpoint *priv_ep); 1369void cdns3_ep0_config(struct cdns3_device *priv_dev); 1370int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable); 1371void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir); 1372int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev); 1373 1374#endif /* __LINUX_CDNS3_GADGET */ 1375