1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Cadence UART driver (found in Xilinx Zynq) 4 * 5 * 2011 - 2014 (C) Xilinx Inc. 6 * 7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 8 * still shows in the naming of this file, the kconfig symbols and some symbols 9 * in the code. 10 */ 11 12#include <linux/platform_device.h> 13#include <linux/serial.h> 14#include <linux/console.h> 15#include <linux/serial_core.h> 16#include <linux/slab.h> 17#include <linux/tty.h> 18#include <linux/tty_flip.h> 19#include <linux/clk.h> 20#include <linux/irq.h> 21#include <linux/io.h> 22#include <linux/of.h> 23#include <linux/module.h> 24#include <linux/pm_runtime.h> 25#include <linux/iopoll.h> 26 27#define CDNS_UART_TTY_NAME "ttyPS" 28#define CDNS_UART_NAME "xuartps" 29#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 30#define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 31#define CDNS_UART_NR_PORTS 16 32#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 33#define CDNS_UART_REGISTER_SPACE 0x1000 34#define TX_TIMEOUT 500000 35 36/* Rx Trigger level */ 37static int rx_trigger_level = 56; 38module_param(rx_trigger_level, uint, 0444); 39MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 40 41/* Rx Timeout */ 42static int rx_timeout = 10; 43module_param(rx_timeout, uint, 0444); 44MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 45 46/* Register offsets for the UART. */ 47#define CDNS_UART_CR 0x00 /* Control Register */ 48#define CDNS_UART_MR 0x04 /* Mode Register */ 49#define CDNS_UART_IER 0x08 /* Interrupt Enable */ 50#define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 51#define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 52#define CDNS_UART_ISR 0x14 /* Interrupt Status */ 53#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 54#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 55#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 56#define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 57#define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 58#define CDNS_UART_SR 0x2C /* Channel Status */ 59#define CDNS_UART_FIFO 0x30 /* FIFO */ 60#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 61#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 62#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 63#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 64#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 65#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 66 67/* Control Register Bit Definitions */ 68#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 69#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 70#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 71#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 72#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 73#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 74#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 75#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 76#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 77#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 78#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 79#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 80 81/* 82 * Mode Register: 83 * The mode register (MR) defines the mode of transfer as well as the data 84 * format. If this register is modified during transmission or reception, 85 * data validity cannot be guaranteed. 86 */ 87#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 88#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 89#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 90#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 91 92#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 93#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 94 95#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 96#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 97#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 98#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 99#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 100 101#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 102#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 103#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 104 105/* 106 * Interrupt Registers: 107 * Interrupt control logic uses the interrupt enable register (IER) and the 108 * interrupt disable register (IDR) to set the value of the bits in the 109 * interrupt mask register (IMR). The IMR determines whether to pass an 110 * interrupt to the interrupt status register (ISR). 111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 112 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 113 * Reading either IER or IDR returns 0x00. 114 * All four registers have the same bit definitions. 115 */ 116#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 117#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 118#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 119#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 120#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 121#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 122#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 123#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 124#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 125#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 126#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */ 127 128 /* 129 * Do not enable parity error interrupt for the following 130 * reason: When parity error interrupt is enabled, each Rx 131 * parity error always results in 2 events. The first one 132 * being parity error interrupt and the second one with a 133 * proper Rx interrupt with the incoming data. Disabling 134 * parity error interrupt ensures better handling of parity 135 * error events. With this change, for a parity error case, we 136 * get a Rx interrupt with parity error set in ISR register 137 * and we still handle parity errors in the desired way. 138 */ 139 140#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 141 CDNS_UART_IXR_OVERRUN | \ 142 CDNS_UART_IXR_RXTRIG | \ 143 CDNS_UART_IXR_TOUT) 144 145/* Goes in read_status_mask for break detection as the HW doesn't do it*/ 146#define CDNS_UART_IXR_BRK 0x00002000 147 148#define CDNS_UART_RXBS_SUPPORT BIT(1) 149/* 150 * Modem Control register: 151 * The read/write Modem Control register controls the interface with the modem 152 * or data set, or a peripheral device emulating a modem. 153 */ 154#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 155#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 156#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 157 158/* 159 * Modem Status register: 160 * The read/write Modem Status register reports the interface with the modem 161 * or data set, or a peripheral device emulating a modem. 162 */ 163#define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */ 164#define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */ 165#define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */ 166#define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */ 167 168/* 169 * Channel Status Register: 170 * The channel status register (CSR) is provided to enable the control logic 171 * to monitor the status of bits in the channel interrupt status register, 172 * even if these are masked out by the interrupt mask register. 173 */ 174#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 175#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 176#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 177#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 178#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */ 179 180/* baud dividers min/max values */ 181#define CDNS_UART_BDIV_MIN 4 182#define CDNS_UART_BDIV_MAX 255 183#define CDNS_UART_CD_MAX 65535 184#define UART_AUTOSUSPEND_TIMEOUT 3000 185 186/** 187 * struct cdns_uart - device data 188 * @port: Pointer to the UART port 189 * @uartclk: Reference clock 190 * @pclk: APB clock 191 * @cdns_uart_driver: Pointer to UART driver 192 * @baud: Current baud rate 193 * @clk_rate_change_nb: Notifier block for clock changes 194 * @quirks: Flags for RXBS support. 195 */ 196struct cdns_uart { 197 struct uart_port *port; 198 struct clk *uartclk; 199 struct clk *pclk; 200 struct uart_driver *cdns_uart_driver; 201 unsigned int baud; 202 struct notifier_block clk_rate_change_nb; 203 u32 quirks; 204 bool cts_override; 205}; 206struct cdns_platform_data { 207 u32 quirks; 208}; 209#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 210 clk_rate_change_nb) 211 212/** 213 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 214 * @dev_id: Id of the UART port 215 * @isrstatus: The interrupt status register value as read 216 * Return: None 217 */ 218static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 219{ 220 struct uart_port *port = (struct uart_port *)dev_id; 221 struct cdns_uart *cdns_uart = port->private_data; 222 unsigned int data; 223 unsigned int rxbs_status = 0; 224 unsigned int status_mask; 225 unsigned int framerrprocessed = 0; 226 char status = TTY_NORMAL; 227 bool is_rxbs_support; 228 229 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 230 231 while ((readl(port->membase + CDNS_UART_SR) & 232 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 233 if (is_rxbs_support) 234 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 235 data = readl(port->membase + CDNS_UART_FIFO); 236 port->icount.rx++; 237 /* 238 * There is no hardware break detection in Zynq, so we interpret 239 * framing error with all-zeros data as a break sequence. 240 * Most of the time, there's another non-zero byte at the 241 * end of the sequence. 242 */ 243 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 244 if (!data) { 245 port->read_status_mask |= CDNS_UART_IXR_BRK; 246 framerrprocessed = 1; 247 continue; 248 } 249 } 250 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 251 port->icount.brk++; 252 status = TTY_BREAK; 253 if (uart_handle_break(port)) 254 continue; 255 } 256 257 isrstatus &= port->read_status_mask; 258 isrstatus &= ~port->ignore_status_mask; 259 status_mask = port->read_status_mask; 260 status_mask &= ~port->ignore_status_mask; 261 262 if (data && 263 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 264 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 265 port->icount.brk++; 266 if (uart_handle_break(port)) 267 continue; 268 } 269 270 if (uart_handle_sysrq_char(port, data)) 271 continue; 272 273 if (is_rxbs_support) { 274 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 275 && (status_mask & CDNS_UART_IXR_PARITY)) { 276 port->icount.parity++; 277 status = TTY_PARITY; 278 } 279 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 280 && (status_mask & CDNS_UART_IXR_PARITY)) { 281 port->icount.frame++; 282 status = TTY_FRAME; 283 } 284 } else { 285 if (isrstatus & CDNS_UART_IXR_PARITY) { 286 port->icount.parity++; 287 status = TTY_PARITY; 288 } 289 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 290 !framerrprocessed) { 291 port->icount.frame++; 292 status = TTY_FRAME; 293 } 294 } 295 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 296 port->icount.overrun++; 297 tty_insert_flip_char(&port->state->port, 0, 298 TTY_OVERRUN); 299 } 300 tty_insert_flip_char(&port->state->port, data, status); 301 isrstatus = 0; 302 } 303 spin_unlock(&port->lock); 304 tty_flip_buffer_push(&port->state->port); 305 spin_lock(&port->lock); 306} 307 308/** 309 * cdns_uart_handle_tx - Handle the bytes to be Txed. 310 * @dev_id: Id of the UART port 311 * Return: None 312 */ 313static void cdns_uart_handle_tx(void *dev_id) 314{ 315 struct uart_port *port = (struct uart_port *)dev_id; 316 unsigned int numbytes; 317 318 if (uart_circ_empty(&port->state->xmit)) { 319 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 320 } else { 321 numbytes = port->fifosize; 322 while (numbytes && !uart_circ_empty(&port->state->xmit) && 323 !(readl(port->membase + CDNS_UART_SR) & 324 CDNS_UART_SR_TXFULL)) { 325 /* 326 * Get the data from the UART circular buffer 327 * and write it to the cdns_uart's TX_FIFO 328 * register. 329 */ 330 writel( 331 port->state->xmit.buf[port->state->xmit.tail], 332 port->membase + CDNS_UART_FIFO); 333 334 port->icount.tx++; 335 336 /* 337 * Adjust the tail of the UART buffer and wrap 338 * the buffer if it reaches limit. 339 */ 340 port->state->xmit.tail = 341 (port->state->xmit.tail + 1) & 342 (UART_XMIT_SIZE - 1); 343 344 numbytes--; 345 } 346 347 if (uart_circ_chars_pending( 348 &port->state->xmit) < WAKEUP_CHARS) 349 uart_write_wakeup(port); 350 } 351} 352 353/** 354 * cdns_uart_isr - Interrupt handler 355 * @irq: Irq number 356 * @dev_id: Id of the port 357 * 358 * Return: IRQHANDLED 359 */ 360static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 361{ 362 struct uart_port *port = (struct uart_port *)dev_id; 363 unsigned int isrstatus; 364 365 spin_lock(&port->lock); 366 367 /* Read the interrupt status register to determine which 368 * interrupt(s) is/are active and clear them. 369 */ 370 isrstatus = readl(port->membase + CDNS_UART_ISR); 371 writel(isrstatus, port->membase + CDNS_UART_ISR); 372 373 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 374 cdns_uart_handle_tx(dev_id); 375 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 376 } 377 378 isrstatus &= port->read_status_mask; 379 isrstatus &= ~port->ignore_status_mask; 380 /* 381 * Skip RX processing if RX is disabled as RXEMPTY will never be set 382 * as read bytes will not be removed from the FIFO. 383 */ 384 if (isrstatus & CDNS_UART_IXR_RXMASK && 385 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 386 cdns_uart_handle_rx(dev_id, isrstatus); 387 388 spin_unlock(&port->lock); 389 return IRQ_HANDLED; 390} 391 392/** 393 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 394 * @clk: UART module input clock 395 * @baud: Desired baud rate 396 * @rbdiv: BDIV value (return value) 397 * @rcd: CD value (return value) 398 * @div8: Value for clk_sel bit in mod (return value) 399 * Return: baud rate, requested baud when possible, or actual baud when there 400 * was too much error, zero if no valid divisors are found. 401 * 402 * Formula to obtain baud rate is 403 * baud_tx/rx rate = clk/CD * (BDIV + 1) 404 * input_clk = (Uart User Defined Clock or Apb Clock) 405 * depends on UCLKEN in MR Reg 406 * clk = input_clk or input_clk/8; 407 * depends on CLKS in MR reg 408 * CD and BDIV depends on values in 409 * baud rate generate register 410 * baud rate clock divisor register 411 */ 412static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 413 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 414{ 415 u32 cd, bdiv; 416 unsigned int calc_baud; 417 unsigned int bestbaud = 0; 418 unsigned int bauderror; 419 unsigned int besterror = ~0; 420 421 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 422 *div8 = 1; 423 clk /= 8; 424 } else { 425 *div8 = 0; 426 } 427 428 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 429 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 430 if (cd < 1 || cd > CDNS_UART_CD_MAX) 431 continue; 432 433 calc_baud = clk / (cd * (bdiv + 1)); 434 435 if (baud > calc_baud) 436 bauderror = baud - calc_baud; 437 else 438 bauderror = calc_baud - baud; 439 440 if (besterror > bauderror) { 441 *rbdiv = bdiv; 442 *rcd = cd; 443 bestbaud = calc_baud; 444 besterror = bauderror; 445 } 446 } 447 /* use the values when percent error is acceptable */ 448 if (((besterror * 100) / baud) < 3) 449 bestbaud = baud; 450 451 return bestbaud; 452} 453 454/** 455 * cdns_uart_set_baud_rate - Calculate and set the baud rate 456 * @port: Handle to the uart port structure 457 * @baud: Baud rate to set 458 * Return: baud rate, requested baud when possible, or actual baud when there 459 * was too much error, zero if no valid divisors are found. 460 */ 461static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 462 unsigned int baud) 463{ 464 unsigned int calc_baud; 465 u32 cd = 0, bdiv = 0; 466 u32 mreg; 467 int div8; 468 struct cdns_uart *cdns_uart = port->private_data; 469 470 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 471 &div8); 472 473 /* Write new divisors to hardware */ 474 mreg = readl(port->membase + CDNS_UART_MR); 475 if (div8) 476 mreg |= CDNS_UART_MR_CLKSEL; 477 else 478 mreg &= ~CDNS_UART_MR_CLKSEL; 479 writel(mreg, port->membase + CDNS_UART_MR); 480 writel(cd, port->membase + CDNS_UART_BAUDGEN); 481 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 482 cdns_uart->baud = baud; 483 484 return calc_baud; 485} 486 487#ifdef CONFIG_COMMON_CLK 488/** 489 * cdns_uart_clk_notitifer_cb - Clock notifier callback 490 * @nb: Notifier block 491 * @event: Notify event 492 * @data: Notifier data 493 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 494 */ 495static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 496 unsigned long event, void *data) 497{ 498 u32 ctrl_reg; 499 struct uart_port *port; 500 int locked = 0; 501 struct clk_notifier_data *ndata = data; 502 unsigned long flags = 0; 503 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 504 505 port = cdns_uart->port; 506 if (port->suspended) 507 return NOTIFY_OK; 508 509 switch (event) { 510 case PRE_RATE_CHANGE: 511 { 512 u32 bdiv, cd; 513 int div8; 514 515 /* 516 * Find out if current baud-rate can be achieved with new clock 517 * frequency. 518 */ 519 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 520 &bdiv, &cd, &div8)) { 521 dev_warn(port->dev, "clock rate change rejected\n"); 522 return NOTIFY_BAD; 523 } 524 525 spin_lock_irqsave(&cdns_uart->port->lock, flags); 526 527 /* Disable the TX and RX to set baud rate */ 528 ctrl_reg = readl(port->membase + CDNS_UART_CR); 529 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 530 writel(ctrl_reg, port->membase + CDNS_UART_CR); 531 532 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 533 534 return NOTIFY_OK; 535 } 536 case POST_RATE_CHANGE: 537 /* 538 * Set clk dividers to generate correct baud with new clock 539 * frequency. 540 */ 541 542 spin_lock_irqsave(&cdns_uart->port->lock, flags); 543 544 locked = 1; 545 port->uartclk = ndata->new_rate; 546 547 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 548 cdns_uart->baud); 549 fallthrough; 550 case ABORT_RATE_CHANGE: 551 if (!locked) 552 spin_lock_irqsave(&cdns_uart->port->lock, flags); 553 554 /* Set TX/RX Reset */ 555 ctrl_reg = readl(port->membase + CDNS_UART_CR); 556 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 557 writel(ctrl_reg, port->membase + CDNS_UART_CR); 558 559 while (readl(port->membase + CDNS_UART_CR) & 560 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 561 cpu_relax(); 562 563 /* 564 * Clear the RX disable and TX disable bits and then set the TX 565 * enable bit and RX enable bit to enable the transmitter and 566 * receiver. 567 */ 568 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 569 ctrl_reg = readl(port->membase + CDNS_UART_CR); 570 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 571 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 572 writel(ctrl_reg, port->membase + CDNS_UART_CR); 573 574 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 575 576 return NOTIFY_OK; 577 default: 578 return NOTIFY_DONE; 579 } 580} 581#endif 582 583/** 584 * cdns_uart_start_tx - Start transmitting bytes 585 * @port: Handle to the uart port structure 586 */ 587static void cdns_uart_start_tx(struct uart_port *port) 588{ 589 unsigned int status; 590 591 if (uart_tx_stopped(port)) 592 return; 593 594 /* 595 * Set the TX enable bit and clear the TX disable bit to enable the 596 * transmitter. 597 */ 598 status = readl(port->membase + CDNS_UART_CR); 599 status &= ~CDNS_UART_CR_TX_DIS; 600 status |= CDNS_UART_CR_TX_EN; 601 writel(status, port->membase + CDNS_UART_CR); 602 603 if (uart_circ_empty(&port->state->xmit)) 604 return; 605 606 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 607 608 cdns_uart_handle_tx(port); 609 610 /* Enable the TX Empty interrupt */ 611 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 612} 613 614/** 615 * cdns_uart_stop_tx - Stop TX 616 * @port: Handle to the uart port structure 617 */ 618static void cdns_uart_stop_tx(struct uart_port *port) 619{ 620 unsigned int regval; 621 622 regval = readl(port->membase + CDNS_UART_CR); 623 regval |= CDNS_UART_CR_TX_DIS; 624 /* Disable the transmitter */ 625 writel(regval, port->membase + CDNS_UART_CR); 626} 627 628/** 629 * cdns_uart_stop_rx - Stop RX 630 * @port: Handle to the uart port structure 631 */ 632static void cdns_uart_stop_rx(struct uart_port *port) 633{ 634 unsigned int regval; 635 636 /* Disable RX IRQs */ 637 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 638 639 /* Disable the receiver */ 640 regval = readl(port->membase + CDNS_UART_CR); 641 regval |= CDNS_UART_CR_RX_DIS; 642 writel(regval, port->membase + CDNS_UART_CR); 643} 644 645/** 646 * cdns_uart_tx_empty - Check whether TX is empty 647 * @port: Handle to the uart port structure 648 * 649 * Return: TIOCSER_TEMT on success, 0 otherwise 650 */ 651static unsigned int cdns_uart_tx_empty(struct uart_port *port) 652{ 653 unsigned int status; 654 655 status = readl(port->membase + CDNS_UART_SR) & 656 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE); 657 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0; 658} 659 660/** 661 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 662 * transmitting char breaks 663 * @port: Handle to the uart port structure 664 * @ctl: Value based on which start or stop decision is taken 665 */ 666static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 667{ 668 unsigned int status; 669 unsigned long flags; 670 671 spin_lock_irqsave(&port->lock, flags); 672 673 status = readl(port->membase + CDNS_UART_CR); 674 675 if (ctl == -1) 676 writel(CDNS_UART_CR_STARTBRK | status, 677 port->membase + CDNS_UART_CR); 678 else { 679 if ((status & CDNS_UART_CR_STOPBRK) == 0) 680 writel(CDNS_UART_CR_STOPBRK | status, 681 port->membase + CDNS_UART_CR); 682 } 683 spin_unlock_irqrestore(&port->lock, flags); 684} 685 686/** 687 * cdns_uart_set_termios - termios operations, handling data length, parity, 688 * stop bits, flow control, baud rate 689 * @port: Handle to the uart port structure 690 * @termios: Handle to the input termios structure 691 * @old: Values of the previously saved termios structure 692 */ 693static void cdns_uart_set_termios(struct uart_port *port, 694 struct ktermios *termios, struct ktermios *old) 695{ 696 u32 cval = 0; 697 unsigned int baud, minbaud, maxbaud; 698 unsigned long flags; 699 unsigned int ctrl_reg, mode_reg; 700 701 spin_lock_irqsave(&port->lock, flags); 702 703 /* Disable the TX and RX to set baud rate */ 704 ctrl_reg = readl(port->membase + CDNS_UART_CR); 705 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 706 writel(ctrl_reg, port->membase + CDNS_UART_CR); 707 708 /* 709 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 710 * min and max baud should be calculated here based on port->uartclk. 711 * this way we get a valid baud and can safely call set_baud() 712 */ 713 minbaud = port->uartclk / 714 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 715 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 716 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 717 baud = cdns_uart_set_baud_rate(port, baud); 718 if (tty_termios_baud_rate(termios)) 719 tty_termios_encode_baud_rate(termios, baud, baud); 720 721 /* Update the per-port timeout. */ 722 uart_update_timeout(port, termios->c_cflag, baud); 723 724 /* Set TX/RX Reset */ 725 ctrl_reg = readl(port->membase + CDNS_UART_CR); 726 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 727 writel(ctrl_reg, port->membase + CDNS_UART_CR); 728 729 while (readl(port->membase + CDNS_UART_CR) & 730 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 731 cpu_relax(); 732 733 /* 734 * Clear the RX disable and TX disable bits and then set the TX enable 735 * bit and RX enable bit to enable the transmitter and receiver. 736 */ 737 ctrl_reg = readl(port->membase + CDNS_UART_CR); 738 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 739 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 740 writel(ctrl_reg, port->membase + CDNS_UART_CR); 741 742 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 743 744 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 745 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 746 port->ignore_status_mask = 0; 747 748 if (termios->c_iflag & INPCK) 749 port->read_status_mask |= CDNS_UART_IXR_PARITY | 750 CDNS_UART_IXR_FRAMING; 751 752 if (termios->c_iflag & IGNPAR) 753 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 754 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 755 756 /* ignore all characters if CREAD is not set */ 757 if ((termios->c_cflag & CREAD) == 0) 758 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 759 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 760 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 761 762 mode_reg = readl(port->membase + CDNS_UART_MR); 763 764 /* Handling Data Size */ 765 switch (termios->c_cflag & CSIZE) { 766 case CS6: 767 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 768 break; 769 case CS7: 770 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 771 break; 772 default: 773 case CS8: 774 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 775 termios->c_cflag &= ~CSIZE; 776 termios->c_cflag |= CS8; 777 break; 778 } 779 780 /* Handling Parity and Stop Bits length */ 781 if (termios->c_cflag & CSTOPB) 782 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 783 else 784 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 785 786 if (termios->c_cflag & PARENB) { 787 /* Mark or Space parity */ 788 if (termios->c_cflag & CMSPAR) { 789 if (termios->c_cflag & PARODD) 790 cval |= CDNS_UART_MR_PARITY_MARK; 791 else 792 cval |= CDNS_UART_MR_PARITY_SPACE; 793 } else { 794 if (termios->c_cflag & PARODD) 795 cval |= CDNS_UART_MR_PARITY_ODD; 796 else 797 cval |= CDNS_UART_MR_PARITY_EVEN; 798 } 799 } else { 800 cval |= CDNS_UART_MR_PARITY_NONE; 801 } 802 cval |= mode_reg & 1; 803 writel(cval, port->membase + CDNS_UART_MR); 804 805 cval = readl(port->membase + CDNS_UART_MODEMCR); 806 if (termios->c_cflag & CRTSCTS) 807 cval |= CDNS_UART_MODEMCR_FCM; 808 else 809 cval &= ~CDNS_UART_MODEMCR_FCM; 810 writel(cval, port->membase + CDNS_UART_MODEMCR); 811 812 spin_unlock_irqrestore(&port->lock, flags); 813} 814 815/** 816 * cdns_uart_startup - Called when an application opens a cdns_uart port 817 * @port: Handle to the uart port structure 818 * 819 * Return: 0 on success, negative errno otherwise 820 */ 821static int cdns_uart_startup(struct uart_port *port) 822{ 823 struct cdns_uart *cdns_uart = port->private_data; 824 bool is_brk_support; 825 int ret; 826 unsigned long flags; 827 unsigned int status = 0; 828 829 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 830 831 spin_lock_irqsave(&port->lock, flags); 832 833 /* Disable the TX and RX */ 834 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 835 port->membase + CDNS_UART_CR); 836 837 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 838 * no break chars. 839 */ 840 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 841 port->membase + CDNS_UART_CR); 842 843 while (readl(port->membase + CDNS_UART_CR) & 844 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 845 cpu_relax(); 846 847 /* 848 * Clear the RX disable bit and then set the RX enable bit to enable 849 * the receiver. 850 */ 851 status = readl(port->membase + CDNS_UART_CR); 852 status &= ~CDNS_UART_CR_RX_DIS; 853 status |= CDNS_UART_CR_RX_EN; 854 writel(status, port->membase + CDNS_UART_CR); 855 856 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 857 * no parity. 858 */ 859 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 860 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 861 port->membase + CDNS_UART_MR); 862 863 /* 864 * Set the RX FIFO Trigger level to use most of the FIFO, but it 865 * can be tuned with a module parameter 866 */ 867 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 868 869 /* 870 * Receive Timeout register is enabled but it 871 * can be tuned with a module parameter 872 */ 873 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 874 875 /* Clear out any pending interrupts before enabling them */ 876 writel(readl(port->membase + CDNS_UART_ISR), 877 port->membase + CDNS_UART_ISR); 878 879 spin_unlock_irqrestore(&port->lock, flags); 880 881 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 882 if (ret) { 883 dev_err(port->dev, "request_irq '%d' failed with %d\n", 884 port->irq, ret); 885 return ret; 886 } 887 888 /* Set the Interrupt Registers with desired interrupts */ 889 if (is_brk_support) 890 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 891 port->membase + CDNS_UART_IER); 892 else 893 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 894 895 return 0; 896} 897 898/** 899 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 900 * @port: Handle to the uart port structure 901 */ 902static void cdns_uart_shutdown(struct uart_port *port) 903{ 904 int status; 905 unsigned long flags; 906 907 spin_lock_irqsave(&port->lock, flags); 908 909 /* Disable interrupts */ 910 status = readl(port->membase + CDNS_UART_IMR); 911 writel(status, port->membase + CDNS_UART_IDR); 912 writel(0xffffffff, port->membase + CDNS_UART_ISR); 913 914 /* Disable the TX and RX */ 915 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 916 port->membase + CDNS_UART_CR); 917 918 spin_unlock_irqrestore(&port->lock, flags); 919 920 free_irq(port->irq, port); 921} 922 923/** 924 * cdns_uart_type - Set UART type to cdns_uart port 925 * @port: Handle to the uart port structure 926 * 927 * Return: string on success, NULL otherwise 928 */ 929static const char *cdns_uart_type(struct uart_port *port) 930{ 931 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 932} 933 934/** 935 * cdns_uart_verify_port - Verify the port params 936 * @port: Handle to the uart port structure 937 * @ser: Handle to the structure whose members are compared 938 * 939 * Return: 0 on success, negative errno otherwise. 940 */ 941static int cdns_uart_verify_port(struct uart_port *port, 942 struct serial_struct *ser) 943{ 944 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 945 return -EINVAL; 946 if (port->irq != ser->irq) 947 return -EINVAL; 948 if (ser->io_type != UPIO_MEM) 949 return -EINVAL; 950 if (port->iobase != ser->port) 951 return -EINVAL; 952 if (ser->hub6 != 0) 953 return -EINVAL; 954 return 0; 955} 956 957/** 958 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 959 * called when the driver adds a cdns_uart port via 960 * uart_add_one_port() 961 * @port: Handle to the uart port structure 962 * 963 * Return: 0 on success, negative errno otherwise. 964 */ 965static int cdns_uart_request_port(struct uart_port *port) 966{ 967 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 968 CDNS_UART_NAME)) { 969 return -ENOMEM; 970 } 971 972 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 973 if (!port->membase) { 974 dev_err(port->dev, "Unable to map registers\n"); 975 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 976 return -ENOMEM; 977 } 978 return 0; 979} 980 981/** 982 * cdns_uart_release_port - Release UART port 983 * @port: Handle to the uart port structure 984 * 985 * Release the memory region attached to a cdns_uart port. Called when the 986 * driver removes a cdns_uart port via uart_remove_one_port(). 987 */ 988static void cdns_uart_release_port(struct uart_port *port) 989{ 990 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 991 iounmap(port->membase); 992 port->membase = NULL; 993} 994 995/** 996 * cdns_uart_config_port - Configure UART port 997 * @port: Handle to the uart port structure 998 * @flags: If any 999 */ 1000static void cdns_uart_config_port(struct uart_port *port, int flags) 1001{ 1002 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 1003 port->type = PORT_XUARTPS; 1004} 1005 1006/** 1007 * cdns_uart_get_mctrl - Get the modem control state 1008 * @port: Handle to the uart port structure 1009 * 1010 * Return: the modem control state 1011 */ 1012static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 1013{ 1014 u32 val; 1015 unsigned int mctrl = 0; 1016 struct cdns_uart *cdns_uart_data = port->private_data; 1017 1018 if (cdns_uart_data->cts_override) 1019 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 1020 1021 val = readl(port->membase + CDNS_UART_MODEMSR); 1022 if (val & CDNS_UART_MODEMSR_CTS) 1023 mctrl |= TIOCM_CTS; 1024 if (val & CDNS_UART_MODEMSR_DSR) 1025 mctrl |= TIOCM_DSR; 1026 if (val & CDNS_UART_MODEMSR_RI) 1027 mctrl |= TIOCM_RNG; 1028 if (val & CDNS_UART_MODEMSR_DCD) 1029 mctrl |= TIOCM_CAR; 1030 1031 return mctrl; 1032} 1033 1034static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1035{ 1036 u32 val; 1037 u32 mode_reg; 1038 struct cdns_uart *cdns_uart_data = port->private_data; 1039 1040 if (cdns_uart_data->cts_override) 1041 return; 1042 1043 val = readl(port->membase + CDNS_UART_MODEMCR); 1044 mode_reg = readl(port->membase + CDNS_UART_MR); 1045 1046 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1047 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1048 1049 if (mctrl & TIOCM_RTS) 1050 val |= CDNS_UART_MODEMCR_RTS; 1051 if (mctrl & TIOCM_DTR) 1052 val |= CDNS_UART_MODEMCR_DTR; 1053 if (mctrl & TIOCM_LOOP) 1054 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1055 else 1056 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1057 1058 writel(val, port->membase + CDNS_UART_MODEMCR); 1059 writel(mode_reg, port->membase + CDNS_UART_MR); 1060} 1061 1062#ifdef CONFIG_CONSOLE_POLL 1063static int cdns_uart_poll_get_char(struct uart_port *port) 1064{ 1065 int c; 1066 unsigned long flags; 1067 1068 spin_lock_irqsave(&port->lock, flags); 1069 1070 /* Check if FIFO is empty */ 1071 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1072 c = NO_POLL_CHAR; 1073 else /* Read a character */ 1074 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1075 1076 spin_unlock_irqrestore(&port->lock, flags); 1077 1078 return c; 1079} 1080 1081static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1082{ 1083 unsigned long flags; 1084 1085 spin_lock_irqsave(&port->lock, flags); 1086 1087 /* Wait until FIFO is empty */ 1088 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1089 cpu_relax(); 1090 1091 /* Write a character */ 1092 writel(c, port->membase + CDNS_UART_FIFO); 1093 1094 /* Wait until FIFO is empty */ 1095 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1096 cpu_relax(); 1097 1098 spin_unlock_irqrestore(&port->lock, flags); 1099} 1100#endif 1101 1102static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1103 unsigned int oldstate) 1104{ 1105 switch (state) { 1106 case UART_PM_STATE_OFF: 1107 pm_runtime_mark_last_busy(port->dev); 1108 pm_runtime_put_autosuspend(port->dev); 1109 break; 1110 default: 1111 pm_runtime_get_sync(port->dev); 1112 break; 1113 } 1114} 1115 1116static const struct uart_ops cdns_uart_ops = { 1117 .set_mctrl = cdns_uart_set_mctrl, 1118 .get_mctrl = cdns_uart_get_mctrl, 1119 .start_tx = cdns_uart_start_tx, 1120 .stop_tx = cdns_uart_stop_tx, 1121 .stop_rx = cdns_uart_stop_rx, 1122 .tx_empty = cdns_uart_tx_empty, 1123 .break_ctl = cdns_uart_break_ctl, 1124 .set_termios = cdns_uart_set_termios, 1125 .startup = cdns_uart_startup, 1126 .shutdown = cdns_uart_shutdown, 1127 .pm = cdns_uart_pm, 1128 .type = cdns_uart_type, 1129 .verify_port = cdns_uart_verify_port, 1130 .request_port = cdns_uart_request_port, 1131 .release_port = cdns_uart_release_port, 1132 .config_port = cdns_uart_config_port, 1133#ifdef CONFIG_CONSOLE_POLL 1134 .poll_get_char = cdns_uart_poll_get_char, 1135 .poll_put_char = cdns_uart_poll_put_char, 1136#endif 1137}; 1138 1139static struct uart_driver cdns_uart_uart_driver; 1140 1141#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1142/** 1143 * cdns_uart_console_putchar - write the character to the FIFO buffer 1144 * @port: Handle to the uart port structure 1145 * @ch: Character to be written 1146 */ 1147static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1148{ 1149 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL) 1150 cpu_relax(); 1151 writel(ch, port->membase + CDNS_UART_FIFO); 1152} 1153 1154static void cdns_early_write(struct console *con, const char *s, 1155 unsigned n) 1156{ 1157 struct earlycon_device *dev = con->data; 1158 1159 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1160} 1161 1162static int __init cdns_early_console_setup(struct earlycon_device *device, 1163 const char *opt) 1164{ 1165 struct uart_port *port = &device->port; 1166 1167 if (!port->membase) 1168 return -ENODEV; 1169 1170 /* initialise control register */ 1171 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1172 port->membase + CDNS_UART_CR); 1173 1174 /* only set baud if specified on command line - otherwise 1175 * assume it has been initialized by a boot loader. 1176 */ 1177 if (port->uartclk && device->baud) { 1178 u32 cd = 0, bdiv = 0; 1179 u32 mr; 1180 int div8; 1181 1182 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1183 &bdiv, &cd, &div8); 1184 mr = CDNS_UART_MR_PARITY_NONE; 1185 if (div8) 1186 mr |= CDNS_UART_MR_CLKSEL; 1187 1188 writel(mr, port->membase + CDNS_UART_MR); 1189 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1190 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1191 } 1192 1193 device->con->write = cdns_early_write; 1194 1195 return 0; 1196} 1197OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1198OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1199OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1200OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1201 1202 1203/* Static pointer to console port */ 1204static struct uart_port *console_port; 1205 1206/** 1207 * cdns_uart_console_write - perform write operation 1208 * @co: Console handle 1209 * @s: Pointer to character array 1210 * @count: No of characters 1211 */ 1212static void cdns_uart_console_write(struct console *co, const char *s, 1213 unsigned int count) 1214{ 1215 struct uart_port *port = console_port; 1216 unsigned long flags = 0; 1217 unsigned int imr, ctrl; 1218 int locked = 1; 1219 1220 if (port->sysrq) 1221 locked = 0; 1222 else if (oops_in_progress) 1223 locked = spin_trylock_irqsave(&port->lock, flags); 1224 else 1225 spin_lock_irqsave(&port->lock, flags); 1226 1227 /* save and disable interrupt */ 1228 imr = readl(port->membase + CDNS_UART_IMR); 1229 writel(imr, port->membase + CDNS_UART_IDR); 1230 1231 /* 1232 * Make sure that the tx part is enabled. Set the TX enable bit and 1233 * clear the TX disable bit to enable the transmitter. 1234 */ 1235 ctrl = readl(port->membase + CDNS_UART_CR); 1236 ctrl &= ~CDNS_UART_CR_TX_DIS; 1237 ctrl |= CDNS_UART_CR_TX_EN; 1238 writel(ctrl, port->membase + CDNS_UART_CR); 1239 1240 uart_console_write(port, s, count, cdns_uart_console_putchar); 1241 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1242 cpu_relax(); 1243 1244 /* restore interrupt state */ 1245 writel(imr, port->membase + CDNS_UART_IER); 1246 1247 if (locked) 1248 spin_unlock_irqrestore(&port->lock, flags); 1249} 1250 1251/** 1252 * cdns_uart_console_setup - Initialize the uart to default config 1253 * @co: Console handle 1254 * @options: Initial settings of uart 1255 * 1256 * Return: 0 on success, negative errno otherwise. 1257 */ 1258static int cdns_uart_console_setup(struct console *co, char *options) 1259{ 1260 struct uart_port *port = console_port; 1261 1262 int baud = 9600; 1263 int bits = 8; 1264 int parity = 'n'; 1265 int flow = 'n'; 1266 unsigned long time_out; 1267 1268 if (!port->membase) { 1269 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1270 co->index); 1271 return -ENODEV; 1272 } 1273 1274 if (options) 1275 uart_parse_options(options, &baud, &parity, &bits, &flow); 1276 1277 /* Wait for tx_empty before setting up the console */ 1278 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT); 1279 1280 while (time_before(jiffies, time_out) && 1281 cdns_uart_tx_empty(port) != TIOCSER_TEMT) 1282 cpu_relax(); 1283 1284 return uart_set_options(port, co, baud, parity, bits, flow); 1285} 1286 1287static struct console cdns_uart_console = { 1288 .name = CDNS_UART_TTY_NAME, 1289 .write = cdns_uart_console_write, 1290 .device = uart_console_device, 1291 .setup = cdns_uart_console_setup, 1292 .flags = CON_PRINTBUFFER, 1293 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1294 .data = &cdns_uart_uart_driver, 1295}; 1296#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1297 1298#ifdef CONFIG_PM_SLEEP 1299/** 1300 * cdns_uart_suspend - suspend event 1301 * @device: Pointer to the device structure 1302 * 1303 * Return: 0 1304 */ 1305static int cdns_uart_suspend(struct device *device) 1306{ 1307 struct uart_port *port = dev_get_drvdata(device); 1308 struct cdns_uart *cdns_uart = port->private_data; 1309 int may_wake; 1310 1311 may_wake = device_may_wakeup(device); 1312 1313 if (console_suspend_enabled && uart_console(port) && may_wake) { 1314 unsigned long flags = 0; 1315 1316 spin_lock_irqsave(&port->lock, flags); 1317 /* Empty the receive FIFO 1st before making changes */ 1318 while (!(readl(port->membase + CDNS_UART_SR) & 1319 CDNS_UART_SR_RXEMPTY)) 1320 readl(port->membase + CDNS_UART_FIFO); 1321 /* set RX trigger level to 1 */ 1322 writel(1, port->membase + CDNS_UART_RXWM); 1323 /* disable RX timeout interrups */ 1324 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1325 spin_unlock_irqrestore(&port->lock, flags); 1326 } 1327 1328 /* 1329 * Call the API provided in serial_core.c file which handles 1330 * the suspend. 1331 */ 1332 return uart_suspend_port(cdns_uart->cdns_uart_driver, port); 1333} 1334 1335/** 1336 * cdns_uart_resume - Resume after a previous suspend 1337 * @device: Pointer to the device structure 1338 * 1339 * Return: 0 1340 */ 1341static int cdns_uart_resume(struct device *device) 1342{ 1343 struct uart_port *port = dev_get_drvdata(device); 1344 struct cdns_uart *cdns_uart = port->private_data; 1345 unsigned long flags = 0; 1346 u32 ctrl_reg; 1347 int may_wake; 1348 1349 may_wake = device_may_wakeup(device); 1350 1351 if (console_suspend_enabled && uart_console(port) && !may_wake) { 1352 clk_enable(cdns_uart->pclk); 1353 clk_enable(cdns_uart->uartclk); 1354 1355 spin_lock_irqsave(&port->lock, flags); 1356 1357 /* Set TX/RX Reset */ 1358 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1359 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1360 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1361 while (readl(port->membase + CDNS_UART_CR) & 1362 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1363 cpu_relax(); 1364 1365 /* restore rx timeout value */ 1366 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1367 /* Enable Tx/Rx */ 1368 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1369 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1370 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1371 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1372 1373 clk_disable(cdns_uart->uartclk); 1374 clk_disable(cdns_uart->pclk); 1375 spin_unlock_irqrestore(&port->lock, flags); 1376 } else { 1377 spin_lock_irqsave(&port->lock, flags); 1378 /* restore original rx trigger level */ 1379 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1380 /* enable RX timeout interrupt */ 1381 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1382 spin_unlock_irqrestore(&port->lock, flags); 1383 } 1384 1385 return uart_resume_port(cdns_uart->cdns_uart_driver, port); 1386} 1387#endif /* ! CONFIG_PM_SLEEP */ 1388static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1389{ 1390 struct uart_port *port = dev_get_drvdata(dev); 1391 struct cdns_uart *cdns_uart = port->private_data; 1392 1393 clk_disable(cdns_uart->uartclk); 1394 clk_disable(cdns_uart->pclk); 1395 return 0; 1396}; 1397 1398static int __maybe_unused cdns_runtime_resume(struct device *dev) 1399{ 1400 struct uart_port *port = dev_get_drvdata(dev); 1401 struct cdns_uart *cdns_uart = port->private_data; 1402 1403 clk_enable(cdns_uart->pclk); 1404 clk_enable(cdns_uart->uartclk); 1405 return 0; 1406}; 1407 1408static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1409 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1410 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1411 cdns_runtime_resume, NULL) 1412}; 1413 1414static const struct cdns_platform_data zynqmp_uart_def = { 1415 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1416 1417/* Match table for of_platform binding */ 1418static const struct of_device_id cdns_uart_of_match[] = { 1419 { .compatible = "xlnx,xuartps", }, 1420 { .compatible = "cdns,uart-r1p8", }, 1421 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1422 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1423 {} 1424}; 1425MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1426 1427/* Temporary variable for storing number of instances */ 1428static int instances; 1429 1430/** 1431 * cdns_uart_probe - Platform driver probe 1432 * @pdev: Pointer to the platform device structure 1433 * 1434 * Return: 0 on success, negative errno otherwise 1435 */ 1436static int cdns_uart_probe(struct platform_device *pdev) 1437{ 1438 int rc, id, irq; 1439 struct uart_port *port; 1440 struct resource *res; 1441 struct cdns_uart *cdns_uart_data; 1442 const struct of_device_id *match; 1443 1444 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1445 GFP_KERNEL); 1446 if (!cdns_uart_data) 1447 return -ENOMEM; 1448 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 1449 if (!port) 1450 return -ENOMEM; 1451 1452 /* Look for a serialN alias */ 1453 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1454 if (id < 0) 1455 id = 0; 1456 1457 if (id >= CDNS_UART_NR_PORTS) { 1458 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1459 return -ENODEV; 1460 } 1461 1462 if (!cdns_uart_uart_driver.state) { 1463 cdns_uart_uart_driver.owner = THIS_MODULE; 1464 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME; 1465 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME; 1466 cdns_uart_uart_driver.major = CDNS_UART_MAJOR; 1467 cdns_uart_uart_driver.minor = CDNS_UART_MINOR; 1468 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS; 1469#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1470 cdns_uart_uart_driver.cons = &cdns_uart_console; 1471#endif 1472 1473 rc = uart_register_driver(&cdns_uart_uart_driver); 1474 if (rc < 0) { 1475 dev_err(&pdev->dev, "Failed to register driver\n"); 1476 return rc; 1477 } 1478 } 1479 1480 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver; 1481 1482 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1483 if (match && match->data) { 1484 const struct cdns_platform_data *data = match->data; 1485 1486 cdns_uart_data->quirks = data->quirks; 1487 } 1488 1489 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1490 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) { 1491 rc = PTR_ERR(cdns_uart_data->pclk); 1492 goto err_out_unregister_driver; 1493 } 1494 1495 if (IS_ERR(cdns_uart_data->pclk)) { 1496 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1497 if (IS_ERR(cdns_uart_data->pclk)) { 1498 rc = PTR_ERR(cdns_uart_data->pclk); 1499 goto err_out_unregister_driver; 1500 } 1501 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1502 } 1503 1504 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1505 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) { 1506 rc = PTR_ERR(cdns_uart_data->uartclk); 1507 goto err_out_unregister_driver; 1508 } 1509 1510 if (IS_ERR(cdns_uart_data->uartclk)) { 1511 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1512 if (IS_ERR(cdns_uart_data->uartclk)) { 1513 rc = PTR_ERR(cdns_uart_data->uartclk); 1514 goto err_out_unregister_driver; 1515 } 1516 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1517 } 1518 1519 rc = clk_prepare_enable(cdns_uart_data->pclk); 1520 if (rc) { 1521 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1522 goto err_out_unregister_driver; 1523 } 1524 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1525 if (rc) { 1526 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1527 goto err_out_clk_dis_pclk; 1528 } 1529 1530 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1531 if (!res) { 1532 rc = -ENODEV; 1533 goto err_out_clk_disable; 1534 } 1535 1536 irq = platform_get_irq(pdev, 0); 1537 if (irq <= 0) { 1538 rc = -ENXIO; 1539 goto err_out_clk_disable; 1540 } 1541 1542#ifdef CONFIG_COMMON_CLK 1543 cdns_uart_data->clk_rate_change_nb.notifier_call = 1544 cdns_uart_clk_notifier_cb; 1545 if (clk_notifier_register(cdns_uart_data->uartclk, 1546 &cdns_uart_data->clk_rate_change_nb)) 1547 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1548#endif 1549 1550 /* At this point, we've got an empty uart_port struct, initialize it */ 1551 spin_lock_init(&port->lock); 1552 port->type = PORT_UNKNOWN; 1553 port->iotype = UPIO_MEM32; 1554 port->flags = UPF_BOOT_AUTOCONF; 1555 port->ops = &cdns_uart_ops; 1556 port->fifosize = CDNS_UART_FIFO_SIZE; 1557 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE); 1558 port->line = id; 1559 1560 /* 1561 * Register the port. 1562 * This function also registers this device with the tty layer 1563 * and triggers invocation of the config_port() entry point. 1564 */ 1565 port->mapbase = res->start; 1566 port->irq = irq; 1567 port->dev = &pdev->dev; 1568 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1569 port->private_data = cdns_uart_data; 1570 cdns_uart_data->port = port; 1571 platform_set_drvdata(pdev, port); 1572 1573 pm_runtime_use_autosuspend(&pdev->dev); 1574 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1575 pm_runtime_set_active(&pdev->dev); 1576 pm_runtime_enable(&pdev->dev); 1577 device_init_wakeup(port->dev, true); 1578 1579#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1580 /* 1581 * If console hasn't been found yet try to assign this port 1582 * because it is required to be assigned for console setup function. 1583 * If register_console() don't assign value, then console_port pointer 1584 * is cleanup. 1585 */ 1586 if (!console_port) { 1587 cdns_uart_console.index = id; 1588 console_port = port; 1589 } 1590#endif 1591 1592 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1593 if (rc) { 1594 dev_err(&pdev->dev, 1595 "uart_add_one_port() failed; err=%i\n", rc); 1596 goto err_out_pm_disable; 1597 } 1598 1599#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1600 /* This is not port which is used for console that's why clean it up */ 1601 if (console_port == port && 1602 !(cdns_uart_uart_driver.cons->flags & CON_ENABLED)) { 1603 console_port = NULL; 1604 cdns_uart_console.index = -1; 1605 } 1606#endif 1607 1608 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node, 1609 "cts-override"); 1610 1611 instances++; 1612 1613 return 0; 1614 1615err_out_pm_disable: 1616 pm_runtime_disable(&pdev->dev); 1617 pm_runtime_set_suspended(&pdev->dev); 1618 pm_runtime_dont_use_autosuspend(&pdev->dev); 1619#ifdef CONFIG_COMMON_CLK 1620 clk_notifier_unregister(cdns_uart_data->uartclk, 1621 &cdns_uart_data->clk_rate_change_nb); 1622#endif 1623err_out_clk_disable: 1624 clk_disable_unprepare(cdns_uart_data->uartclk); 1625err_out_clk_dis_pclk: 1626 clk_disable_unprepare(cdns_uart_data->pclk); 1627err_out_unregister_driver: 1628 if (!instances) 1629 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1630 return rc; 1631} 1632 1633/** 1634 * cdns_uart_remove - called when the platform driver is unregistered 1635 * @pdev: Pointer to the platform device structure 1636 * 1637 * Return: 0 on success, negative errno otherwise 1638 */ 1639static int cdns_uart_remove(struct platform_device *pdev) 1640{ 1641 struct uart_port *port = platform_get_drvdata(pdev); 1642 struct cdns_uart *cdns_uart_data = port->private_data; 1643 int rc; 1644 1645 /* Remove the cdns_uart port from the serial core */ 1646#ifdef CONFIG_COMMON_CLK 1647 clk_notifier_unregister(cdns_uart_data->uartclk, 1648 &cdns_uart_data->clk_rate_change_nb); 1649#endif 1650 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port); 1651 port->mapbase = 0; 1652 clk_disable_unprepare(cdns_uart_data->uartclk); 1653 clk_disable_unprepare(cdns_uart_data->pclk); 1654 pm_runtime_disable(&pdev->dev); 1655 pm_runtime_set_suspended(&pdev->dev); 1656 pm_runtime_dont_use_autosuspend(&pdev->dev); 1657 device_init_wakeup(&pdev->dev, false); 1658 1659#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1660 if (console_port == port) 1661 console_port = NULL; 1662#endif 1663 1664 if (!--instances) 1665 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1666 return rc; 1667} 1668 1669static struct platform_driver cdns_uart_platform_driver = { 1670 .probe = cdns_uart_probe, 1671 .remove = cdns_uart_remove, 1672 .driver = { 1673 .name = CDNS_UART_NAME, 1674 .of_match_table = cdns_uart_of_match, 1675 .pm = &cdns_uart_dev_pm_ops, 1676 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART), 1677 }, 1678}; 1679 1680static int __init cdns_uart_init(void) 1681{ 1682 /* Register the platform driver */ 1683 return platform_driver_register(&cdns_uart_platform_driver); 1684} 1685 1686static void __exit cdns_uart_exit(void) 1687{ 1688 /* Unregister the platform driver */ 1689 platform_driver_unregister(&cdns_uart_platform_driver); 1690} 1691 1692arch_initcall(cdns_uart_init); 1693module_exit(cdns_uart_exit); 1694 1695MODULE_DESCRIPTION("Driver for Cadence UART"); 1696MODULE_AUTHOR("Xilinx Inc."); 1697MODULE_LICENSE("GPL"); 1698