1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Driver for NEC VR4100 series Serial Interface Unit. 4 * 5 * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org> 6 * 7 * Based on drivers/serial/8250.c, by Russell King. 8 */ 9 10#include <linux/console.h> 11#include <linux/errno.h> 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/ioport.h> 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/serial.h> 18#include <linux/serial_core.h> 19#include <linux/serial_reg.h> 20#include <linux/tty.h> 21#include <linux/tty_flip.h> 22 23#include <asm/io.h> 24#include <asm/vr41xx/siu.h> 25#include <asm/vr41xx/vr41xx.h> 26 27#define SIU_BAUD_BASE 1152000 28#define SIU_MAJOR 204 29#define SIU_MINOR_BASE 82 30 31#define RX_MAX_COUNT 256 32#define TX_MAX_COUNT 15 33 34#define SIUIRSEL 0x08 35 #define TMICMODE 0x20 36 #define TMICTX 0x10 37 #define IRMSEL 0x0c 38 #define IRMSEL_HP 0x08 39 #define IRMSEL_TEMIC 0x04 40 #define IRMSEL_SHARP 0x00 41 #define IRUSESEL 0x02 42 #define SIRSEL 0x01 43 44static struct uart_port siu_uart_ports[SIU_PORTS_MAX] = { 45 [0 ... SIU_PORTS_MAX-1] = { 46 .lock = __SPIN_LOCK_UNLOCKED(siu_uart_ports->lock), 47 .irq = 0, 48 }, 49}; 50 51#ifdef CONFIG_SERIAL_VR41XX_CONSOLE 52static uint8_t lsr_break_flag[SIU_PORTS_MAX]; 53#endif 54 55#define siu_read(port, offset) readb((port)->membase + (offset)) 56#define siu_write(port, offset, value) writeb((value), (port)->membase + (offset)) 57 58void vr41xx_select_siu_interface(siu_interface_t interface) 59{ 60 struct uart_port *port; 61 unsigned long flags; 62 uint8_t irsel; 63 64 port = &siu_uart_ports[0]; 65 66 spin_lock_irqsave(&port->lock, flags); 67 68 irsel = siu_read(port, SIUIRSEL); 69 if (interface == SIU_INTERFACE_IRDA) 70 irsel |= SIRSEL; 71 else 72 irsel &= ~SIRSEL; 73 siu_write(port, SIUIRSEL, irsel); 74 75 spin_unlock_irqrestore(&port->lock, flags); 76} 77EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface); 78 79void vr41xx_use_irda(irda_use_t use) 80{ 81 struct uart_port *port; 82 unsigned long flags; 83 uint8_t irsel; 84 85 port = &siu_uart_ports[0]; 86 87 spin_lock_irqsave(&port->lock, flags); 88 89 irsel = siu_read(port, SIUIRSEL); 90 if (use == FIR_USE_IRDA) 91 irsel |= IRUSESEL; 92 else 93 irsel &= ~IRUSESEL; 94 siu_write(port, SIUIRSEL, irsel); 95 96 spin_unlock_irqrestore(&port->lock, flags); 97} 98EXPORT_SYMBOL_GPL(vr41xx_use_irda); 99 100void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed) 101{ 102 struct uart_port *port; 103 unsigned long flags; 104 uint8_t irsel; 105 106 port = &siu_uart_ports[0]; 107 108 spin_lock_irqsave(&port->lock, flags); 109 110 irsel = siu_read(port, SIUIRSEL); 111 irsel &= ~(IRMSEL | TMICTX | TMICMODE); 112 switch (module) { 113 case SHARP_IRDA: 114 irsel |= IRMSEL_SHARP; 115 break; 116 case TEMIC_IRDA: 117 irsel |= IRMSEL_TEMIC | TMICMODE; 118 if (speed == IRDA_TX_4MBPS) 119 irsel |= TMICTX; 120 break; 121 case HP_IRDA: 122 irsel |= IRMSEL_HP; 123 break; 124 default: 125 break; 126 } 127 siu_write(port, SIUIRSEL, irsel); 128 129 spin_unlock_irqrestore(&port->lock, flags); 130} 131EXPORT_SYMBOL_GPL(vr41xx_select_irda_module); 132 133static inline void siu_clear_fifo(struct uart_port *port) 134{ 135 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO); 136 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 137 UART_FCR_CLEAR_XMIT); 138 siu_write(port, UART_FCR, 0); 139} 140 141static inline unsigned long siu_port_size(struct uart_port *port) 142{ 143 switch (port->type) { 144 case PORT_VR41XX_SIU: 145 return 11UL; 146 case PORT_VR41XX_DSIU: 147 return 8UL; 148 } 149 150 return 0; 151} 152 153static inline unsigned int siu_check_type(struct uart_port *port) 154{ 155 if (port->line == 0) 156 return PORT_VR41XX_SIU; 157 if (port->line == 1 && port->irq) 158 return PORT_VR41XX_DSIU; 159 160 return PORT_UNKNOWN; 161} 162 163static inline const char *siu_type_name(struct uart_port *port) 164{ 165 switch (port->type) { 166 case PORT_VR41XX_SIU: 167 return "SIU"; 168 case PORT_VR41XX_DSIU: 169 return "DSIU"; 170 } 171 172 return NULL; 173} 174 175static unsigned int siu_tx_empty(struct uart_port *port) 176{ 177 uint8_t lsr; 178 179 lsr = siu_read(port, UART_LSR); 180 if (lsr & UART_LSR_TEMT) 181 return TIOCSER_TEMT; 182 183 return 0; 184} 185 186static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl) 187{ 188 uint8_t mcr = 0; 189 190 if (mctrl & TIOCM_DTR) 191 mcr |= UART_MCR_DTR; 192 if (mctrl & TIOCM_RTS) 193 mcr |= UART_MCR_RTS; 194 if (mctrl & TIOCM_OUT1) 195 mcr |= UART_MCR_OUT1; 196 if (mctrl & TIOCM_OUT2) 197 mcr |= UART_MCR_OUT2; 198 if (mctrl & TIOCM_LOOP) 199 mcr |= UART_MCR_LOOP; 200 201 siu_write(port, UART_MCR, mcr); 202} 203 204static unsigned int siu_get_mctrl(struct uart_port *port) 205{ 206 uint8_t msr; 207 unsigned int mctrl = 0; 208 209 msr = siu_read(port, UART_MSR); 210 if (msr & UART_MSR_DCD) 211 mctrl |= TIOCM_CAR; 212 if (msr & UART_MSR_RI) 213 mctrl |= TIOCM_RNG; 214 if (msr & UART_MSR_DSR) 215 mctrl |= TIOCM_DSR; 216 if (msr & UART_MSR_CTS) 217 mctrl |= TIOCM_CTS; 218 219 return mctrl; 220} 221 222static void siu_stop_tx(struct uart_port *port) 223{ 224 unsigned long flags; 225 uint8_t ier; 226 227 spin_lock_irqsave(&port->lock, flags); 228 229 ier = siu_read(port, UART_IER); 230 ier &= ~UART_IER_THRI; 231 siu_write(port, UART_IER, ier); 232 233 spin_unlock_irqrestore(&port->lock, flags); 234} 235 236static void siu_start_tx(struct uart_port *port) 237{ 238 unsigned long flags; 239 uint8_t ier; 240 241 spin_lock_irqsave(&port->lock, flags); 242 243 ier = siu_read(port, UART_IER); 244 ier |= UART_IER_THRI; 245 siu_write(port, UART_IER, ier); 246 247 spin_unlock_irqrestore(&port->lock, flags); 248} 249 250static void siu_stop_rx(struct uart_port *port) 251{ 252 unsigned long flags; 253 uint8_t ier; 254 255 spin_lock_irqsave(&port->lock, flags); 256 257 ier = siu_read(port, UART_IER); 258 ier &= ~UART_IER_RLSI; 259 siu_write(port, UART_IER, ier); 260 261 port->read_status_mask &= ~UART_LSR_DR; 262 263 spin_unlock_irqrestore(&port->lock, flags); 264} 265 266static void siu_enable_ms(struct uart_port *port) 267{ 268 unsigned long flags; 269 uint8_t ier; 270 271 spin_lock_irqsave(&port->lock, flags); 272 273 ier = siu_read(port, UART_IER); 274 ier |= UART_IER_MSI; 275 siu_write(port, UART_IER, ier); 276 277 spin_unlock_irqrestore(&port->lock, flags); 278} 279 280static void siu_break_ctl(struct uart_port *port, int ctl) 281{ 282 unsigned long flags; 283 uint8_t lcr; 284 285 spin_lock_irqsave(&port->lock, flags); 286 287 lcr = siu_read(port, UART_LCR); 288 if (ctl == -1) 289 lcr |= UART_LCR_SBC; 290 else 291 lcr &= ~UART_LCR_SBC; 292 siu_write(port, UART_LCR, lcr); 293 294 spin_unlock_irqrestore(&port->lock, flags); 295} 296 297static inline void receive_chars(struct uart_port *port, uint8_t *status) 298{ 299 uint8_t lsr, ch; 300 char flag; 301 int max_count = RX_MAX_COUNT; 302 303 lsr = *status; 304 305 do { 306 ch = siu_read(port, UART_RX); 307 port->icount.rx++; 308 flag = TTY_NORMAL; 309 310#ifdef CONFIG_SERIAL_VR41XX_CONSOLE 311 lsr |= lsr_break_flag[port->line]; 312 lsr_break_flag[port->line] = 0; 313#endif 314 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE | 315 UART_LSR_PE | UART_LSR_OE))) { 316 if (lsr & UART_LSR_BI) { 317 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 318 port->icount.brk++; 319 320 if (uart_handle_break(port)) 321 goto ignore_char; 322 } 323 324 if (lsr & UART_LSR_FE) 325 port->icount.frame++; 326 if (lsr & UART_LSR_PE) 327 port->icount.parity++; 328 if (lsr & UART_LSR_OE) 329 port->icount.overrun++; 330 331 lsr &= port->read_status_mask; 332 if (lsr & UART_LSR_BI) 333 flag = TTY_BREAK; 334 if (lsr & UART_LSR_FE) 335 flag = TTY_FRAME; 336 if (lsr & UART_LSR_PE) 337 flag = TTY_PARITY; 338 } 339 340 if (uart_handle_sysrq_char(port, ch)) 341 goto ignore_char; 342 343 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); 344 345 ignore_char: 346 lsr = siu_read(port, UART_LSR); 347 } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); 348 349 tty_flip_buffer_push(&port->state->port); 350 351 *status = lsr; 352} 353 354static inline void check_modem_status(struct uart_port *port) 355{ 356 uint8_t msr; 357 358 msr = siu_read(port, UART_MSR); 359 if ((msr & UART_MSR_ANY_DELTA) == 0) 360 return; 361 if (msr & UART_MSR_DDCD) 362 uart_handle_dcd_change(port, msr & UART_MSR_DCD); 363 if (msr & UART_MSR_TERI) 364 port->icount.rng++; 365 if (msr & UART_MSR_DDSR) 366 port->icount.dsr++; 367 if (msr & UART_MSR_DCTS) 368 uart_handle_cts_change(port, msr & UART_MSR_CTS); 369 370 wake_up_interruptible(&port->state->port.delta_msr_wait); 371} 372 373static inline void transmit_chars(struct uart_port *port) 374{ 375 struct circ_buf *xmit; 376 int max_count = TX_MAX_COUNT; 377 378 xmit = &port->state->xmit; 379 380 if (port->x_char) { 381 siu_write(port, UART_TX, port->x_char); 382 port->icount.tx++; 383 port->x_char = 0; 384 return; 385 } 386 387 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 388 siu_stop_tx(port); 389 return; 390 } 391 392 do { 393 siu_write(port, UART_TX, xmit->buf[xmit->tail]); 394 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 395 port->icount.tx++; 396 if (uart_circ_empty(xmit)) 397 break; 398 } while (max_count-- > 0); 399 400 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 401 uart_write_wakeup(port); 402 403 if (uart_circ_empty(xmit)) 404 siu_stop_tx(port); 405} 406 407static irqreturn_t siu_interrupt(int irq, void *dev_id) 408{ 409 struct uart_port *port; 410 uint8_t iir, lsr; 411 412 port = (struct uart_port *)dev_id; 413 414 iir = siu_read(port, UART_IIR); 415 if (iir & UART_IIR_NO_INT) 416 return IRQ_NONE; 417 418 lsr = siu_read(port, UART_LSR); 419 if (lsr & UART_LSR_DR) 420 receive_chars(port, &lsr); 421 422 check_modem_status(port); 423 424 if (lsr & UART_LSR_THRE) 425 transmit_chars(port); 426 427 return IRQ_HANDLED; 428} 429 430static int siu_startup(struct uart_port *port) 431{ 432 int retval; 433 434 if (port->membase == NULL) 435 return -ENODEV; 436 437 siu_clear_fifo(port); 438 439 (void)siu_read(port, UART_LSR); 440 (void)siu_read(port, UART_RX); 441 (void)siu_read(port, UART_IIR); 442 (void)siu_read(port, UART_MSR); 443 444 if (siu_read(port, UART_LSR) == 0xff) 445 return -ENODEV; 446 447 retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port); 448 if (retval) 449 return retval; 450 451 if (port->type == PORT_VR41XX_DSIU) 452 vr41xx_enable_dsiuint(DSIUINT_ALL); 453 454 siu_write(port, UART_LCR, UART_LCR_WLEN8); 455 456 spin_lock_irq(&port->lock); 457 siu_set_mctrl(port, port->mctrl); 458 spin_unlock_irq(&port->lock); 459 460 siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI); 461 462 (void)siu_read(port, UART_LSR); 463 (void)siu_read(port, UART_RX); 464 (void)siu_read(port, UART_IIR); 465 (void)siu_read(port, UART_MSR); 466 467 return 0; 468} 469 470static void siu_shutdown(struct uart_port *port) 471{ 472 unsigned long flags; 473 uint8_t lcr; 474 475 siu_write(port, UART_IER, 0); 476 477 spin_lock_irqsave(&port->lock, flags); 478 479 port->mctrl &= ~TIOCM_OUT2; 480 siu_set_mctrl(port, port->mctrl); 481 482 spin_unlock_irqrestore(&port->lock, flags); 483 484 lcr = siu_read(port, UART_LCR); 485 lcr &= ~UART_LCR_SBC; 486 siu_write(port, UART_LCR, lcr); 487 488 siu_clear_fifo(port); 489 490 (void)siu_read(port, UART_RX); 491 492 if (port->type == PORT_VR41XX_DSIU) 493 vr41xx_disable_dsiuint(DSIUINT_ALL); 494 495 free_irq(port->irq, port); 496} 497 498static void siu_set_termios(struct uart_port *port, struct ktermios *new, 499 struct ktermios *old) 500{ 501 tcflag_t c_cflag, c_iflag; 502 uint8_t lcr, fcr, ier; 503 unsigned int baud, quot; 504 unsigned long flags; 505 506 c_cflag = new->c_cflag; 507 switch (c_cflag & CSIZE) { 508 case CS5: 509 lcr = UART_LCR_WLEN5; 510 break; 511 case CS6: 512 lcr = UART_LCR_WLEN6; 513 break; 514 case CS7: 515 lcr = UART_LCR_WLEN7; 516 break; 517 default: 518 lcr = UART_LCR_WLEN8; 519 break; 520 } 521 522 if (c_cflag & CSTOPB) 523 lcr |= UART_LCR_STOP; 524 if (c_cflag & PARENB) 525 lcr |= UART_LCR_PARITY; 526 if ((c_cflag & PARODD) != PARODD) 527 lcr |= UART_LCR_EPAR; 528 if (c_cflag & CMSPAR) 529 lcr |= UART_LCR_SPAR; 530 531 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); 532 quot = uart_get_divisor(port, baud); 533 534 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; 535 536 spin_lock_irqsave(&port->lock, flags); 537 538 uart_update_timeout(port, c_cflag, baud); 539 540 c_iflag = new->c_iflag; 541 542 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; 543 if (c_iflag & INPCK) 544 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 545 if (c_iflag & (IGNBRK | BRKINT | PARMRK)) 546 port->read_status_mask |= UART_LSR_BI; 547 548 port->ignore_status_mask = 0; 549 if (c_iflag & IGNPAR) 550 port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE; 551 if (c_iflag & IGNBRK) { 552 port->ignore_status_mask |= UART_LSR_BI; 553 if (c_iflag & IGNPAR) 554 port->ignore_status_mask |= UART_LSR_OE; 555 } 556 557 if ((c_cflag & CREAD) == 0) 558 port->ignore_status_mask |= UART_LSR_DR; 559 560 ier = siu_read(port, UART_IER); 561 ier &= ~UART_IER_MSI; 562 if (UART_ENABLE_MS(port, c_cflag)) 563 ier |= UART_IER_MSI; 564 siu_write(port, UART_IER, ier); 565 566 siu_write(port, UART_LCR, lcr | UART_LCR_DLAB); 567 568 siu_write(port, UART_DLL, (uint8_t)quot); 569 siu_write(port, UART_DLM, (uint8_t)(quot >> 8)); 570 571 siu_write(port, UART_LCR, lcr); 572 573 siu_write(port, UART_FCR, fcr); 574 575 siu_set_mctrl(port, port->mctrl); 576 577 spin_unlock_irqrestore(&port->lock, flags); 578} 579 580static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 581{ 582 switch (state) { 583 case 0: 584 switch (port->type) { 585 case PORT_VR41XX_SIU: 586 vr41xx_supply_clock(SIU_CLOCK); 587 break; 588 case PORT_VR41XX_DSIU: 589 vr41xx_supply_clock(DSIU_CLOCK); 590 break; 591 } 592 break; 593 case 3: 594 switch (port->type) { 595 case PORT_VR41XX_SIU: 596 vr41xx_mask_clock(SIU_CLOCK); 597 break; 598 case PORT_VR41XX_DSIU: 599 vr41xx_mask_clock(DSIU_CLOCK); 600 break; 601 } 602 break; 603 } 604} 605 606static const char *siu_type(struct uart_port *port) 607{ 608 return siu_type_name(port); 609} 610 611static void siu_release_port(struct uart_port *port) 612{ 613 unsigned long size; 614 615 if (port->flags & UPF_IOREMAP) { 616 iounmap(port->membase); 617 port->membase = NULL; 618 } 619 620 size = siu_port_size(port); 621 release_mem_region(port->mapbase, size); 622} 623 624static int siu_request_port(struct uart_port *port) 625{ 626 unsigned long size; 627 struct resource *res; 628 629 size = siu_port_size(port); 630 res = request_mem_region(port->mapbase, size, siu_type_name(port)); 631 if (res == NULL) 632 return -EBUSY; 633 634 if (port->flags & UPF_IOREMAP) { 635 port->membase = ioremap(port->mapbase, size); 636 if (port->membase == NULL) { 637 release_resource(res); 638 return -ENOMEM; 639 } 640 } 641 642 return 0; 643} 644 645static void siu_config_port(struct uart_port *port, int flags) 646{ 647 if (flags & UART_CONFIG_TYPE) { 648 port->type = siu_check_type(port); 649 (void)siu_request_port(port); 650 } 651} 652 653static int siu_verify_port(struct uart_port *port, struct serial_struct *serial) 654{ 655 if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU) 656 return -EINVAL; 657 if (port->irq != serial->irq) 658 return -EINVAL; 659 if (port->iotype != serial->io_type) 660 return -EINVAL; 661 if (port->mapbase != (unsigned long)serial->iomem_base) 662 return -EINVAL; 663 664 return 0; 665} 666 667static const struct uart_ops siu_uart_ops = { 668 .tx_empty = siu_tx_empty, 669 .set_mctrl = siu_set_mctrl, 670 .get_mctrl = siu_get_mctrl, 671 .stop_tx = siu_stop_tx, 672 .start_tx = siu_start_tx, 673 .stop_rx = siu_stop_rx, 674 .enable_ms = siu_enable_ms, 675 .break_ctl = siu_break_ctl, 676 .startup = siu_startup, 677 .shutdown = siu_shutdown, 678 .set_termios = siu_set_termios, 679 .pm = siu_pm, 680 .type = siu_type, 681 .release_port = siu_release_port, 682 .request_port = siu_request_port, 683 .config_port = siu_config_port, 684 .verify_port = siu_verify_port, 685}; 686 687static int siu_init_ports(struct platform_device *pdev) 688{ 689 struct uart_port *port; 690 struct resource *res; 691 int *type = dev_get_platdata(&pdev->dev); 692 int i; 693 694 if (!type) 695 return 0; 696 697 port = siu_uart_ports; 698 for (i = 0; i < SIU_PORTS_MAX; i++) { 699 port->type = type[i]; 700 if (port->type == PORT_UNKNOWN) 701 continue; 702 port->irq = platform_get_irq(pdev, i); 703 port->uartclk = SIU_BAUD_BASE * 16; 704 port->fifosize = 16; 705 port->regshift = 0; 706 port->iotype = UPIO_MEM; 707 port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; 708 port->line = i; 709 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 710 port->mapbase = res->start; 711 port++; 712 } 713 714 return i; 715} 716 717#ifdef CONFIG_SERIAL_VR41XX_CONSOLE 718 719#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 720 721static void wait_for_xmitr(struct uart_port *port) 722{ 723 int timeout = 10000; 724 uint8_t lsr, msr; 725 726 do { 727 lsr = siu_read(port, UART_LSR); 728 if (lsr & UART_LSR_BI) 729 lsr_break_flag[port->line] = UART_LSR_BI; 730 731 if ((lsr & BOTH_EMPTY) == BOTH_EMPTY) 732 break; 733 } while (timeout-- > 0); 734 735 if (port->flags & UPF_CONS_FLOW) { 736 timeout = 1000000; 737 738 do { 739 msr = siu_read(port, UART_MSR); 740 if ((msr & UART_MSR_CTS) != 0) 741 break; 742 } while (timeout-- > 0); 743 } 744} 745 746static void siu_console_putchar(struct uart_port *port, int ch) 747{ 748 wait_for_xmitr(port); 749 siu_write(port, UART_TX, ch); 750} 751 752static void siu_console_write(struct console *con, const char *s, unsigned count) 753{ 754 struct uart_port *port; 755 uint8_t ier; 756 757 port = &siu_uart_ports[con->index]; 758 759 ier = siu_read(port, UART_IER); 760 siu_write(port, UART_IER, 0); 761 762 uart_console_write(port, s, count, siu_console_putchar); 763 764 wait_for_xmitr(port); 765 siu_write(port, UART_IER, ier); 766} 767 768static int __init siu_console_setup(struct console *con, char *options) 769{ 770 struct uart_port *port; 771 int baud = 9600; 772 int parity = 'n'; 773 int bits = 8; 774 int flow = 'n'; 775 776 if (con->index >= SIU_PORTS_MAX) 777 con->index = 0; 778 779 port = &siu_uart_ports[con->index]; 780 if (port->membase == NULL) { 781 if (port->mapbase == 0) 782 return -ENODEV; 783 port->membase = ioremap(port->mapbase, siu_port_size(port)); 784 } 785 786 if (port->type == PORT_VR41XX_SIU) 787 vr41xx_select_siu_interface(SIU_INTERFACE_RS232C); 788 789 if (options != NULL) 790 uart_parse_options(options, &baud, &parity, &bits, &flow); 791 792 return uart_set_options(port, con, baud, parity, bits, flow); 793} 794 795static struct uart_driver siu_uart_driver; 796 797static struct console siu_console = { 798 .name = "ttyVR", 799 .write = siu_console_write, 800 .device = uart_console_device, 801 .setup = siu_console_setup, 802 .flags = CON_PRINTBUFFER, 803 .index = -1, 804 .data = &siu_uart_driver, 805}; 806 807static int siu_console_init(void) 808{ 809 struct uart_port *port; 810 int i; 811 812 for (i = 0; i < SIU_PORTS_MAX; i++) { 813 port = &siu_uart_ports[i]; 814 port->ops = &siu_uart_ops; 815 } 816 817 register_console(&siu_console); 818 819 return 0; 820} 821 822console_initcall(siu_console_init); 823 824void __init vr41xx_siu_early_setup(struct uart_port *port) 825{ 826 if (port->type == PORT_UNKNOWN) 827 return; 828 829 siu_uart_ports[port->line].line = port->line; 830 siu_uart_ports[port->line].type = port->type; 831 siu_uart_ports[port->line].uartclk = SIU_BAUD_BASE * 16; 832 siu_uart_ports[port->line].mapbase = port->mapbase; 833 siu_uart_ports[port->line].ops = &siu_uart_ops; 834} 835 836#define SERIAL_VR41XX_CONSOLE &siu_console 837#else 838#define SERIAL_VR41XX_CONSOLE NULL 839#endif 840 841static struct uart_driver siu_uart_driver = { 842 .owner = THIS_MODULE, 843 .driver_name = "SIU", 844 .dev_name = "ttyVR", 845 .major = SIU_MAJOR, 846 .minor = SIU_MINOR_BASE, 847 .cons = SERIAL_VR41XX_CONSOLE, 848}; 849 850static int siu_probe(struct platform_device *dev) 851{ 852 struct uart_port *port; 853 int num, i, retval; 854 855 num = siu_init_ports(dev); 856 if (num <= 0) 857 return -ENODEV; 858 859 siu_uart_driver.nr = num; 860 retval = uart_register_driver(&siu_uart_driver); 861 if (retval) 862 return retval; 863 864 for (i = 0; i < num; i++) { 865 port = &siu_uart_ports[i]; 866 port->ops = &siu_uart_ops; 867 port->dev = &dev->dev; 868 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_VR41XX_CONSOLE); 869 870 retval = uart_add_one_port(&siu_uart_driver, port); 871 if (retval < 0) { 872 port->dev = NULL; 873 break; 874 } 875 } 876 877 if (i == 0 && retval < 0) { 878 uart_unregister_driver(&siu_uart_driver); 879 return retval; 880 } 881 882 return 0; 883} 884 885static int siu_remove(struct platform_device *dev) 886{ 887 struct uart_port *port; 888 int i; 889 890 for (i = 0; i < siu_uart_driver.nr; i++) { 891 port = &siu_uart_ports[i]; 892 if (port->dev == &dev->dev) { 893 uart_remove_one_port(&siu_uart_driver, port); 894 port->dev = NULL; 895 } 896 } 897 898 uart_unregister_driver(&siu_uart_driver); 899 900 return 0; 901} 902 903static int siu_suspend(struct platform_device *dev, pm_message_t state) 904{ 905 struct uart_port *port; 906 int i; 907 908 for (i = 0; i < siu_uart_driver.nr; i++) { 909 port = &siu_uart_ports[i]; 910 if ((port->type == PORT_VR41XX_SIU || 911 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev) 912 uart_suspend_port(&siu_uart_driver, port); 913 914 } 915 916 return 0; 917} 918 919static int siu_resume(struct platform_device *dev) 920{ 921 struct uart_port *port; 922 int i; 923 924 for (i = 0; i < siu_uart_driver.nr; i++) { 925 port = &siu_uart_ports[i]; 926 if ((port->type == PORT_VR41XX_SIU || 927 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev) 928 uart_resume_port(&siu_uart_driver, port); 929 } 930 931 return 0; 932} 933 934static struct platform_driver siu_device_driver = { 935 .probe = siu_probe, 936 .remove = siu_remove, 937 .suspend = siu_suspend, 938 .resume = siu_resume, 939 .driver = { 940 .name = "SIU", 941 }, 942}; 943 944module_platform_driver(siu_device_driver); 945 946MODULE_LICENSE("GPL"); 947MODULE_ALIAS("platform:SIU"); 948