18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 68c2ecf20Sopenharmony_ci * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com) 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * This is mainly a variation of 8250.c, credits go to authors mentioned 98c2ecf20Sopenharmony_ci * therein. In fact this driver should be merged into the generic 8250.c 108c2ecf20Sopenharmony_ci * infrastructure perhaps using a 8250_sparc.c module. 118c2ecf20Sopenharmony_ci * 128c2ecf20Sopenharmony_ci * Fixed to use tty_get_baud_rate(). 138c2ecf20Sopenharmony_ci * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 148c2ecf20Sopenharmony_ci * 158c2ecf20Sopenharmony_ci * Converted to new 2.5.x UART layer. 168c2ecf20Sopenharmony_ci * David S. Miller (davem@davemloft.net), 2002-Jul-29 178c2ecf20Sopenharmony_ci */ 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci#include <linux/module.h> 208c2ecf20Sopenharmony_ci#include <linux/kernel.h> 218c2ecf20Sopenharmony_ci#include <linux/spinlock.h> 228c2ecf20Sopenharmony_ci#include <linux/errno.h> 238c2ecf20Sopenharmony_ci#include <linux/tty.h> 248c2ecf20Sopenharmony_ci#include <linux/tty_flip.h> 258c2ecf20Sopenharmony_ci#include <linux/major.h> 268c2ecf20Sopenharmony_ci#include <linux/string.h> 278c2ecf20Sopenharmony_ci#include <linux/ptrace.h> 288c2ecf20Sopenharmony_ci#include <linux/ioport.h> 298c2ecf20Sopenharmony_ci#include <linux/circ_buf.h> 308c2ecf20Sopenharmony_ci#include <linux/serial.h> 318c2ecf20Sopenharmony_ci#include <linux/sysrq.h> 328c2ecf20Sopenharmony_ci#include <linux/console.h> 338c2ecf20Sopenharmony_ci#include <linux/slab.h> 348c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 358c2ecf20Sopenharmony_ci#include <linux/serio.h> 368c2ecf20Sopenharmony_ci#endif 378c2ecf20Sopenharmony_ci#include <linux/serial_reg.h> 388c2ecf20Sopenharmony_ci#include <linux/init.h> 398c2ecf20Sopenharmony_ci#include <linux/delay.h> 408c2ecf20Sopenharmony_ci#include <linux/of_device.h> 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci#include <asm/io.h> 438c2ecf20Sopenharmony_ci#include <asm/irq.h> 448c2ecf20Sopenharmony_ci#include <asm/prom.h> 458c2ecf20Sopenharmony_ci#include <asm/setup.h> 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci#include <linux/serial_core.h> 488c2ecf20Sopenharmony_ci#include <linux/sunserialcore.h> 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/* We are on a NS PC87303 clocked with 24.0 MHz, which results 518c2ecf20Sopenharmony_ci * in a UART clock of 1.8462 MHz. 528c2ecf20Sopenharmony_ci */ 538c2ecf20Sopenharmony_ci#define SU_BASE_BAUD (1846200 / 16) 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_cienum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT }; 568c2ecf20Sopenharmony_cistatic char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" }; 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_cistruct serial_uart_config { 598c2ecf20Sopenharmony_ci char *name; 608c2ecf20Sopenharmony_ci int dfl_xmit_fifo_size; 618c2ecf20Sopenharmony_ci int flags; 628c2ecf20Sopenharmony_ci}; 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci/* 658c2ecf20Sopenharmony_ci * Here we define the default xmit fifo size used for each type of UART. 668c2ecf20Sopenharmony_ci */ 678c2ecf20Sopenharmony_cistatic const struct serial_uart_config uart_config[] = { 688c2ecf20Sopenharmony_ci { "unknown", 1, 0 }, 698c2ecf20Sopenharmony_ci { "8250", 1, 0 }, 708c2ecf20Sopenharmony_ci { "16450", 1, 0 }, 718c2ecf20Sopenharmony_ci { "16550", 1, 0 }, 728c2ecf20Sopenharmony_ci { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, 738c2ecf20Sopenharmony_ci { "Cirrus", 1, 0 }, 748c2ecf20Sopenharmony_ci { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, 758c2ecf20Sopenharmony_ci { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 768c2ecf20Sopenharmony_ci { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO }, 778c2ecf20Sopenharmony_ci { "Startech", 1, 0 }, 788c2ecf20Sopenharmony_ci { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO }, 798c2ecf20Sopenharmony_ci { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 808c2ecf20Sopenharmony_ci { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 818c2ecf20Sopenharmony_ci { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO } 828c2ecf20Sopenharmony_ci}; 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_cistruct uart_sunsu_port { 858c2ecf20Sopenharmony_ci struct uart_port port; 868c2ecf20Sopenharmony_ci unsigned char acr; 878c2ecf20Sopenharmony_ci unsigned char ier; 888c2ecf20Sopenharmony_ci unsigned short rev; 898c2ecf20Sopenharmony_ci unsigned char lcr; 908c2ecf20Sopenharmony_ci unsigned int lsr_break_flag; 918c2ecf20Sopenharmony_ci unsigned int cflag; 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci /* Probing information. */ 948c2ecf20Sopenharmony_ci enum su_type su_type; 958c2ecf20Sopenharmony_ci unsigned int type_probed; /* XXX Stupid */ 968c2ecf20Sopenharmony_ci unsigned long reg_size; 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 998c2ecf20Sopenharmony_ci struct serio serio; 1008c2ecf20Sopenharmony_ci int serio_open; 1018c2ecf20Sopenharmony_ci#endif 1028c2ecf20Sopenharmony_ci}; 1038c2ecf20Sopenharmony_ci 1048c2ecf20Sopenharmony_cistatic unsigned int serial_in(struct uart_sunsu_port *up, int offset) 1058c2ecf20Sopenharmony_ci{ 1068c2ecf20Sopenharmony_ci offset <<= up->port.regshift; 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci switch (up->port.iotype) { 1098c2ecf20Sopenharmony_ci case UPIO_HUB6: 1108c2ecf20Sopenharmony_ci outb(up->port.hub6 - 1 + offset, up->port.iobase); 1118c2ecf20Sopenharmony_ci return inb(up->port.iobase + 1); 1128c2ecf20Sopenharmony_ci 1138c2ecf20Sopenharmony_ci case UPIO_MEM: 1148c2ecf20Sopenharmony_ci return readb(up->port.membase + offset); 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_ci default: 1178c2ecf20Sopenharmony_ci return inb(up->port.iobase + offset); 1188c2ecf20Sopenharmony_ci } 1198c2ecf20Sopenharmony_ci} 1208c2ecf20Sopenharmony_ci 1218c2ecf20Sopenharmony_cistatic void serial_out(struct uart_sunsu_port *up, int offset, int value) 1228c2ecf20Sopenharmony_ci{ 1238c2ecf20Sopenharmony_ci#ifndef CONFIG_SPARC64 1248c2ecf20Sopenharmony_ci /* 1258c2ecf20Sopenharmony_ci * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are 1268c2ecf20Sopenharmony_ci * connected with a gate then go to SlavIO. When IRQ4 goes tristated 1278c2ecf20Sopenharmony_ci * gate outputs a logical one. Since we use level triggered interrupts 1288c2ecf20Sopenharmony_ci * we have lockup and watchdog reset. We cannot mask IRQ because 1298c2ecf20Sopenharmony_ci * keyboard shares IRQ with us (Word has it as Bob Smelik's design). 1308c2ecf20Sopenharmony_ci * This problem is similar to what Alpha people suffer, see serial.c. 1318c2ecf20Sopenharmony_ci */ 1328c2ecf20Sopenharmony_ci if (offset == UART_MCR) 1338c2ecf20Sopenharmony_ci value |= UART_MCR_OUT2; 1348c2ecf20Sopenharmony_ci#endif 1358c2ecf20Sopenharmony_ci offset <<= up->port.regshift; 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ci switch (up->port.iotype) { 1388c2ecf20Sopenharmony_ci case UPIO_HUB6: 1398c2ecf20Sopenharmony_ci outb(up->port.hub6 - 1 + offset, up->port.iobase); 1408c2ecf20Sopenharmony_ci outb(value, up->port.iobase + 1); 1418c2ecf20Sopenharmony_ci break; 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_ci case UPIO_MEM: 1448c2ecf20Sopenharmony_ci writeb(value, up->port.membase + offset); 1458c2ecf20Sopenharmony_ci break; 1468c2ecf20Sopenharmony_ci 1478c2ecf20Sopenharmony_ci default: 1488c2ecf20Sopenharmony_ci outb(value, up->port.iobase + offset); 1498c2ecf20Sopenharmony_ci } 1508c2ecf20Sopenharmony_ci} 1518c2ecf20Sopenharmony_ci 1528c2ecf20Sopenharmony_ci/* 1538c2ecf20Sopenharmony_ci * We used to support using pause I/O for certain machines. We 1548c2ecf20Sopenharmony_ci * haven't supported this for a while, but just in case it's badly 1558c2ecf20Sopenharmony_ci * needed for certain old 386 machines, I've left these #define's 1568c2ecf20Sopenharmony_ci * in.... 1578c2ecf20Sopenharmony_ci */ 1588c2ecf20Sopenharmony_ci#define serial_inp(up, offset) serial_in(up, offset) 1598c2ecf20Sopenharmony_ci#define serial_outp(up, offset, value) serial_out(up, offset, value) 1608c2ecf20Sopenharmony_ci 1618c2ecf20Sopenharmony_ci 1628c2ecf20Sopenharmony_ci/* 1638c2ecf20Sopenharmony_ci * For the 16C950 1648c2ecf20Sopenharmony_ci */ 1658c2ecf20Sopenharmony_cistatic void serial_icr_write(struct uart_sunsu_port *up, int offset, int value) 1668c2ecf20Sopenharmony_ci{ 1678c2ecf20Sopenharmony_ci serial_out(up, UART_SCR, offset); 1688c2ecf20Sopenharmony_ci serial_out(up, UART_ICR, value); 1698c2ecf20Sopenharmony_ci} 1708c2ecf20Sopenharmony_ci 1718c2ecf20Sopenharmony_ci#if 0 /* Unused currently */ 1728c2ecf20Sopenharmony_cistatic unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset) 1738c2ecf20Sopenharmony_ci{ 1748c2ecf20Sopenharmony_ci unsigned int value; 1758c2ecf20Sopenharmony_ci 1768c2ecf20Sopenharmony_ci serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 1778c2ecf20Sopenharmony_ci serial_out(up, UART_SCR, offset); 1788c2ecf20Sopenharmony_ci value = serial_in(up, UART_ICR); 1798c2ecf20Sopenharmony_ci serial_icr_write(up, UART_ACR, up->acr); 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_ci return value; 1828c2ecf20Sopenharmony_ci} 1838c2ecf20Sopenharmony_ci#endif 1848c2ecf20Sopenharmony_ci 1858c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_8250_RSA 1868c2ecf20Sopenharmony_ci/* 1878c2ecf20Sopenharmony_ci * Attempts to turn on the RSA FIFO. Returns zero on failure. 1888c2ecf20Sopenharmony_ci * We set the port uart clock rate if we succeed. 1898c2ecf20Sopenharmony_ci */ 1908c2ecf20Sopenharmony_cistatic int __enable_rsa(struct uart_sunsu_port *up) 1918c2ecf20Sopenharmony_ci{ 1928c2ecf20Sopenharmony_ci unsigned char mode; 1938c2ecf20Sopenharmony_ci int result; 1948c2ecf20Sopenharmony_ci 1958c2ecf20Sopenharmony_ci mode = serial_inp(up, UART_RSA_MSR); 1968c2ecf20Sopenharmony_ci result = mode & UART_RSA_MSR_FIFO; 1978c2ecf20Sopenharmony_ci 1988c2ecf20Sopenharmony_ci if (!result) { 1998c2ecf20Sopenharmony_ci serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 2008c2ecf20Sopenharmony_ci mode = serial_inp(up, UART_RSA_MSR); 2018c2ecf20Sopenharmony_ci result = mode & UART_RSA_MSR_FIFO; 2028c2ecf20Sopenharmony_ci } 2038c2ecf20Sopenharmony_ci 2048c2ecf20Sopenharmony_ci if (result) 2058c2ecf20Sopenharmony_ci up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 2068c2ecf20Sopenharmony_ci 2078c2ecf20Sopenharmony_ci return result; 2088c2ecf20Sopenharmony_ci} 2098c2ecf20Sopenharmony_ci 2108c2ecf20Sopenharmony_cistatic void enable_rsa(struct uart_sunsu_port *up) 2118c2ecf20Sopenharmony_ci{ 2128c2ecf20Sopenharmony_ci if (up->port.type == PORT_RSA) { 2138c2ecf20Sopenharmony_ci if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 2148c2ecf20Sopenharmony_ci spin_lock_irq(&up->port.lock); 2158c2ecf20Sopenharmony_ci __enable_rsa(up); 2168c2ecf20Sopenharmony_ci spin_unlock_irq(&up->port.lock); 2178c2ecf20Sopenharmony_ci } 2188c2ecf20Sopenharmony_ci if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 2198c2ecf20Sopenharmony_ci serial_outp(up, UART_RSA_FRR, 0); 2208c2ecf20Sopenharmony_ci } 2218c2ecf20Sopenharmony_ci} 2228c2ecf20Sopenharmony_ci 2238c2ecf20Sopenharmony_ci/* 2248c2ecf20Sopenharmony_ci * Attempts to turn off the RSA FIFO. Returns zero on failure. 2258c2ecf20Sopenharmony_ci * It is unknown why interrupts were disabled in here. However, 2268c2ecf20Sopenharmony_ci * the caller is expected to preserve this behaviour by grabbing 2278c2ecf20Sopenharmony_ci * the spinlock before calling this function. 2288c2ecf20Sopenharmony_ci */ 2298c2ecf20Sopenharmony_cistatic void disable_rsa(struct uart_sunsu_port *up) 2308c2ecf20Sopenharmony_ci{ 2318c2ecf20Sopenharmony_ci unsigned char mode; 2328c2ecf20Sopenharmony_ci int result; 2338c2ecf20Sopenharmony_ci 2348c2ecf20Sopenharmony_ci if (up->port.type == PORT_RSA && 2358c2ecf20Sopenharmony_ci up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 2368c2ecf20Sopenharmony_ci spin_lock_irq(&up->port.lock); 2378c2ecf20Sopenharmony_ci 2388c2ecf20Sopenharmony_ci mode = serial_inp(up, UART_RSA_MSR); 2398c2ecf20Sopenharmony_ci result = !(mode & UART_RSA_MSR_FIFO); 2408c2ecf20Sopenharmony_ci 2418c2ecf20Sopenharmony_ci if (!result) { 2428c2ecf20Sopenharmony_ci serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 2438c2ecf20Sopenharmony_ci mode = serial_inp(up, UART_RSA_MSR); 2448c2ecf20Sopenharmony_ci result = !(mode & UART_RSA_MSR_FIFO); 2458c2ecf20Sopenharmony_ci } 2468c2ecf20Sopenharmony_ci 2478c2ecf20Sopenharmony_ci if (result) 2488c2ecf20Sopenharmony_ci up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 2498c2ecf20Sopenharmony_ci spin_unlock_irq(&up->port.lock); 2508c2ecf20Sopenharmony_ci } 2518c2ecf20Sopenharmony_ci} 2528c2ecf20Sopenharmony_ci#endif /* CONFIG_SERIAL_8250_RSA */ 2538c2ecf20Sopenharmony_ci 2548c2ecf20Sopenharmony_cistatic inline void __stop_tx(struct uart_sunsu_port *p) 2558c2ecf20Sopenharmony_ci{ 2568c2ecf20Sopenharmony_ci if (p->ier & UART_IER_THRI) { 2578c2ecf20Sopenharmony_ci p->ier &= ~UART_IER_THRI; 2588c2ecf20Sopenharmony_ci serial_out(p, UART_IER, p->ier); 2598c2ecf20Sopenharmony_ci } 2608c2ecf20Sopenharmony_ci} 2618c2ecf20Sopenharmony_ci 2628c2ecf20Sopenharmony_cistatic void sunsu_stop_tx(struct uart_port *port) 2638c2ecf20Sopenharmony_ci{ 2648c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 2658c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 2668c2ecf20Sopenharmony_ci 2678c2ecf20Sopenharmony_ci __stop_tx(up); 2688c2ecf20Sopenharmony_ci 2698c2ecf20Sopenharmony_ci /* 2708c2ecf20Sopenharmony_ci * We really want to stop the transmitter from sending. 2718c2ecf20Sopenharmony_ci */ 2728c2ecf20Sopenharmony_ci if (up->port.type == PORT_16C950) { 2738c2ecf20Sopenharmony_ci up->acr |= UART_ACR_TXDIS; 2748c2ecf20Sopenharmony_ci serial_icr_write(up, UART_ACR, up->acr); 2758c2ecf20Sopenharmony_ci } 2768c2ecf20Sopenharmony_ci} 2778c2ecf20Sopenharmony_ci 2788c2ecf20Sopenharmony_cistatic void sunsu_start_tx(struct uart_port *port) 2798c2ecf20Sopenharmony_ci{ 2808c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 2818c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 2828c2ecf20Sopenharmony_ci 2838c2ecf20Sopenharmony_ci if (!(up->ier & UART_IER_THRI)) { 2848c2ecf20Sopenharmony_ci up->ier |= UART_IER_THRI; 2858c2ecf20Sopenharmony_ci serial_out(up, UART_IER, up->ier); 2868c2ecf20Sopenharmony_ci } 2878c2ecf20Sopenharmony_ci 2888c2ecf20Sopenharmony_ci /* 2898c2ecf20Sopenharmony_ci * Re-enable the transmitter if we disabled it. 2908c2ecf20Sopenharmony_ci */ 2918c2ecf20Sopenharmony_ci if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 2928c2ecf20Sopenharmony_ci up->acr &= ~UART_ACR_TXDIS; 2938c2ecf20Sopenharmony_ci serial_icr_write(up, UART_ACR, up->acr); 2948c2ecf20Sopenharmony_ci } 2958c2ecf20Sopenharmony_ci} 2968c2ecf20Sopenharmony_ci 2978c2ecf20Sopenharmony_cistatic void sunsu_stop_rx(struct uart_port *port) 2988c2ecf20Sopenharmony_ci{ 2998c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 3008c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 3018c2ecf20Sopenharmony_ci 3028c2ecf20Sopenharmony_ci up->ier &= ~UART_IER_RLSI; 3038c2ecf20Sopenharmony_ci up->port.read_status_mask &= ~UART_LSR_DR; 3048c2ecf20Sopenharmony_ci serial_out(up, UART_IER, up->ier); 3058c2ecf20Sopenharmony_ci} 3068c2ecf20Sopenharmony_ci 3078c2ecf20Sopenharmony_cistatic void sunsu_enable_ms(struct uart_port *port) 3088c2ecf20Sopenharmony_ci{ 3098c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 3108c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 3118c2ecf20Sopenharmony_ci unsigned long flags; 3128c2ecf20Sopenharmony_ci 3138c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 3148c2ecf20Sopenharmony_ci up->ier |= UART_IER_MSI; 3158c2ecf20Sopenharmony_ci serial_out(up, UART_IER, up->ier); 3168c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 3178c2ecf20Sopenharmony_ci} 3188c2ecf20Sopenharmony_ci 3198c2ecf20Sopenharmony_cistatic void 3208c2ecf20Sopenharmony_cireceive_chars(struct uart_sunsu_port *up, unsigned char *status) 3218c2ecf20Sopenharmony_ci{ 3228c2ecf20Sopenharmony_ci struct tty_port *port = &up->port.state->port; 3238c2ecf20Sopenharmony_ci unsigned char ch, flag; 3248c2ecf20Sopenharmony_ci int max_count = 256; 3258c2ecf20Sopenharmony_ci int saw_console_brk = 0; 3268c2ecf20Sopenharmony_ci 3278c2ecf20Sopenharmony_ci do { 3288c2ecf20Sopenharmony_ci ch = serial_inp(up, UART_RX); 3298c2ecf20Sopenharmony_ci flag = TTY_NORMAL; 3308c2ecf20Sopenharmony_ci up->port.icount.rx++; 3318c2ecf20Sopenharmony_ci 3328c2ecf20Sopenharmony_ci if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 3338c2ecf20Sopenharmony_ci UART_LSR_FE | UART_LSR_OE))) { 3348c2ecf20Sopenharmony_ci /* 3358c2ecf20Sopenharmony_ci * For statistics only 3368c2ecf20Sopenharmony_ci */ 3378c2ecf20Sopenharmony_ci if (*status & UART_LSR_BI) { 3388c2ecf20Sopenharmony_ci *status &= ~(UART_LSR_FE | UART_LSR_PE); 3398c2ecf20Sopenharmony_ci up->port.icount.brk++; 3408c2ecf20Sopenharmony_ci if (up->port.cons != NULL && 3418c2ecf20Sopenharmony_ci up->port.line == up->port.cons->index) 3428c2ecf20Sopenharmony_ci saw_console_brk = 1; 3438c2ecf20Sopenharmony_ci /* 3448c2ecf20Sopenharmony_ci * We do the SysRQ and SAK checking 3458c2ecf20Sopenharmony_ci * here because otherwise the break 3468c2ecf20Sopenharmony_ci * may get masked by ignore_status_mask 3478c2ecf20Sopenharmony_ci * or read_status_mask. 3488c2ecf20Sopenharmony_ci */ 3498c2ecf20Sopenharmony_ci if (uart_handle_break(&up->port)) 3508c2ecf20Sopenharmony_ci goto ignore_char; 3518c2ecf20Sopenharmony_ci } else if (*status & UART_LSR_PE) 3528c2ecf20Sopenharmony_ci up->port.icount.parity++; 3538c2ecf20Sopenharmony_ci else if (*status & UART_LSR_FE) 3548c2ecf20Sopenharmony_ci up->port.icount.frame++; 3558c2ecf20Sopenharmony_ci if (*status & UART_LSR_OE) 3568c2ecf20Sopenharmony_ci up->port.icount.overrun++; 3578c2ecf20Sopenharmony_ci 3588c2ecf20Sopenharmony_ci /* 3598c2ecf20Sopenharmony_ci * Mask off conditions which should be ingored. 3608c2ecf20Sopenharmony_ci */ 3618c2ecf20Sopenharmony_ci *status &= up->port.read_status_mask; 3628c2ecf20Sopenharmony_ci 3638c2ecf20Sopenharmony_ci if (up->port.cons != NULL && 3648c2ecf20Sopenharmony_ci up->port.line == up->port.cons->index) { 3658c2ecf20Sopenharmony_ci /* Recover the break flag from console xmit */ 3668c2ecf20Sopenharmony_ci *status |= up->lsr_break_flag; 3678c2ecf20Sopenharmony_ci up->lsr_break_flag = 0; 3688c2ecf20Sopenharmony_ci } 3698c2ecf20Sopenharmony_ci 3708c2ecf20Sopenharmony_ci if (*status & UART_LSR_BI) { 3718c2ecf20Sopenharmony_ci flag = TTY_BREAK; 3728c2ecf20Sopenharmony_ci } else if (*status & UART_LSR_PE) 3738c2ecf20Sopenharmony_ci flag = TTY_PARITY; 3748c2ecf20Sopenharmony_ci else if (*status & UART_LSR_FE) 3758c2ecf20Sopenharmony_ci flag = TTY_FRAME; 3768c2ecf20Sopenharmony_ci } 3778c2ecf20Sopenharmony_ci if (uart_handle_sysrq_char(&up->port, ch)) 3788c2ecf20Sopenharmony_ci goto ignore_char; 3798c2ecf20Sopenharmony_ci if ((*status & up->port.ignore_status_mask) == 0) 3808c2ecf20Sopenharmony_ci tty_insert_flip_char(port, ch, flag); 3818c2ecf20Sopenharmony_ci if (*status & UART_LSR_OE) 3828c2ecf20Sopenharmony_ci /* 3838c2ecf20Sopenharmony_ci * Overrun is special, since it's reported 3848c2ecf20Sopenharmony_ci * immediately, and doesn't affect the current 3858c2ecf20Sopenharmony_ci * character. 3868c2ecf20Sopenharmony_ci */ 3878c2ecf20Sopenharmony_ci tty_insert_flip_char(port, 0, TTY_OVERRUN); 3888c2ecf20Sopenharmony_ci ignore_char: 3898c2ecf20Sopenharmony_ci *status = serial_inp(up, UART_LSR); 3908c2ecf20Sopenharmony_ci } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 3918c2ecf20Sopenharmony_ci 3928c2ecf20Sopenharmony_ci if (saw_console_brk) 3938c2ecf20Sopenharmony_ci sun_do_break(); 3948c2ecf20Sopenharmony_ci} 3958c2ecf20Sopenharmony_ci 3968c2ecf20Sopenharmony_cistatic void transmit_chars(struct uart_sunsu_port *up) 3978c2ecf20Sopenharmony_ci{ 3988c2ecf20Sopenharmony_ci struct circ_buf *xmit = &up->port.state->xmit; 3998c2ecf20Sopenharmony_ci int count; 4008c2ecf20Sopenharmony_ci 4018c2ecf20Sopenharmony_ci if (up->port.x_char) { 4028c2ecf20Sopenharmony_ci serial_outp(up, UART_TX, up->port.x_char); 4038c2ecf20Sopenharmony_ci up->port.icount.tx++; 4048c2ecf20Sopenharmony_ci up->port.x_char = 0; 4058c2ecf20Sopenharmony_ci return; 4068c2ecf20Sopenharmony_ci } 4078c2ecf20Sopenharmony_ci if (uart_tx_stopped(&up->port)) { 4088c2ecf20Sopenharmony_ci sunsu_stop_tx(&up->port); 4098c2ecf20Sopenharmony_ci return; 4108c2ecf20Sopenharmony_ci } 4118c2ecf20Sopenharmony_ci if (uart_circ_empty(xmit)) { 4128c2ecf20Sopenharmony_ci __stop_tx(up); 4138c2ecf20Sopenharmony_ci return; 4148c2ecf20Sopenharmony_ci } 4158c2ecf20Sopenharmony_ci 4168c2ecf20Sopenharmony_ci count = up->port.fifosize; 4178c2ecf20Sopenharmony_ci do { 4188c2ecf20Sopenharmony_ci serial_out(up, UART_TX, xmit->buf[xmit->tail]); 4198c2ecf20Sopenharmony_ci xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 4208c2ecf20Sopenharmony_ci up->port.icount.tx++; 4218c2ecf20Sopenharmony_ci if (uart_circ_empty(xmit)) 4228c2ecf20Sopenharmony_ci break; 4238c2ecf20Sopenharmony_ci } while (--count > 0); 4248c2ecf20Sopenharmony_ci 4258c2ecf20Sopenharmony_ci if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 4268c2ecf20Sopenharmony_ci uart_write_wakeup(&up->port); 4278c2ecf20Sopenharmony_ci 4288c2ecf20Sopenharmony_ci if (uart_circ_empty(xmit)) 4298c2ecf20Sopenharmony_ci __stop_tx(up); 4308c2ecf20Sopenharmony_ci} 4318c2ecf20Sopenharmony_ci 4328c2ecf20Sopenharmony_cistatic void check_modem_status(struct uart_sunsu_port *up) 4338c2ecf20Sopenharmony_ci{ 4348c2ecf20Sopenharmony_ci int status; 4358c2ecf20Sopenharmony_ci 4368c2ecf20Sopenharmony_ci status = serial_in(up, UART_MSR); 4378c2ecf20Sopenharmony_ci 4388c2ecf20Sopenharmony_ci if ((status & UART_MSR_ANY_DELTA) == 0) 4398c2ecf20Sopenharmony_ci return; 4408c2ecf20Sopenharmony_ci 4418c2ecf20Sopenharmony_ci if (status & UART_MSR_TERI) 4428c2ecf20Sopenharmony_ci up->port.icount.rng++; 4438c2ecf20Sopenharmony_ci if (status & UART_MSR_DDSR) 4448c2ecf20Sopenharmony_ci up->port.icount.dsr++; 4458c2ecf20Sopenharmony_ci if (status & UART_MSR_DDCD) 4468c2ecf20Sopenharmony_ci uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 4478c2ecf20Sopenharmony_ci if (status & UART_MSR_DCTS) 4488c2ecf20Sopenharmony_ci uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 4498c2ecf20Sopenharmony_ci 4508c2ecf20Sopenharmony_ci wake_up_interruptible(&up->port.state->port.delta_msr_wait); 4518c2ecf20Sopenharmony_ci} 4528c2ecf20Sopenharmony_ci 4538c2ecf20Sopenharmony_cistatic irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id) 4548c2ecf20Sopenharmony_ci{ 4558c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = dev_id; 4568c2ecf20Sopenharmony_ci unsigned long flags; 4578c2ecf20Sopenharmony_ci unsigned char status; 4588c2ecf20Sopenharmony_ci 4598c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 4608c2ecf20Sopenharmony_ci 4618c2ecf20Sopenharmony_ci do { 4628c2ecf20Sopenharmony_ci status = serial_inp(up, UART_LSR); 4638c2ecf20Sopenharmony_ci if (status & UART_LSR_DR) 4648c2ecf20Sopenharmony_ci receive_chars(up, &status); 4658c2ecf20Sopenharmony_ci check_modem_status(up); 4668c2ecf20Sopenharmony_ci if (status & UART_LSR_THRE) 4678c2ecf20Sopenharmony_ci transmit_chars(up); 4688c2ecf20Sopenharmony_ci 4698c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 4708c2ecf20Sopenharmony_ci 4718c2ecf20Sopenharmony_ci tty_flip_buffer_push(&up->port.state->port); 4728c2ecf20Sopenharmony_ci 4738c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 4748c2ecf20Sopenharmony_ci 4758c2ecf20Sopenharmony_ci } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)); 4768c2ecf20Sopenharmony_ci 4778c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 4788c2ecf20Sopenharmony_ci 4798c2ecf20Sopenharmony_ci return IRQ_HANDLED; 4808c2ecf20Sopenharmony_ci} 4818c2ecf20Sopenharmony_ci 4828c2ecf20Sopenharmony_ci/* Separate interrupt handling path for keyboard/mouse ports. */ 4838c2ecf20Sopenharmony_ci 4848c2ecf20Sopenharmony_cistatic void 4858c2ecf20Sopenharmony_cisunsu_change_speed(struct uart_port *port, unsigned int cflag, 4868c2ecf20Sopenharmony_ci unsigned int iflag, unsigned int quot); 4878c2ecf20Sopenharmony_ci 4888c2ecf20Sopenharmony_cistatic void sunsu_change_mouse_baud(struct uart_sunsu_port *up) 4898c2ecf20Sopenharmony_ci{ 4908c2ecf20Sopenharmony_ci unsigned int cur_cflag = up->cflag; 4918c2ecf20Sopenharmony_ci int quot, new_baud; 4928c2ecf20Sopenharmony_ci 4938c2ecf20Sopenharmony_ci up->cflag &= ~CBAUD; 4948c2ecf20Sopenharmony_ci up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud); 4958c2ecf20Sopenharmony_ci 4968c2ecf20Sopenharmony_ci quot = up->port.uartclk / (16 * new_baud); 4978c2ecf20Sopenharmony_ci 4988c2ecf20Sopenharmony_ci sunsu_change_speed(&up->port, up->cflag, 0, quot); 4998c2ecf20Sopenharmony_ci} 5008c2ecf20Sopenharmony_ci 5018c2ecf20Sopenharmony_cistatic void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break) 5028c2ecf20Sopenharmony_ci{ 5038c2ecf20Sopenharmony_ci do { 5048c2ecf20Sopenharmony_ci unsigned char ch = serial_inp(up, UART_RX); 5058c2ecf20Sopenharmony_ci 5068c2ecf20Sopenharmony_ci /* Stop-A is handled by drivers/char/keyboard.c now. */ 5078c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_KBD) { 5088c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 5098c2ecf20Sopenharmony_ci serio_interrupt(&up->serio, ch, 0); 5108c2ecf20Sopenharmony_ci#endif 5118c2ecf20Sopenharmony_ci } else if (up->su_type == SU_PORT_MS) { 5128c2ecf20Sopenharmony_ci int ret = suncore_mouse_baud_detection(ch, is_break); 5138c2ecf20Sopenharmony_ci 5148c2ecf20Sopenharmony_ci switch (ret) { 5158c2ecf20Sopenharmony_ci case 2: 5168c2ecf20Sopenharmony_ci sunsu_change_mouse_baud(up); 5178c2ecf20Sopenharmony_ci fallthrough; 5188c2ecf20Sopenharmony_ci case 1: 5198c2ecf20Sopenharmony_ci break; 5208c2ecf20Sopenharmony_ci 5218c2ecf20Sopenharmony_ci case 0: 5228c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 5238c2ecf20Sopenharmony_ci serio_interrupt(&up->serio, ch, 0); 5248c2ecf20Sopenharmony_ci#endif 5258c2ecf20Sopenharmony_ci break; 5268c2ecf20Sopenharmony_ci } 5278c2ecf20Sopenharmony_ci } 5288c2ecf20Sopenharmony_ci } while (serial_in(up, UART_LSR) & UART_LSR_DR); 5298c2ecf20Sopenharmony_ci} 5308c2ecf20Sopenharmony_ci 5318c2ecf20Sopenharmony_cistatic irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id) 5328c2ecf20Sopenharmony_ci{ 5338c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = dev_id; 5348c2ecf20Sopenharmony_ci 5358c2ecf20Sopenharmony_ci if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) { 5368c2ecf20Sopenharmony_ci unsigned char status = serial_inp(up, UART_LSR); 5378c2ecf20Sopenharmony_ci 5388c2ecf20Sopenharmony_ci if ((status & UART_LSR_DR) || (status & UART_LSR_BI)) 5398c2ecf20Sopenharmony_ci receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0); 5408c2ecf20Sopenharmony_ci } 5418c2ecf20Sopenharmony_ci 5428c2ecf20Sopenharmony_ci return IRQ_HANDLED; 5438c2ecf20Sopenharmony_ci} 5448c2ecf20Sopenharmony_ci 5458c2ecf20Sopenharmony_cistatic unsigned int sunsu_tx_empty(struct uart_port *port) 5468c2ecf20Sopenharmony_ci{ 5478c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 5488c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 5498c2ecf20Sopenharmony_ci unsigned long flags; 5508c2ecf20Sopenharmony_ci unsigned int ret; 5518c2ecf20Sopenharmony_ci 5528c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 5538c2ecf20Sopenharmony_ci ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 5548c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 5558c2ecf20Sopenharmony_ci 5568c2ecf20Sopenharmony_ci return ret; 5578c2ecf20Sopenharmony_ci} 5588c2ecf20Sopenharmony_ci 5598c2ecf20Sopenharmony_cistatic unsigned int sunsu_get_mctrl(struct uart_port *port) 5608c2ecf20Sopenharmony_ci{ 5618c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 5628c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 5638c2ecf20Sopenharmony_ci unsigned char status; 5648c2ecf20Sopenharmony_ci unsigned int ret; 5658c2ecf20Sopenharmony_ci 5668c2ecf20Sopenharmony_ci status = serial_in(up, UART_MSR); 5678c2ecf20Sopenharmony_ci 5688c2ecf20Sopenharmony_ci ret = 0; 5698c2ecf20Sopenharmony_ci if (status & UART_MSR_DCD) 5708c2ecf20Sopenharmony_ci ret |= TIOCM_CAR; 5718c2ecf20Sopenharmony_ci if (status & UART_MSR_RI) 5728c2ecf20Sopenharmony_ci ret |= TIOCM_RNG; 5738c2ecf20Sopenharmony_ci if (status & UART_MSR_DSR) 5748c2ecf20Sopenharmony_ci ret |= TIOCM_DSR; 5758c2ecf20Sopenharmony_ci if (status & UART_MSR_CTS) 5768c2ecf20Sopenharmony_ci ret |= TIOCM_CTS; 5778c2ecf20Sopenharmony_ci return ret; 5788c2ecf20Sopenharmony_ci} 5798c2ecf20Sopenharmony_ci 5808c2ecf20Sopenharmony_cistatic void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl) 5818c2ecf20Sopenharmony_ci{ 5828c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 5838c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 5848c2ecf20Sopenharmony_ci unsigned char mcr = 0; 5858c2ecf20Sopenharmony_ci 5868c2ecf20Sopenharmony_ci if (mctrl & TIOCM_RTS) 5878c2ecf20Sopenharmony_ci mcr |= UART_MCR_RTS; 5888c2ecf20Sopenharmony_ci if (mctrl & TIOCM_DTR) 5898c2ecf20Sopenharmony_ci mcr |= UART_MCR_DTR; 5908c2ecf20Sopenharmony_ci if (mctrl & TIOCM_OUT1) 5918c2ecf20Sopenharmony_ci mcr |= UART_MCR_OUT1; 5928c2ecf20Sopenharmony_ci if (mctrl & TIOCM_OUT2) 5938c2ecf20Sopenharmony_ci mcr |= UART_MCR_OUT2; 5948c2ecf20Sopenharmony_ci if (mctrl & TIOCM_LOOP) 5958c2ecf20Sopenharmony_ci mcr |= UART_MCR_LOOP; 5968c2ecf20Sopenharmony_ci 5978c2ecf20Sopenharmony_ci serial_out(up, UART_MCR, mcr); 5988c2ecf20Sopenharmony_ci} 5998c2ecf20Sopenharmony_ci 6008c2ecf20Sopenharmony_cistatic void sunsu_break_ctl(struct uart_port *port, int break_state) 6018c2ecf20Sopenharmony_ci{ 6028c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 6038c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 6048c2ecf20Sopenharmony_ci unsigned long flags; 6058c2ecf20Sopenharmony_ci 6068c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 6078c2ecf20Sopenharmony_ci if (break_state == -1) 6088c2ecf20Sopenharmony_ci up->lcr |= UART_LCR_SBC; 6098c2ecf20Sopenharmony_ci else 6108c2ecf20Sopenharmony_ci up->lcr &= ~UART_LCR_SBC; 6118c2ecf20Sopenharmony_ci serial_out(up, UART_LCR, up->lcr); 6128c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 6138c2ecf20Sopenharmony_ci} 6148c2ecf20Sopenharmony_ci 6158c2ecf20Sopenharmony_cistatic int sunsu_startup(struct uart_port *port) 6168c2ecf20Sopenharmony_ci{ 6178c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 6188c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 6198c2ecf20Sopenharmony_ci unsigned long flags; 6208c2ecf20Sopenharmony_ci int retval; 6218c2ecf20Sopenharmony_ci 6228c2ecf20Sopenharmony_ci if (up->port.type == PORT_16C950) { 6238c2ecf20Sopenharmony_ci /* Wake up and initialize UART */ 6248c2ecf20Sopenharmony_ci up->acr = 0; 6258c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0xBF); 6268c2ecf20Sopenharmony_ci serial_outp(up, UART_EFR, UART_EFR_ECB); 6278c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, 0); 6288c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0); 6298c2ecf20Sopenharmony_ci serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 6308c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0xBF); 6318c2ecf20Sopenharmony_ci serial_outp(up, UART_EFR, UART_EFR_ECB); 6328c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0); 6338c2ecf20Sopenharmony_ci } 6348c2ecf20Sopenharmony_ci 6358c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_8250_RSA 6368c2ecf20Sopenharmony_ci /* 6378c2ecf20Sopenharmony_ci * If this is an RSA port, see if we can kick it up to the 6388c2ecf20Sopenharmony_ci * higher speed clock. 6398c2ecf20Sopenharmony_ci */ 6408c2ecf20Sopenharmony_ci enable_rsa(up); 6418c2ecf20Sopenharmony_ci#endif 6428c2ecf20Sopenharmony_ci 6438c2ecf20Sopenharmony_ci /* 6448c2ecf20Sopenharmony_ci * Clear the FIFO buffers and disable them. 6458c2ecf20Sopenharmony_ci * (they will be reenabled in set_termios()) 6468c2ecf20Sopenharmony_ci */ 6478c2ecf20Sopenharmony_ci if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) { 6488c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 6498c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 6508c2ecf20Sopenharmony_ci UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 6518c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, 0); 6528c2ecf20Sopenharmony_ci } 6538c2ecf20Sopenharmony_ci 6548c2ecf20Sopenharmony_ci /* 6558c2ecf20Sopenharmony_ci * Clear the interrupt registers. 6568c2ecf20Sopenharmony_ci */ 6578c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_LSR); 6588c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_RX); 6598c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_IIR); 6608c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_MSR); 6618c2ecf20Sopenharmony_ci 6628c2ecf20Sopenharmony_ci /* 6638c2ecf20Sopenharmony_ci * At this point, there's no way the LSR could still be 0xff; 6648c2ecf20Sopenharmony_ci * if it is, then bail out, because there's likely no UART 6658c2ecf20Sopenharmony_ci * here. 6668c2ecf20Sopenharmony_ci */ 6678c2ecf20Sopenharmony_ci if (!(up->port.flags & UPF_BUGGY_UART) && 6688c2ecf20Sopenharmony_ci (serial_inp(up, UART_LSR) == 0xff)) { 6698c2ecf20Sopenharmony_ci printk("ttyS%d: LSR safety check engaged!\n", up->port.line); 6708c2ecf20Sopenharmony_ci return -ENODEV; 6718c2ecf20Sopenharmony_ci } 6728c2ecf20Sopenharmony_ci 6738c2ecf20Sopenharmony_ci if (up->su_type != SU_PORT_PORT) { 6748c2ecf20Sopenharmony_ci retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt, 6758c2ecf20Sopenharmony_ci IRQF_SHARED, su_typev[up->su_type], up); 6768c2ecf20Sopenharmony_ci } else { 6778c2ecf20Sopenharmony_ci retval = request_irq(up->port.irq, sunsu_serial_interrupt, 6788c2ecf20Sopenharmony_ci IRQF_SHARED, su_typev[up->su_type], up); 6798c2ecf20Sopenharmony_ci } 6808c2ecf20Sopenharmony_ci if (retval) { 6818c2ecf20Sopenharmony_ci printk("su: Cannot register IRQ %d\n", up->port.irq); 6828c2ecf20Sopenharmony_ci return retval; 6838c2ecf20Sopenharmony_ci } 6848c2ecf20Sopenharmony_ci 6858c2ecf20Sopenharmony_ci /* 6868c2ecf20Sopenharmony_ci * Now, initialize the UART 6878c2ecf20Sopenharmony_ci */ 6888c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, UART_LCR_WLEN8); 6898c2ecf20Sopenharmony_ci 6908c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 6918c2ecf20Sopenharmony_ci 6928c2ecf20Sopenharmony_ci up->port.mctrl |= TIOCM_OUT2; 6938c2ecf20Sopenharmony_ci 6948c2ecf20Sopenharmony_ci sunsu_set_mctrl(&up->port, up->port.mctrl); 6958c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 6968c2ecf20Sopenharmony_ci 6978c2ecf20Sopenharmony_ci /* 6988c2ecf20Sopenharmony_ci * Finally, enable interrupts. Note: Modem status interrupts 6998c2ecf20Sopenharmony_ci * are set via set_termios(), which will be occurring imminently 7008c2ecf20Sopenharmony_ci * anyway, so we don't enable them here. 7018c2ecf20Sopenharmony_ci */ 7028c2ecf20Sopenharmony_ci up->ier = UART_IER_RLSI | UART_IER_RDI; 7038c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, up->ier); 7048c2ecf20Sopenharmony_ci 7058c2ecf20Sopenharmony_ci if (up->port.flags & UPF_FOURPORT) { 7068c2ecf20Sopenharmony_ci unsigned int icp; 7078c2ecf20Sopenharmony_ci /* 7088c2ecf20Sopenharmony_ci * Enable interrupts on the AST Fourport board 7098c2ecf20Sopenharmony_ci */ 7108c2ecf20Sopenharmony_ci icp = (up->port.iobase & 0xfe0) | 0x01f; 7118c2ecf20Sopenharmony_ci outb_p(0x80, icp); 7128c2ecf20Sopenharmony_ci (void) inb_p(icp); 7138c2ecf20Sopenharmony_ci } 7148c2ecf20Sopenharmony_ci 7158c2ecf20Sopenharmony_ci /* 7168c2ecf20Sopenharmony_ci * And clear the interrupt registers again for luck. 7178c2ecf20Sopenharmony_ci */ 7188c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_LSR); 7198c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_RX); 7208c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_IIR); 7218c2ecf20Sopenharmony_ci (void) serial_inp(up, UART_MSR); 7228c2ecf20Sopenharmony_ci 7238c2ecf20Sopenharmony_ci return 0; 7248c2ecf20Sopenharmony_ci} 7258c2ecf20Sopenharmony_ci 7268c2ecf20Sopenharmony_cistatic void sunsu_shutdown(struct uart_port *port) 7278c2ecf20Sopenharmony_ci{ 7288c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 7298c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 7308c2ecf20Sopenharmony_ci unsigned long flags; 7318c2ecf20Sopenharmony_ci 7328c2ecf20Sopenharmony_ci /* 7338c2ecf20Sopenharmony_ci * Disable interrupts from this port 7348c2ecf20Sopenharmony_ci */ 7358c2ecf20Sopenharmony_ci up->ier = 0; 7368c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, 0); 7378c2ecf20Sopenharmony_ci 7388c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 7398c2ecf20Sopenharmony_ci if (up->port.flags & UPF_FOURPORT) { 7408c2ecf20Sopenharmony_ci /* reset interrupts on the AST Fourport board */ 7418c2ecf20Sopenharmony_ci inb((up->port.iobase & 0xfe0) | 0x1f); 7428c2ecf20Sopenharmony_ci up->port.mctrl |= TIOCM_OUT1; 7438c2ecf20Sopenharmony_ci } else 7448c2ecf20Sopenharmony_ci up->port.mctrl &= ~TIOCM_OUT2; 7458c2ecf20Sopenharmony_ci 7468c2ecf20Sopenharmony_ci sunsu_set_mctrl(&up->port, up->port.mctrl); 7478c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 7488c2ecf20Sopenharmony_ci 7498c2ecf20Sopenharmony_ci /* 7508c2ecf20Sopenharmony_ci * Disable break condition and FIFOs 7518c2ecf20Sopenharmony_ci */ 7528c2ecf20Sopenharmony_ci serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); 7538c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 7548c2ecf20Sopenharmony_ci UART_FCR_CLEAR_RCVR | 7558c2ecf20Sopenharmony_ci UART_FCR_CLEAR_XMIT); 7568c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, 0); 7578c2ecf20Sopenharmony_ci 7588c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_8250_RSA 7598c2ecf20Sopenharmony_ci /* 7608c2ecf20Sopenharmony_ci * Reset the RSA board back to 115kbps compat mode. 7618c2ecf20Sopenharmony_ci */ 7628c2ecf20Sopenharmony_ci disable_rsa(up); 7638c2ecf20Sopenharmony_ci#endif 7648c2ecf20Sopenharmony_ci 7658c2ecf20Sopenharmony_ci /* 7668c2ecf20Sopenharmony_ci * Read data port to reset things. 7678c2ecf20Sopenharmony_ci */ 7688c2ecf20Sopenharmony_ci (void) serial_in(up, UART_RX); 7698c2ecf20Sopenharmony_ci 7708c2ecf20Sopenharmony_ci free_irq(up->port.irq, up); 7718c2ecf20Sopenharmony_ci} 7728c2ecf20Sopenharmony_ci 7738c2ecf20Sopenharmony_cistatic void 7748c2ecf20Sopenharmony_cisunsu_change_speed(struct uart_port *port, unsigned int cflag, 7758c2ecf20Sopenharmony_ci unsigned int iflag, unsigned int quot) 7768c2ecf20Sopenharmony_ci{ 7778c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 7788c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 7798c2ecf20Sopenharmony_ci unsigned char cval, fcr = 0; 7808c2ecf20Sopenharmony_ci unsigned long flags; 7818c2ecf20Sopenharmony_ci 7828c2ecf20Sopenharmony_ci switch (cflag & CSIZE) { 7838c2ecf20Sopenharmony_ci case CS5: 7848c2ecf20Sopenharmony_ci cval = 0x00; 7858c2ecf20Sopenharmony_ci break; 7868c2ecf20Sopenharmony_ci case CS6: 7878c2ecf20Sopenharmony_ci cval = 0x01; 7888c2ecf20Sopenharmony_ci break; 7898c2ecf20Sopenharmony_ci case CS7: 7908c2ecf20Sopenharmony_ci cval = 0x02; 7918c2ecf20Sopenharmony_ci break; 7928c2ecf20Sopenharmony_ci default: 7938c2ecf20Sopenharmony_ci case CS8: 7948c2ecf20Sopenharmony_ci cval = 0x03; 7958c2ecf20Sopenharmony_ci break; 7968c2ecf20Sopenharmony_ci } 7978c2ecf20Sopenharmony_ci 7988c2ecf20Sopenharmony_ci if (cflag & CSTOPB) 7998c2ecf20Sopenharmony_ci cval |= 0x04; 8008c2ecf20Sopenharmony_ci if (cflag & PARENB) 8018c2ecf20Sopenharmony_ci cval |= UART_LCR_PARITY; 8028c2ecf20Sopenharmony_ci if (!(cflag & PARODD)) 8038c2ecf20Sopenharmony_ci cval |= UART_LCR_EPAR; 8048c2ecf20Sopenharmony_ci#ifdef CMSPAR 8058c2ecf20Sopenharmony_ci if (cflag & CMSPAR) 8068c2ecf20Sopenharmony_ci cval |= UART_LCR_SPAR; 8078c2ecf20Sopenharmony_ci#endif 8088c2ecf20Sopenharmony_ci 8098c2ecf20Sopenharmony_ci /* 8108c2ecf20Sopenharmony_ci * Work around a bug in the Oxford Semiconductor 952 rev B 8118c2ecf20Sopenharmony_ci * chip which causes it to seriously miscalculate baud rates 8128c2ecf20Sopenharmony_ci * when DLL is 0. 8138c2ecf20Sopenharmony_ci */ 8148c2ecf20Sopenharmony_ci if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 && 8158c2ecf20Sopenharmony_ci up->rev == 0x5201) 8168c2ecf20Sopenharmony_ci quot ++; 8178c2ecf20Sopenharmony_ci 8188c2ecf20Sopenharmony_ci if (uart_config[up->port.type].flags & UART_USE_FIFO) { 8198c2ecf20Sopenharmony_ci if ((up->port.uartclk / quot) < (2400 * 16)) 8208c2ecf20Sopenharmony_ci fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; 8218c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_8250_RSA 8228c2ecf20Sopenharmony_ci else if (up->port.type == PORT_RSA) 8238c2ecf20Sopenharmony_ci fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; 8248c2ecf20Sopenharmony_ci#endif 8258c2ecf20Sopenharmony_ci else 8268c2ecf20Sopenharmony_ci fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; 8278c2ecf20Sopenharmony_ci } 8288c2ecf20Sopenharmony_ci if (up->port.type == PORT_16750) 8298c2ecf20Sopenharmony_ci fcr |= UART_FCR7_64BYTE; 8308c2ecf20Sopenharmony_ci 8318c2ecf20Sopenharmony_ci /* 8328c2ecf20Sopenharmony_ci * Ok, we're now changing the port state. Do it with 8338c2ecf20Sopenharmony_ci * interrupts disabled. 8348c2ecf20Sopenharmony_ci */ 8358c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 8368c2ecf20Sopenharmony_ci 8378c2ecf20Sopenharmony_ci /* 8388c2ecf20Sopenharmony_ci * Update the per-port timeout. 8398c2ecf20Sopenharmony_ci */ 8408c2ecf20Sopenharmony_ci uart_update_timeout(port, cflag, (port->uartclk / (16 * quot))); 8418c2ecf20Sopenharmony_ci 8428c2ecf20Sopenharmony_ci up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 8438c2ecf20Sopenharmony_ci if (iflag & INPCK) 8448c2ecf20Sopenharmony_ci up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 8458c2ecf20Sopenharmony_ci if (iflag & (IGNBRK | BRKINT | PARMRK)) 8468c2ecf20Sopenharmony_ci up->port.read_status_mask |= UART_LSR_BI; 8478c2ecf20Sopenharmony_ci 8488c2ecf20Sopenharmony_ci /* 8498c2ecf20Sopenharmony_ci * Characteres to ignore 8508c2ecf20Sopenharmony_ci */ 8518c2ecf20Sopenharmony_ci up->port.ignore_status_mask = 0; 8528c2ecf20Sopenharmony_ci if (iflag & IGNPAR) 8538c2ecf20Sopenharmony_ci up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 8548c2ecf20Sopenharmony_ci if (iflag & IGNBRK) { 8558c2ecf20Sopenharmony_ci up->port.ignore_status_mask |= UART_LSR_BI; 8568c2ecf20Sopenharmony_ci /* 8578c2ecf20Sopenharmony_ci * If we're ignoring parity and break indicators, 8588c2ecf20Sopenharmony_ci * ignore overruns too (for real raw support). 8598c2ecf20Sopenharmony_ci */ 8608c2ecf20Sopenharmony_ci if (iflag & IGNPAR) 8618c2ecf20Sopenharmony_ci up->port.ignore_status_mask |= UART_LSR_OE; 8628c2ecf20Sopenharmony_ci } 8638c2ecf20Sopenharmony_ci 8648c2ecf20Sopenharmony_ci /* 8658c2ecf20Sopenharmony_ci * ignore all characters if CREAD is not set 8668c2ecf20Sopenharmony_ci */ 8678c2ecf20Sopenharmony_ci if ((cflag & CREAD) == 0) 8688c2ecf20Sopenharmony_ci up->port.ignore_status_mask |= UART_LSR_DR; 8698c2ecf20Sopenharmony_ci 8708c2ecf20Sopenharmony_ci /* 8718c2ecf20Sopenharmony_ci * CTS flow control flag and modem status interrupts 8728c2ecf20Sopenharmony_ci */ 8738c2ecf20Sopenharmony_ci up->ier &= ~UART_IER_MSI; 8748c2ecf20Sopenharmony_ci if (UART_ENABLE_MS(&up->port, cflag)) 8758c2ecf20Sopenharmony_ci up->ier |= UART_IER_MSI; 8768c2ecf20Sopenharmony_ci 8778c2ecf20Sopenharmony_ci serial_out(up, UART_IER, up->ier); 8788c2ecf20Sopenharmony_ci 8798c2ecf20Sopenharmony_ci if (uart_config[up->port.type].flags & UART_STARTECH) { 8808c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0xBF); 8818c2ecf20Sopenharmony_ci serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0); 8828c2ecf20Sopenharmony_ci } 8838c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ 8848c2ecf20Sopenharmony_ci serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ 8858c2ecf20Sopenharmony_ci serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ 8868c2ecf20Sopenharmony_ci if (up->port.type == PORT_16750) 8878c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, fcr); /* set fcr */ 8888c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, cval); /* reset DLAB */ 8898c2ecf20Sopenharmony_ci up->lcr = cval; /* Save LCR */ 8908c2ecf20Sopenharmony_ci if (up->port.type != PORT_16750) { 8918c2ecf20Sopenharmony_ci if (fcr & UART_FCR_ENABLE_FIFO) { 8928c2ecf20Sopenharmony_ci /* emulated UARTs (Lucent Venus 167x) need two steps */ 8938c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 8948c2ecf20Sopenharmony_ci } 8958c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, fcr); /* set fcr */ 8968c2ecf20Sopenharmony_ci } 8978c2ecf20Sopenharmony_ci 8988c2ecf20Sopenharmony_ci up->cflag = cflag; 8998c2ecf20Sopenharmony_ci 9008c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 9018c2ecf20Sopenharmony_ci} 9028c2ecf20Sopenharmony_ci 9038c2ecf20Sopenharmony_cistatic void 9048c2ecf20Sopenharmony_cisunsu_set_termios(struct uart_port *port, struct ktermios *termios, 9058c2ecf20Sopenharmony_ci struct ktermios *old) 9068c2ecf20Sopenharmony_ci{ 9078c2ecf20Sopenharmony_ci unsigned int baud, quot; 9088c2ecf20Sopenharmony_ci 9098c2ecf20Sopenharmony_ci /* 9108c2ecf20Sopenharmony_ci * Ask the core to calculate the divisor for us. 9118c2ecf20Sopenharmony_ci */ 9128c2ecf20Sopenharmony_ci baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 9138c2ecf20Sopenharmony_ci quot = uart_get_divisor(port, baud); 9148c2ecf20Sopenharmony_ci 9158c2ecf20Sopenharmony_ci sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot); 9168c2ecf20Sopenharmony_ci} 9178c2ecf20Sopenharmony_ci 9188c2ecf20Sopenharmony_cistatic void sunsu_release_port(struct uart_port *port) 9198c2ecf20Sopenharmony_ci{ 9208c2ecf20Sopenharmony_ci} 9218c2ecf20Sopenharmony_ci 9228c2ecf20Sopenharmony_cistatic int sunsu_request_port(struct uart_port *port) 9238c2ecf20Sopenharmony_ci{ 9248c2ecf20Sopenharmony_ci return 0; 9258c2ecf20Sopenharmony_ci} 9268c2ecf20Sopenharmony_ci 9278c2ecf20Sopenharmony_cistatic void sunsu_config_port(struct uart_port *port, int flags) 9288c2ecf20Sopenharmony_ci{ 9298c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 9308c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 9318c2ecf20Sopenharmony_ci 9328c2ecf20Sopenharmony_ci if (flags & UART_CONFIG_TYPE) { 9338c2ecf20Sopenharmony_ci /* 9348c2ecf20Sopenharmony_ci * We are supposed to call autoconfig here, but this requires 9358c2ecf20Sopenharmony_ci * splitting all the OBP probing crap from the UART probing. 9368c2ecf20Sopenharmony_ci * We'll do it when we kill sunsu.c altogether. 9378c2ecf20Sopenharmony_ci */ 9388c2ecf20Sopenharmony_ci port->type = up->type_probed; /* XXX */ 9398c2ecf20Sopenharmony_ci } 9408c2ecf20Sopenharmony_ci} 9418c2ecf20Sopenharmony_ci 9428c2ecf20Sopenharmony_cistatic int 9438c2ecf20Sopenharmony_cisunsu_verify_port(struct uart_port *port, struct serial_struct *ser) 9448c2ecf20Sopenharmony_ci{ 9458c2ecf20Sopenharmony_ci return -EINVAL; 9468c2ecf20Sopenharmony_ci} 9478c2ecf20Sopenharmony_ci 9488c2ecf20Sopenharmony_cistatic const char * 9498c2ecf20Sopenharmony_cisunsu_type(struct uart_port *port) 9508c2ecf20Sopenharmony_ci{ 9518c2ecf20Sopenharmony_ci int type = port->type; 9528c2ecf20Sopenharmony_ci 9538c2ecf20Sopenharmony_ci if (type >= ARRAY_SIZE(uart_config)) 9548c2ecf20Sopenharmony_ci type = 0; 9558c2ecf20Sopenharmony_ci return uart_config[type].name; 9568c2ecf20Sopenharmony_ci} 9578c2ecf20Sopenharmony_ci 9588c2ecf20Sopenharmony_cistatic const struct uart_ops sunsu_pops = { 9598c2ecf20Sopenharmony_ci .tx_empty = sunsu_tx_empty, 9608c2ecf20Sopenharmony_ci .set_mctrl = sunsu_set_mctrl, 9618c2ecf20Sopenharmony_ci .get_mctrl = sunsu_get_mctrl, 9628c2ecf20Sopenharmony_ci .stop_tx = sunsu_stop_tx, 9638c2ecf20Sopenharmony_ci .start_tx = sunsu_start_tx, 9648c2ecf20Sopenharmony_ci .stop_rx = sunsu_stop_rx, 9658c2ecf20Sopenharmony_ci .enable_ms = sunsu_enable_ms, 9668c2ecf20Sopenharmony_ci .break_ctl = sunsu_break_ctl, 9678c2ecf20Sopenharmony_ci .startup = sunsu_startup, 9688c2ecf20Sopenharmony_ci .shutdown = sunsu_shutdown, 9698c2ecf20Sopenharmony_ci .set_termios = sunsu_set_termios, 9708c2ecf20Sopenharmony_ci .type = sunsu_type, 9718c2ecf20Sopenharmony_ci .release_port = sunsu_release_port, 9728c2ecf20Sopenharmony_ci .request_port = sunsu_request_port, 9738c2ecf20Sopenharmony_ci .config_port = sunsu_config_port, 9748c2ecf20Sopenharmony_ci .verify_port = sunsu_verify_port, 9758c2ecf20Sopenharmony_ci}; 9768c2ecf20Sopenharmony_ci 9778c2ecf20Sopenharmony_ci#define UART_NR 4 9788c2ecf20Sopenharmony_ci 9798c2ecf20Sopenharmony_cistatic struct uart_sunsu_port sunsu_ports[UART_NR]; 9808c2ecf20Sopenharmony_cistatic int nr_inst; /* Number of already registered ports */ 9818c2ecf20Sopenharmony_ci 9828c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 9838c2ecf20Sopenharmony_ci 9848c2ecf20Sopenharmony_cistatic DEFINE_SPINLOCK(sunsu_serio_lock); 9858c2ecf20Sopenharmony_ci 9868c2ecf20Sopenharmony_cistatic int sunsu_serio_write(struct serio *serio, unsigned char ch) 9878c2ecf20Sopenharmony_ci{ 9888c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = serio->port_data; 9898c2ecf20Sopenharmony_ci unsigned long flags; 9908c2ecf20Sopenharmony_ci int lsr; 9918c2ecf20Sopenharmony_ci 9928c2ecf20Sopenharmony_ci spin_lock_irqsave(&sunsu_serio_lock, flags); 9938c2ecf20Sopenharmony_ci 9948c2ecf20Sopenharmony_ci do { 9958c2ecf20Sopenharmony_ci lsr = serial_in(up, UART_LSR); 9968c2ecf20Sopenharmony_ci } while (!(lsr & UART_LSR_THRE)); 9978c2ecf20Sopenharmony_ci 9988c2ecf20Sopenharmony_ci /* Send the character out. */ 9998c2ecf20Sopenharmony_ci serial_out(up, UART_TX, ch); 10008c2ecf20Sopenharmony_ci 10018c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&sunsu_serio_lock, flags); 10028c2ecf20Sopenharmony_ci 10038c2ecf20Sopenharmony_ci return 0; 10048c2ecf20Sopenharmony_ci} 10058c2ecf20Sopenharmony_ci 10068c2ecf20Sopenharmony_cistatic int sunsu_serio_open(struct serio *serio) 10078c2ecf20Sopenharmony_ci{ 10088c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = serio->port_data; 10098c2ecf20Sopenharmony_ci unsigned long flags; 10108c2ecf20Sopenharmony_ci int ret; 10118c2ecf20Sopenharmony_ci 10128c2ecf20Sopenharmony_ci spin_lock_irqsave(&sunsu_serio_lock, flags); 10138c2ecf20Sopenharmony_ci if (!up->serio_open) { 10148c2ecf20Sopenharmony_ci up->serio_open = 1; 10158c2ecf20Sopenharmony_ci ret = 0; 10168c2ecf20Sopenharmony_ci } else 10178c2ecf20Sopenharmony_ci ret = -EBUSY; 10188c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&sunsu_serio_lock, flags); 10198c2ecf20Sopenharmony_ci 10208c2ecf20Sopenharmony_ci return ret; 10218c2ecf20Sopenharmony_ci} 10228c2ecf20Sopenharmony_ci 10238c2ecf20Sopenharmony_cistatic void sunsu_serio_close(struct serio *serio) 10248c2ecf20Sopenharmony_ci{ 10258c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = serio->port_data; 10268c2ecf20Sopenharmony_ci unsigned long flags; 10278c2ecf20Sopenharmony_ci 10288c2ecf20Sopenharmony_ci spin_lock_irqsave(&sunsu_serio_lock, flags); 10298c2ecf20Sopenharmony_ci up->serio_open = 0; 10308c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&sunsu_serio_lock, flags); 10318c2ecf20Sopenharmony_ci} 10328c2ecf20Sopenharmony_ci 10338c2ecf20Sopenharmony_ci#endif /* CONFIG_SERIO */ 10348c2ecf20Sopenharmony_ci 10358c2ecf20Sopenharmony_cistatic void sunsu_autoconfig(struct uart_sunsu_port *up) 10368c2ecf20Sopenharmony_ci{ 10378c2ecf20Sopenharmony_ci unsigned char status1, status2, scratch, scratch2, scratch3; 10388c2ecf20Sopenharmony_ci unsigned char save_lcr, save_mcr; 10398c2ecf20Sopenharmony_ci unsigned long flags; 10408c2ecf20Sopenharmony_ci 10418c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_NONE) 10428c2ecf20Sopenharmony_ci return; 10438c2ecf20Sopenharmony_ci 10448c2ecf20Sopenharmony_ci up->type_probed = PORT_UNKNOWN; 10458c2ecf20Sopenharmony_ci up->port.iotype = UPIO_MEM; 10468c2ecf20Sopenharmony_ci 10478c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 10488c2ecf20Sopenharmony_ci 10498c2ecf20Sopenharmony_ci if (!(up->port.flags & UPF_BUGGY_UART)) { 10508c2ecf20Sopenharmony_ci /* 10518c2ecf20Sopenharmony_ci * Do a simple existence test first; if we fail this, there's 10528c2ecf20Sopenharmony_ci * no point trying anything else. 10538c2ecf20Sopenharmony_ci * 10548c2ecf20Sopenharmony_ci * 0x80 is used as a nonsense port to prevent against false 10558c2ecf20Sopenharmony_ci * positives due to ISA bus float. The assumption is that 10568c2ecf20Sopenharmony_ci * 0x80 is a non-existent port; which should be safe since 10578c2ecf20Sopenharmony_ci * include/asm/io.h also makes this assumption. 10588c2ecf20Sopenharmony_ci */ 10598c2ecf20Sopenharmony_ci scratch = serial_inp(up, UART_IER); 10608c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, 0); 10618c2ecf20Sopenharmony_ci#ifdef __i386__ 10628c2ecf20Sopenharmony_ci outb(0xff, 0x080); 10638c2ecf20Sopenharmony_ci#endif 10648c2ecf20Sopenharmony_ci scratch2 = serial_inp(up, UART_IER); 10658c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, 0x0f); 10668c2ecf20Sopenharmony_ci#ifdef __i386__ 10678c2ecf20Sopenharmony_ci outb(0, 0x080); 10688c2ecf20Sopenharmony_ci#endif 10698c2ecf20Sopenharmony_ci scratch3 = serial_inp(up, UART_IER); 10708c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, scratch); 10718c2ecf20Sopenharmony_ci if (scratch2 != 0 || scratch3 != 0x0F) 10728c2ecf20Sopenharmony_ci goto out; /* We failed; there's nothing here */ 10738c2ecf20Sopenharmony_ci } 10748c2ecf20Sopenharmony_ci 10758c2ecf20Sopenharmony_ci save_mcr = serial_in(up, UART_MCR); 10768c2ecf20Sopenharmony_ci save_lcr = serial_in(up, UART_LCR); 10778c2ecf20Sopenharmony_ci 10788c2ecf20Sopenharmony_ci /* 10798c2ecf20Sopenharmony_ci * Check to see if a UART is really there. Certain broken 10808c2ecf20Sopenharmony_ci * internal modems based on the Rockwell chipset fail this 10818c2ecf20Sopenharmony_ci * test, because they apparently don't implement the loopback 10828c2ecf20Sopenharmony_ci * test mode. So this test is skipped on the COM 1 through 10838c2ecf20Sopenharmony_ci * COM 4 ports. This *should* be safe, since no board 10848c2ecf20Sopenharmony_ci * manufacturer would be stupid enough to design a board 10858c2ecf20Sopenharmony_ci * that conflicts with COM 1-4 --- we hope! 10868c2ecf20Sopenharmony_ci */ 10878c2ecf20Sopenharmony_ci if (!(up->port.flags & UPF_SKIP_TEST)) { 10888c2ecf20Sopenharmony_ci serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); 10898c2ecf20Sopenharmony_ci status1 = serial_inp(up, UART_MSR) & 0xF0; 10908c2ecf20Sopenharmony_ci serial_outp(up, UART_MCR, save_mcr); 10918c2ecf20Sopenharmony_ci if (status1 != 0x90) 10928c2ecf20Sopenharmony_ci goto out; /* We failed loopback test */ 10938c2ecf20Sopenharmony_ci } 10948c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */ 10958c2ecf20Sopenharmony_ci serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */ 10968c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0); 10978c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 10988c2ecf20Sopenharmony_ci scratch = serial_in(up, UART_IIR) >> 6; 10998c2ecf20Sopenharmony_ci switch (scratch) { 11008c2ecf20Sopenharmony_ci case 0: 11018c2ecf20Sopenharmony_ci up->port.type = PORT_16450; 11028c2ecf20Sopenharmony_ci break; 11038c2ecf20Sopenharmony_ci case 1: 11048c2ecf20Sopenharmony_ci up->port.type = PORT_UNKNOWN; 11058c2ecf20Sopenharmony_ci break; 11068c2ecf20Sopenharmony_ci case 2: 11078c2ecf20Sopenharmony_ci up->port.type = PORT_16550; 11088c2ecf20Sopenharmony_ci break; 11098c2ecf20Sopenharmony_ci case 3: 11108c2ecf20Sopenharmony_ci up->port.type = PORT_16550A; 11118c2ecf20Sopenharmony_ci break; 11128c2ecf20Sopenharmony_ci } 11138c2ecf20Sopenharmony_ci if (up->port.type == PORT_16550A) { 11148c2ecf20Sopenharmony_ci /* Check for Startech UART's */ 11158c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, UART_LCR_DLAB); 11168c2ecf20Sopenharmony_ci if (serial_in(up, UART_EFR) == 0) { 11178c2ecf20Sopenharmony_ci up->port.type = PORT_16650; 11188c2ecf20Sopenharmony_ci } else { 11198c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0xBF); 11208c2ecf20Sopenharmony_ci if (serial_in(up, UART_EFR) == 0) 11218c2ecf20Sopenharmony_ci up->port.type = PORT_16650V2; 11228c2ecf20Sopenharmony_ci } 11238c2ecf20Sopenharmony_ci } 11248c2ecf20Sopenharmony_ci if (up->port.type == PORT_16550A) { 11258c2ecf20Sopenharmony_ci /* Check for TI 16750 */ 11268c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB); 11278c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, 11288c2ecf20Sopenharmony_ci UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 11298c2ecf20Sopenharmony_ci scratch = serial_in(up, UART_IIR) >> 5; 11308c2ecf20Sopenharmony_ci if (scratch == 7) { 11318c2ecf20Sopenharmony_ci /* 11328c2ecf20Sopenharmony_ci * If this is a 16750, and not a cheap UART 11338c2ecf20Sopenharmony_ci * clone, then it should only go into 64 byte 11348c2ecf20Sopenharmony_ci * mode if the UART_FCR7_64BYTE bit was set 11358c2ecf20Sopenharmony_ci * while UART_LCR_DLAB was latched. 11368c2ecf20Sopenharmony_ci */ 11378c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 11388c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, 0); 11398c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, 11408c2ecf20Sopenharmony_ci UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 11418c2ecf20Sopenharmony_ci scratch = serial_in(up, UART_IIR) >> 5; 11428c2ecf20Sopenharmony_ci if (scratch == 6) 11438c2ecf20Sopenharmony_ci up->port.type = PORT_16750; 11448c2ecf20Sopenharmony_ci } 11458c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 11468c2ecf20Sopenharmony_ci } 11478c2ecf20Sopenharmony_ci serial_outp(up, UART_LCR, save_lcr); 11488c2ecf20Sopenharmony_ci if (up->port.type == PORT_16450) { 11498c2ecf20Sopenharmony_ci scratch = serial_in(up, UART_SCR); 11508c2ecf20Sopenharmony_ci serial_outp(up, UART_SCR, 0xa5); 11518c2ecf20Sopenharmony_ci status1 = serial_in(up, UART_SCR); 11528c2ecf20Sopenharmony_ci serial_outp(up, UART_SCR, 0x5a); 11538c2ecf20Sopenharmony_ci status2 = serial_in(up, UART_SCR); 11548c2ecf20Sopenharmony_ci serial_outp(up, UART_SCR, scratch); 11558c2ecf20Sopenharmony_ci 11568c2ecf20Sopenharmony_ci if ((status1 != 0xa5) || (status2 != 0x5a)) 11578c2ecf20Sopenharmony_ci up->port.type = PORT_8250; 11588c2ecf20Sopenharmony_ci } 11598c2ecf20Sopenharmony_ci 11608c2ecf20Sopenharmony_ci up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; 11618c2ecf20Sopenharmony_ci 11628c2ecf20Sopenharmony_ci if (up->port.type == PORT_UNKNOWN) 11638c2ecf20Sopenharmony_ci goto out; 11648c2ecf20Sopenharmony_ci up->type_probed = up->port.type; /* XXX */ 11658c2ecf20Sopenharmony_ci 11668c2ecf20Sopenharmony_ci /* 11678c2ecf20Sopenharmony_ci * Reset the UART. 11688c2ecf20Sopenharmony_ci */ 11698c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_8250_RSA 11708c2ecf20Sopenharmony_ci if (up->port.type == PORT_RSA) 11718c2ecf20Sopenharmony_ci serial_outp(up, UART_RSA_FRR, 0); 11728c2ecf20Sopenharmony_ci#endif 11738c2ecf20Sopenharmony_ci serial_outp(up, UART_MCR, save_mcr); 11748c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO | 11758c2ecf20Sopenharmony_ci UART_FCR_CLEAR_RCVR | 11768c2ecf20Sopenharmony_ci UART_FCR_CLEAR_XMIT)); 11778c2ecf20Sopenharmony_ci serial_outp(up, UART_FCR, 0); 11788c2ecf20Sopenharmony_ci (void)serial_in(up, UART_RX); 11798c2ecf20Sopenharmony_ci serial_outp(up, UART_IER, 0); 11808c2ecf20Sopenharmony_ci 11818c2ecf20Sopenharmony_ciout: 11828c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 11838c2ecf20Sopenharmony_ci} 11848c2ecf20Sopenharmony_ci 11858c2ecf20Sopenharmony_cistatic struct uart_driver sunsu_reg = { 11868c2ecf20Sopenharmony_ci .owner = THIS_MODULE, 11878c2ecf20Sopenharmony_ci .driver_name = "sunsu", 11888c2ecf20Sopenharmony_ci .dev_name = "ttyS", 11898c2ecf20Sopenharmony_ci .major = TTY_MAJOR, 11908c2ecf20Sopenharmony_ci}; 11918c2ecf20Sopenharmony_ci 11928c2ecf20Sopenharmony_cistatic int sunsu_kbd_ms_init(struct uart_sunsu_port *up) 11938c2ecf20Sopenharmony_ci{ 11948c2ecf20Sopenharmony_ci int quot, baud; 11958c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 11968c2ecf20Sopenharmony_ci struct serio *serio; 11978c2ecf20Sopenharmony_ci#endif 11988c2ecf20Sopenharmony_ci 11998c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_KBD) { 12008c2ecf20Sopenharmony_ci up->cflag = B1200 | CS8 | CLOCAL | CREAD; 12018c2ecf20Sopenharmony_ci baud = 1200; 12028c2ecf20Sopenharmony_ci } else { 12038c2ecf20Sopenharmony_ci up->cflag = B4800 | CS8 | CLOCAL | CREAD; 12048c2ecf20Sopenharmony_ci baud = 4800; 12058c2ecf20Sopenharmony_ci } 12068c2ecf20Sopenharmony_ci quot = up->port.uartclk / (16 * baud); 12078c2ecf20Sopenharmony_ci 12088c2ecf20Sopenharmony_ci sunsu_autoconfig(up); 12098c2ecf20Sopenharmony_ci if (up->port.type == PORT_UNKNOWN) 12108c2ecf20Sopenharmony_ci return -ENODEV; 12118c2ecf20Sopenharmony_ci 12128c2ecf20Sopenharmony_ci printk("%pOF: %s port at %llx, irq %u\n", 12138c2ecf20Sopenharmony_ci up->port.dev->of_node, 12148c2ecf20Sopenharmony_ci (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse", 12158c2ecf20Sopenharmony_ci (unsigned long long) up->port.mapbase, 12168c2ecf20Sopenharmony_ci up->port.irq); 12178c2ecf20Sopenharmony_ci 12188c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 12198c2ecf20Sopenharmony_ci serio = &up->serio; 12208c2ecf20Sopenharmony_ci serio->port_data = up; 12218c2ecf20Sopenharmony_ci 12228c2ecf20Sopenharmony_ci serio->id.type = SERIO_RS232; 12238c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_KBD) { 12248c2ecf20Sopenharmony_ci serio->id.proto = SERIO_SUNKBD; 12258c2ecf20Sopenharmony_ci strlcpy(serio->name, "sukbd", sizeof(serio->name)); 12268c2ecf20Sopenharmony_ci } else { 12278c2ecf20Sopenharmony_ci serio->id.proto = SERIO_SUN; 12288c2ecf20Sopenharmony_ci serio->id.extra = 1; 12298c2ecf20Sopenharmony_ci strlcpy(serio->name, "sums", sizeof(serio->name)); 12308c2ecf20Sopenharmony_ci } 12318c2ecf20Sopenharmony_ci strlcpy(serio->phys, 12328c2ecf20Sopenharmony_ci (!(up->port.line & 1) ? "su/serio0" : "su/serio1"), 12338c2ecf20Sopenharmony_ci sizeof(serio->phys)); 12348c2ecf20Sopenharmony_ci 12358c2ecf20Sopenharmony_ci serio->write = sunsu_serio_write; 12368c2ecf20Sopenharmony_ci serio->open = sunsu_serio_open; 12378c2ecf20Sopenharmony_ci serio->close = sunsu_serio_close; 12388c2ecf20Sopenharmony_ci serio->dev.parent = up->port.dev; 12398c2ecf20Sopenharmony_ci 12408c2ecf20Sopenharmony_ci serio_register_port(serio); 12418c2ecf20Sopenharmony_ci#endif 12428c2ecf20Sopenharmony_ci 12438c2ecf20Sopenharmony_ci sunsu_change_speed(&up->port, up->cflag, 0, quot); 12448c2ecf20Sopenharmony_ci 12458c2ecf20Sopenharmony_ci sunsu_startup(&up->port); 12468c2ecf20Sopenharmony_ci return 0; 12478c2ecf20Sopenharmony_ci} 12488c2ecf20Sopenharmony_ci 12498c2ecf20Sopenharmony_ci/* 12508c2ecf20Sopenharmony_ci * ------------------------------------------------------------ 12518c2ecf20Sopenharmony_ci * Serial console driver 12528c2ecf20Sopenharmony_ci * ------------------------------------------------------------ 12538c2ecf20Sopenharmony_ci */ 12548c2ecf20Sopenharmony_ci 12558c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIAL_SUNSU_CONSOLE 12568c2ecf20Sopenharmony_ci 12578c2ecf20Sopenharmony_ci#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 12588c2ecf20Sopenharmony_ci 12598c2ecf20Sopenharmony_ci/* 12608c2ecf20Sopenharmony_ci * Wait for transmitter & holding register to empty 12618c2ecf20Sopenharmony_ci */ 12628c2ecf20Sopenharmony_cistatic void wait_for_xmitr(struct uart_sunsu_port *up) 12638c2ecf20Sopenharmony_ci{ 12648c2ecf20Sopenharmony_ci unsigned int status, tmout = 10000; 12658c2ecf20Sopenharmony_ci 12668c2ecf20Sopenharmony_ci /* Wait up to 10ms for the character(s) to be sent. */ 12678c2ecf20Sopenharmony_ci do { 12688c2ecf20Sopenharmony_ci status = serial_in(up, UART_LSR); 12698c2ecf20Sopenharmony_ci 12708c2ecf20Sopenharmony_ci if (status & UART_LSR_BI) 12718c2ecf20Sopenharmony_ci up->lsr_break_flag = UART_LSR_BI; 12728c2ecf20Sopenharmony_ci 12738c2ecf20Sopenharmony_ci if (--tmout == 0) 12748c2ecf20Sopenharmony_ci break; 12758c2ecf20Sopenharmony_ci udelay(1); 12768c2ecf20Sopenharmony_ci } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 12778c2ecf20Sopenharmony_ci 12788c2ecf20Sopenharmony_ci /* Wait up to 1s for flow control if necessary */ 12798c2ecf20Sopenharmony_ci if (up->port.flags & UPF_CONS_FLOW) { 12808c2ecf20Sopenharmony_ci tmout = 1000000; 12818c2ecf20Sopenharmony_ci while (--tmout && 12828c2ecf20Sopenharmony_ci ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 12838c2ecf20Sopenharmony_ci udelay(1); 12848c2ecf20Sopenharmony_ci } 12858c2ecf20Sopenharmony_ci} 12868c2ecf20Sopenharmony_ci 12878c2ecf20Sopenharmony_cistatic void sunsu_console_putchar(struct uart_port *port, int ch) 12888c2ecf20Sopenharmony_ci{ 12898c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = 12908c2ecf20Sopenharmony_ci container_of(port, struct uart_sunsu_port, port); 12918c2ecf20Sopenharmony_ci 12928c2ecf20Sopenharmony_ci wait_for_xmitr(up); 12938c2ecf20Sopenharmony_ci serial_out(up, UART_TX, ch); 12948c2ecf20Sopenharmony_ci} 12958c2ecf20Sopenharmony_ci 12968c2ecf20Sopenharmony_ci/* 12978c2ecf20Sopenharmony_ci * Print a string to the serial port trying not to disturb 12988c2ecf20Sopenharmony_ci * any possible real use of the port... 12998c2ecf20Sopenharmony_ci */ 13008c2ecf20Sopenharmony_cistatic void sunsu_console_write(struct console *co, const char *s, 13018c2ecf20Sopenharmony_ci unsigned int count) 13028c2ecf20Sopenharmony_ci{ 13038c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = &sunsu_ports[co->index]; 13048c2ecf20Sopenharmony_ci unsigned long flags; 13058c2ecf20Sopenharmony_ci unsigned int ier; 13068c2ecf20Sopenharmony_ci int locked = 1; 13078c2ecf20Sopenharmony_ci 13088c2ecf20Sopenharmony_ci if (up->port.sysrq || oops_in_progress) 13098c2ecf20Sopenharmony_ci locked = spin_trylock_irqsave(&up->port.lock, flags); 13108c2ecf20Sopenharmony_ci else 13118c2ecf20Sopenharmony_ci spin_lock_irqsave(&up->port.lock, flags); 13128c2ecf20Sopenharmony_ci 13138c2ecf20Sopenharmony_ci /* 13148c2ecf20Sopenharmony_ci * First save the UER then disable the interrupts 13158c2ecf20Sopenharmony_ci */ 13168c2ecf20Sopenharmony_ci ier = serial_in(up, UART_IER); 13178c2ecf20Sopenharmony_ci serial_out(up, UART_IER, 0); 13188c2ecf20Sopenharmony_ci 13198c2ecf20Sopenharmony_ci uart_console_write(&up->port, s, count, sunsu_console_putchar); 13208c2ecf20Sopenharmony_ci 13218c2ecf20Sopenharmony_ci /* 13228c2ecf20Sopenharmony_ci * Finally, wait for transmitter to become empty 13238c2ecf20Sopenharmony_ci * and restore the IER 13248c2ecf20Sopenharmony_ci */ 13258c2ecf20Sopenharmony_ci wait_for_xmitr(up); 13268c2ecf20Sopenharmony_ci serial_out(up, UART_IER, ier); 13278c2ecf20Sopenharmony_ci 13288c2ecf20Sopenharmony_ci if (locked) 13298c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&up->port.lock, flags); 13308c2ecf20Sopenharmony_ci} 13318c2ecf20Sopenharmony_ci 13328c2ecf20Sopenharmony_ci/* 13338c2ecf20Sopenharmony_ci * Setup initial baud/bits/parity. We do two things here: 13348c2ecf20Sopenharmony_ci * - construct a cflag setting for the first su_open() 13358c2ecf20Sopenharmony_ci * - initialize the serial port 13368c2ecf20Sopenharmony_ci * Return non-zero if we didn't find a serial port. 13378c2ecf20Sopenharmony_ci */ 13388c2ecf20Sopenharmony_cistatic int __init sunsu_console_setup(struct console *co, char *options) 13398c2ecf20Sopenharmony_ci{ 13408c2ecf20Sopenharmony_ci static struct ktermios dummy; 13418c2ecf20Sopenharmony_ci struct ktermios termios; 13428c2ecf20Sopenharmony_ci struct uart_port *port; 13438c2ecf20Sopenharmony_ci 13448c2ecf20Sopenharmony_ci printk("Console: ttyS%d (SU)\n", 13458c2ecf20Sopenharmony_ci (sunsu_reg.minor - 64) + co->index); 13468c2ecf20Sopenharmony_ci 13478c2ecf20Sopenharmony_ci if (co->index > nr_inst) 13488c2ecf20Sopenharmony_ci return -ENODEV; 13498c2ecf20Sopenharmony_ci port = &sunsu_ports[co->index].port; 13508c2ecf20Sopenharmony_ci 13518c2ecf20Sopenharmony_ci /* 13528c2ecf20Sopenharmony_ci * Temporary fix. 13538c2ecf20Sopenharmony_ci */ 13548c2ecf20Sopenharmony_ci spin_lock_init(&port->lock); 13558c2ecf20Sopenharmony_ci 13568c2ecf20Sopenharmony_ci /* Get firmware console settings. */ 13578c2ecf20Sopenharmony_ci sunserial_console_termios(co, port->dev->of_node); 13588c2ecf20Sopenharmony_ci 13598c2ecf20Sopenharmony_ci memset(&termios, 0, sizeof(struct ktermios)); 13608c2ecf20Sopenharmony_ci termios.c_cflag = co->cflag; 13618c2ecf20Sopenharmony_ci port->mctrl |= TIOCM_DTR; 13628c2ecf20Sopenharmony_ci port->ops->set_termios(port, &termios, &dummy); 13638c2ecf20Sopenharmony_ci 13648c2ecf20Sopenharmony_ci return 0; 13658c2ecf20Sopenharmony_ci} 13668c2ecf20Sopenharmony_ci 13678c2ecf20Sopenharmony_cistatic struct console sunsu_console = { 13688c2ecf20Sopenharmony_ci .name = "ttyS", 13698c2ecf20Sopenharmony_ci .write = sunsu_console_write, 13708c2ecf20Sopenharmony_ci .device = uart_console_device, 13718c2ecf20Sopenharmony_ci .setup = sunsu_console_setup, 13728c2ecf20Sopenharmony_ci .flags = CON_PRINTBUFFER, 13738c2ecf20Sopenharmony_ci .index = -1, 13748c2ecf20Sopenharmony_ci .data = &sunsu_reg, 13758c2ecf20Sopenharmony_ci}; 13768c2ecf20Sopenharmony_ci 13778c2ecf20Sopenharmony_ci/* 13788c2ecf20Sopenharmony_ci * Register console. 13798c2ecf20Sopenharmony_ci */ 13808c2ecf20Sopenharmony_ci 13818c2ecf20Sopenharmony_cistatic inline struct console *SUNSU_CONSOLE(void) 13828c2ecf20Sopenharmony_ci{ 13838c2ecf20Sopenharmony_ci return &sunsu_console; 13848c2ecf20Sopenharmony_ci} 13858c2ecf20Sopenharmony_ci#else 13868c2ecf20Sopenharmony_ci#define SUNSU_CONSOLE() (NULL) 13878c2ecf20Sopenharmony_ci#define sunsu_serial_console_init() do { } while (0) 13888c2ecf20Sopenharmony_ci#endif 13898c2ecf20Sopenharmony_ci 13908c2ecf20Sopenharmony_cistatic enum su_type su_get_type(struct device_node *dp) 13918c2ecf20Sopenharmony_ci{ 13928c2ecf20Sopenharmony_ci struct device_node *ap = of_find_node_by_path("/aliases"); 13938c2ecf20Sopenharmony_ci enum su_type rc = SU_PORT_PORT; 13948c2ecf20Sopenharmony_ci 13958c2ecf20Sopenharmony_ci if (ap) { 13968c2ecf20Sopenharmony_ci const char *keyb = of_get_property(ap, "keyboard", NULL); 13978c2ecf20Sopenharmony_ci const char *ms = of_get_property(ap, "mouse", NULL); 13988c2ecf20Sopenharmony_ci struct device_node *match; 13998c2ecf20Sopenharmony_ci 14008c2ecf20Sopenharmony_ci if (keyb) { 14018c2ecf20Sopenharmony_ci match = of_find_node_by_path(keyb); 14028c2ecf20Sopenharmony_ci 14038c2ecf20Sopenharmony_ci /* 14048c2ecf20Sopenharmony_ci * The pointer is used as an identifier not 14058c2ecf20Sopenharmony_ci * as a pointer, we can drop the refcount on 14068c2ecf20Sopenharmony_ci * the of__node immediately after getting it. 14078c2ecf20Sopenharmony_ci */ 14088c2ecf20Sopenharmony_ci of_node_put(match); 14098c2ecf20Sopenharmony_ci 14108c2ecf20Sopenharmony_ci if (dp == match) { 14118c2ecf20Sopenharmony_ci rc = SU_PORT_KBD; 14128c2ecf20Sopenharmony_ci goto out; 14138c2ecf20Sopenharmony_ci } 14148c2ecf20Sopenharmony_ci } 14158c2ecf20Sopenharmony_ci if (ms) { 14168c2ecf20Sopenharmony_ci match = of_find_node_by_path(ms); 14178c2ecf20Sopenharmony_ci 14188c2ecf20Sopenharmony_ci of_node_put(match); 14198c2ecf20Sopenharmony_ci 14208c2ecf20Sopenharmony_ci if (dp == match) { 14218c2ecf20Sopenharmony_ci rc = SU_PORT_MS; 14228c2ecf20Sopenharmony_ci goto out; 14238c2ecf20Sopenharmony_ci } 14248c2ecf20Sopenharmony_ci } 14258c2ecf20Sopenharmony_ci } 14268c2ecf20Sopenharmony_ci 14278c2ecf20Sopenharmony_ciout: 14288c2ecf20Sopenharmony_ci of_node_put(ap); 14298c2ecf20Sopenharmony_ci return rc; 14308c2ecf20Sopenharmony_ci} 14318c2ecf20Sopenharmony_ci 14328c2ecf20Sopenharmony_cistatic int su_probe(struct platform_device *op) 14338c2ecf20Sopenharmony_ci{ 14348c2ecf20Sopenharmony_ci struct device_node *dp = op->dev.of_node; 14358c2ecf20Sopenharmony_ci struct uart_sunsu_port *up; 14368c2ecf20Sopenharmony_ci struct resource *rp; 14378c2ecf20Sopenharmony_ci enum su_type type; 14388c2ecf20Sopenharmony_ci bool ignore_line; 14398c2ecf20Sopenharmony_ci int err; 14408c2ecf20Sopenharmony_ci 14418c2ecf20Sopenharmony_ci type = su_get_type(dp); 14428c2ecf20Sopenharmony_ci if (type == SU_PORT_PORT) { 14438c2ecf20Sopenharmony_ci if (nr_inst >= UART_NR) 14448c2ecf20Sopenharmony_ci return -EINVAL; 14458c2ecf20Sopenharmony_ci up = &sunsu_ports[nr_inst]; 14468c2ecf20Sopenharmony_ci } else { 14478c2ecf20Sopenharmony_ci up = kzalloc(sizeof(*up), GFP_KERNEL); 14488c2ecf20Sopenharmony_ci if (!up) 14498c2ecf20Sopenharmony_ci return -ENOMEM; 14508c2ecf20Sopenharmony_ci } 14518c2ecf20Sopenharmony_ci 14528c2ecf20Sopenharmony_ci up->port.line = nr_inst; 14538c2ecf20Sopenharmony_ci 14548c2ecf20Sopenharmony_ci spin_lock_init(&up->port.lock); 14558c2ecf20Sopenharmony_ci 14568c2ecf20Sopenharmony_ci up->su_type = type; 14578c2ecf20Sopenharmony_ci 14588c2ecf20Sopenharmony_ci rp = &op->resource[0]; 14598c2ecf20Sopenharmony_ci up->port.mapbase = rp->start; 14608c2ecf20Sopenharmony_ci up->reg_size = resource_size(rp); 14618c2ecf20Sopenharmony_ci up->port.membase = of_ioremap(rp, 0, up->reg_size, "su"); 14628c2ecf20Sopenharmony_ci if (!up->port.membase) { 14638c2ecf20Sopenharmony_ci if (type != SU_PORT_PORT) 14648c2ecf20Sopenharmony_ci kfree(up); 14658c2ecf20Sopenharmony_ci return -ENOMEM; 14668c2ecf20Sopenharmony_ci } 14678c2ecf20Sopenharmony_ci 14688c2ecf20Sopenharmony_ci up->port.irq = op->archdata.irqs[0]; 14698c2ecf20Sopenharmony_ci 14708c2ecf20Sopenharmony_ci up->port.dev = &op->dev; 14718c2ecf20Sopenharmony_ci 14728c2ecf20Sopenharmony_ci up->port.type = PORT_UNKNOWN; 14738c2ecf20Sopenharmony_ci up->port.uartclk = (SU_BASE_BAUD * 16); 14748c2ecf20Sopenharmony_ci up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSU_CONSOLE); 14758c2ecf20Sopenharmony_ci 14768c2ecf20Sopenharmony_ci err = 0; 14778c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) { 14788c2ecf20Sopenharmony_ci err = sunsu_kbd_ms_init(up); 14798c2ecf20Sopenharmony_ci if (err) { 14808c2ecf20Sopenharmony_ci of_iounmap(&op->resource[0], 14818c2ecf20Sopenharmony_ci up->port.membase, up->reg_size); 14828c2ecf20Sopenharmony_ci kfree(up); 14838c2ecf20Sopenharmony_ci return err; 14848c2ecf20Sopenharmony_ci } 14858c2ecf20Sopenharmony_ci platform_set_drvdata(op, up); 14868c2ecf20Sopenharmony_ci 14878c2ecf20Sopenharmony_ci nr_inst++; 14888c2ecf20Sopenharmony_ci 14898c2ecf20Sopenharmony_ci return 0; 14908c2ecf20Sopenharmony_ci } 14918c2ecf20Sopenharmony_ci 14928c2ecf20Sopenharmony_ci up->port.flags |= UPF_BOOT_AUTOCONF; 14938c2ecf20Sopenharmony_ci 14948c2ecf20Sopenharmony_ci sunsu_autoconfig(up); 14958c2ecf20Sopenharmony_ci 14968c2ecf20Sopenharmony_ci err = -ENODEV; 14978c2ecf20Sopenharmony_ci if (up->port.type == PORT_UNKNOWN) 14988c2ecf20Sopenharmony_ci goto out_unmap; 14998c2ecf20Sopenharmony_ci 15008c2ecf20Sopenharmony_ci up->port.ops = &sunsu_pops; 15018c2ecf20Sopenharmony_ci 15028c2ecf20Sopenharmony_ci ignore_line = false; 15038c2ecf20Sopenharmony_ci if (of_node_name_eq(dp, "rsc-console") || 15048c2ecf20Sopenharmony_ci of_node_name_eq(dp, "lom-console")) 15058c2ecf20Sopenharmony_ci ignore_line = true; 15068c2ecf20Sopenharmony_ci 15078c2ecf20Sopenharmony_ci sunserial_console_match(SUNSU_CONSOLE(), dp, 15088c2ecf20Sopenharmony_ci &sunsu_reg, up->port.line, 15098c2ecf20Sopenharmony_ci ignore_line); 15108c2ecf20Sopenharmony_ci err = uart_add_one_port(&sunsu_reg, &up->port); 15118c2ecf20Sopenharmony_ci if (err) 15128c2ecf20Sopenharmony_ci goto out_unmap; 15138c2ecf20Sopenharmony_ci 15148c2ecf20Sopenharmony_ci platform_set_drvdata(op, up); 15158c2ecf20Sopenharmony_ci 15168c2ecf20Sopenharmony_ci nr_inst++; 15178c2ecf20Sopenharmony_ci 15188c2ecf20Sopenharmony_ci return 0; 15198c2ecf20Sopenharmony_ci 15208c2ecf20Sopenharmony_ciout_unmap: 15218c2ecf20Sopenharmony_ci of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 15228c2ecf20Sopenharmony_ci kfree(up); 15238c2ecf20Sopenharmony_ci return err; 15248c2ecf20Sopenharmony_ci} 15258c2ecf20Sopenharmony_ci 15268c2ecf20Sopenharmony_cistatic int su_remove(struct platform_device *op) 15278c2ecf20Sopenharmony_ci{ 15288c2ecf20Sopenharmony_ci struct uart_sunsu_port *up = platform_get_drvdata(op); 15298c2ecf20Sopenharmony_ci bool kbdms = false; 15308c2ecf20Sopenharmony_ci 15318c2ecf20Sopenharmony_ci if (up->su_type == SU_PORT_MS || 15328c2ecf20Sopenharmony_ci up->su_type == SU_PORT_KBD) 15338c2ecf20Sopenharmony_ci kbdms = true; 15348c2ecf20Sopenharmony_ci 15358c2ecf20Sopenharmony_ci if (kbdms) { 15368c2ecf20Sopenharmony_ci#ifdef CONFIG_SERIO 15378c2ecf20Sopenharmony_ci serio_unregister_port(&up->serio); 15388c2ecf20Sopenharmony_ci#endif 15398c2ecf20Sopenharmony_ci } else if (up->port.type != PORT_UNKNOWN) 15408c2ecf20Sopenharmony_ci uart_remove_one_port(&sunsu_reg, &up->port); 15418c2ecf20Sopenharmony_ci 15428c2ecf20Sopenharmony_ci if (up->port.membase) 15438c2ecf20Sopenharmony_ci of_iounmap(&op->resource[0], up->port.membase, up->reg_size); 15448c2ecf20Sopenharmony_ci 15458c2ecf20Sopenharmony_ci if (kbdms) 15468c2ecf20Sopenharmony_ci kfree(up); 15478c2ecf20Sopenharmony_ci 15488c2ecf20Sopenharmony_ci return 0; 15498c2ecf20Sopenharmony_ci} 15508c2ecf20Sopenharmony_ci 15518c2ecf20Sopenharmony_cistatic const struct of_device_id su_match[] = { 15528c2ecf20Sopenharmony_ci { 15538c2ecf20Sopenharmony_ci .name = "su", 15548c2ecf20Sopenharmony_ci }, 15558c2ecf20Sopenharmony_ci { 15568c2ecf20Sopenharmony_ci .name = "su_pnp", 15578c2ecf20Sopenharmony_ci }, 15588c2ecf20Sopenharmony_ci { 15598c2ecf20Sopenharmony_ci .name = "serial", 15608c2ecf20Sopenharmony_ci .compatible = "su", 15618c2ecf20Sopenharmony_ci }, 15628c2ecf20Sopenharmony_ci { 15638c2ecf20Sopenharmony_ci .type = "serial", 15648c2ecf20Sopenharmony_ci .compatible = "su", 15658c2ecf20Sopenharmony_ci }, 15668c2ecf20Sopenharmony_ci {}, 15678c2ecf20Sopenharmony_ci}; 15688c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, su_match); 15698c2ecf20Sopenharmony_ci 15708c2ecf20Sopenharmony_cistatic struct platform_driver su_driver = { 15718c2ecf20Sopenharmony_ci .driver = { 15728c2ecf20Sopenharmony_ci .name = "su", 15738c2ecf20Sopenharmony_ci .of_match_table = su_match, 15748c2ecf20Sopenharmony_ci }, 15758c2ecf20Sopenharmony_ci .probe = su_probe, 15768c2ecf20Sopenharmony_ci .remove = su_remove, 15778c2ecf20Sopenharmony_ci}; 15788c2ecf20Sopenharmony_ci 15798c2ecf20Sopenharmony_cistatic int __init sunsu_init(void) 15808c2ecf20Sopenharmony_ci{ 15818c2ecf20Sopenharmony_ci struct device_node *dp; 15828c2ecf20Sopenharmony_ci int err; 15838c2ecf20Sopenharmony_ci int num_uart = 0; 15848c2ecf20Sopenharmony_ci 15858c2ecf20Sopenharmony_ci for_each_node_by_name(dp, "su") { 15868c2ecf20Sopenharmony_ci if (su_get_type(dp) == SU_PORT_PORT) 15878c2ecf20Sopenharmony_ci num_uart++; 15888c2ecf20Sopenharmony_ci } 15898c2ecf20Sopenharmony_ci for_each_node_by_name(dp, "su_pnp") { 15908c2ecf20Sopenharmony_ci if (su_get_type(dp) == SU_PORT_PORT) 15918c2ecf20Sopenharmony_ci num_uart++; 15928c2ecf20Sopenharmony_ci } 15938c2ecf20Sopenharmony_ci for_each_node_by_name(dp, "serial") { 15948c2ecf20Sopenharmony_ci if (of_device_is_compatible(dp, "su")) { 15958c2ecf20Sopenharmony_ci if (su_get_type(dp) == SU_PORT_PORT) 15968c2ecf20Sopenharmony_ci num_uart++; 15978c2ecf20Sopenharmony_ci } 15988c2ecf20Sopenharmony_ci } 15998c2ecf20Sopenharmony_ci for_each_node_by_type(dp, "serial") { 16008c2ecf20Sopenharmony_ci if (of_device_is_compatible(dp, "su")) { 16018c2ecf20Sopenharmony_ci if (su_get_type(dp) == SU_PORT_PORT) 16028c2ecf20Sopenharmony_ci num_uart++; 16038c2ecf20Sopenharmony_ci } 16048c2ecf20Sopenharmony_ci } 16058c2ecf20Sopenharmony_ci 16068c2ecf20Sopenharmony_ci if (num_uart) { 16078c2ecf20Sopenharmony_ci err = sunserial_register_minors(&sunsu_reg, num_uart); 16088c2ecf20Sopenharmony_ci if (err) 16098c2ecf20Sopenharmony_ci return err; 16108c2ecf20Sopenharmony_ci } 16118c2ecf20Sopenharmony_ci 16128c2ecf20Sopenharmony_ci err = platform_driver_register(&su_driver); 16138c2ecf20Sopenharmony_ci if (err && num_uart) 16148c2ecf20Sopenharmony_ci sunserial_unregister_minors(&sunsu_reg, num_uart); 16158c2ecf20Sopenharmony_ci 16168c2ecf20Sopenharmony_ci return err; 16178c2ecf20Sopenharmony_ci} 16188c2ecf20Sopenharmony_ci 16198c2ecf20Sopenharmony_cistatic void __exit sunsu_exit(void) 16208c2ecf20Sopenharmony_ci{ 16218c2ecf20Sopenharmony_ci platform_driver_unregister(&su_driver); 16228c2ecf20Sopenharmony_ci if (sunsu_reg.nr) 16238c2ecf20Sopenharmony_ci sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr); 16248c2ecf20Sopenharmony_ci} 16258c2ecf20Sopenharmony_ci 16268c2ecf20Sopenharmony_cimodule_init(sunsu_init); 16278c2ecf20Sopenharmony_cimodule_exit(sunsu_exit); 16288c2ecf20Sopenharmony_ci 16298c2ecf20Sopenharmony_ciMODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller"); 16308c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Sun SU serial port driver"); 16318c2ecf20Sopenharmony_ciMODULE_VERSION("2.0"); 16328c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 1633