1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11#include <linux/clk.h> 12#include <linux/console.h> 13#include <linux/delay.h> 14#include <linux/dma-direction.h> 15#include <linux/dmaengine.h> 16#include <linux/dma-mapping.h> 17#include <linux/io.h> 18#include <linux/iopoll.h> 19#include <linux/irq.h> 20#include <linux/module.h> 21#include <linux/of.h> 22#include <linux/of_platform.h> 23#include <linux/pinctrl/consumer.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26#include <linux/pm_wakeirq.h> 27#include <linux/serial_core.h> 28#include <linux/serial.h> 29#include <linux/spinlock.h> 30#include <linux/sysrq.h> 31#include <linux/tty_flip.h> 32#include <linux/tty.h> 33 34#include "serial_mctrl_gpio.h" 35#include "stm32-usart.h" 36 37static void stm32_usart_stop_tx(struct uart_port *port); 38static void stm32_usart_transmit_chars(struct uart_port *port); 39 40static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41{ 42 return container_of(port, struct stm32_port, port); 43} 44 45static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 46{ 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52} 53 54static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55{ 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61} 62 63static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 64 u32 delay_DDE, u32 baud) 65{ 66 u32 rs485_deat_dedt; 67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 68 bool over8; 69 70 *cr3 |= USART_CR3_DEM; 71 over8 = *cr1 & USART_CR1_OVER8; 72 73 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 74 75 if (over8) 76 rs485_deat_dedt = delay_ADE * baud * 8; 77 else 78 rs485_deat_dedt = delay_ADE * baud * 16; 79 80 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 81 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 82 rs485_deat_dedt_max : rs485_deat_dedt; 83 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 84 USART_CR1_DEAT_MASK; 85 *cr1 |= rs485_deat_dedt; 86 87 if (over8) 88 rs485_deat_dedt = delay_DDE * baud * 8; 89 else 90 rs485_deat_dedt = delay_DDE * baud * 16; 91 92 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 93 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 94 rs485_deat_dedt_max : rs485_deat_dedt; 95 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 96 USART_CR1_DEDT_MASK; 97 *cr1 |= rs485_deat_dedt; 98} 99 100static int stm32_usart_config_rs485(struct uart_port *port, 101 struct serial_rs485 *rs485conf) 102{ 103 struct stm32_port *stm32_port = to_stm32_port(port); 104 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 105 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 106 u32 usartdiv, baud, cr1, cr3; 107 bool over8; 108 109 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 110 111 port->rs485 = *rs485conf; 112 113 rs485conf->flags |= SER_RS485_RX_DURING_TX; 114 115 if (rs485conf->flags & SER_RS485_ENABLED) { 116 cr1 = readl_relaxed(port->membase + ofs->cr1); 117 cr3 = readl_relaxed(port->membase + ofs->cr3); 118 usartdiv = readl_relaxed(port->membase + ofs->brr); 119 usartdiv = usartdiv & GENMASK(15, 0); 120 over8 = cr1 & USART_CR1_OVER8; 121 122 if (over8) 123 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 124 << USART_BRR_04_R_SHIFT; 125 126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 127 stm32_usart_config_reg_rs485(&cr1, &cr3, 128 rs485conf->delay_rts_before_send, 129 rs485conf->delay_rts_after_send, 130 baud); 131 132 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 133 cr3 &= ~USART_CR3_DEP; 134 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 135 } else { 136 cr3 |= USART_CR3_DEP; 137 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 138 } 139 140 writel_relaxed(cr3, port->membase + ofs->cr3); 141 writel_relaxed(cr1, port->membase + ofs->cr1); 142 } else { 143 stm32_usart_clr_bits(port, ofs->cr3, 144 USART_CR3_DEM | USART_CR3_DEP); 145 stm32_usart_clr_bits(port, ofs->cr1, 146 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 147 } 148 149 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 150 151 return 0; 152} 153 154static int stm32_usart_init_rs485(struct uart_port *port, 155 struct platform_device *pdev) 156{ 157 struct serial_rs485 *rs485conf = &port->rs485; 158 159 rs485conf->flags = 0; 160 rs485conf->delay_rts_before_send = 0; 161 rs485conf->delay_rts_after_send = 0; 162 163 if (!pdev->dev.of_node) 164 return -ENODEV; 165 166 return uart_get_rs485_mode(port); 167} 168 169static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 170 int *last_res, bool threaded) 171{ 172 struct stm32_port *stm32_port = to_stm32_port(port); 173 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 174 enum dma_status status; 175 struct dma_tx_state state; 176 177 *sr = readl_relaxed(port->membase + ofs->isr); 178 179 if (threaded && stm32_port->rx_ch) { 180 status = dmaengine_tx_status(stm32_port->rx_ch, 181 stm32_port->rx_ch->cookie, 182 &state); 183 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 184 return 1; 185 else 186 return 0; 187 } else if (*sr & USART_SR_RXNE) { 188 return 1; 189 } 190 return 0; 191} 192 193static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 194 int *last_res) 195{ 196 struct stm32_port *stm32_port = to_stm32_port(port); 197 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 198 unsigned long c; 199 200 if (stm32_port->rx_ch) { 201 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 202 if ((*last_res) == 0) 203 *last_res = RX_BUF_L; 204 } else { 205 c = readl_relaxed(port->membase + ofs->rdr); 206 /* apply RDR data mask */ 207 c &= stm32_port->rdr_mask; 208 } 209 210 return c; 211} 212 213static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 214{ 215 struct tty_port *tport = &port->state->port; 216 struct stm32_port *stm32_port = to_stm32_port(port); 217 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 218 unsigned long c; 219 u32 sr; 220 char flag; 221 222 spin_lock(&port->lock); 223 224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 225 threaded)) { 226 sr |= USART_SR_DUMMY_RX; 227 flag = TTY_NORMAL; 228 229 /* 230 * Status bits has to be cleared before reading the RDR: 231 * In FIFO mode, reading the RDR will pop the next data 232 * (if any) along with its status bits into the SR. 233 * Not doing so leads to misalignement between RDR and SR, 234 * and clear status bits of the next rx data. 235 * 236 * Clear errors flags for stm32f7 and stm32h7 compatible 237 * devices. On stm32f4 compatible devices, the error bit is 238 * cleared by the sequence [read SR - read DR]. 239 */ 240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 241 writel_relaxed(sr & USART_SR_ERR_MASK, 242 port->membase + ofs->icr); 243 244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 245 port->icount.rx++; 246 if (sr & USART_SR_ERR_MASK) { 247 if (sr & USART_SR_ORE) { 248 port->icount.overrun++; 249 } else if (sr & USART_SR_PE) { 250 port->icount.parity++; 251 } else if (sr & USART_SR_FE) { 252 /* Break detection if character is null */ 253 if (!c) { 254 port->icount.brk++; 255 if (uart_handle_break(port)) 256 continue; 257 } else { 258 port->icount.frame++; 259 } 260 } 261 262 sr &= port->read_status_mask; 263 264 if (sr & USART_SR_PE) { 265 flag = TTY_PARITY; 266 } else if (sr & USART_SR_FE) { 267 if (!c) 268 flag = TTY_BREAK; 269 else 270 flag = TTY_FRAME; 271 } 272 } 273 274 if (uart_handle_sysrq_char(port, c)) 275 continue; 276 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 277 } 278 279 spin_unlock(&port->lock); 280 281 tty_flip_buffer_push(tport); 282} 283 284static void stm32_usart_tx_dma_complete(void *arg) 285{ 286 struct uart_port *port = arg; 287 struct stm32_port *stm32port = to_stm32_port(port); 288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 289 unsigned long flags; 290 291 dmaengine_terminate_async(stm32port->tx_ch); 292 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 293 stm32port->tx_dma_busy = false; 294 295 /* Let's see if we have pending data to send */ 296 spin_lock_irqsave(&port->lock, flags); 297 stm32_usart_transmit_chars(port); 298 spin_unlock_irqrestore(&port->lock, flags); 299} 300 301static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 302{ 303 struct stm32_port *stm32_port = to_stm32_port(port); 304 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 305 306 /* 307 * Enables TX FIFO threashold irq when FIFO is enabled, 308 * or TX empty irq when FIFO is disabled 309 */ 310 if (stm32_port->fifoen) 311 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 312 else 313 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 314} 315 316static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 317{ 318 struct stm32_port *stm32_port = to_stm32_port(port); 319 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 320 321 if (stm32_port->fifoen) 322 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 323 else 324 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 325} 326 327static void stm32_usart_transmit_chars_pio(struct uart_port *port) 328{ 329 struct stm32_port *stm32_port = to_stm32_port(port); 330 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 331 struct circ_buf *xmit = &port->state->xmit; 332 333 if (stm32_port->tx_dma_busy) { 334 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 335 stm32_port->tx_dma_busy = false; 336 } 337 338 while (!uart_circ_empty(xmit)) { 339 /* Check that TDR is empty before filling FIFO */ 340 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 341 break; 342 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 344 port->icount.tx++; 345 } 346 347 /* rely on TXE irq (mask or unmask) for sending remaining data */ 348 if (uart_circ_empty(xmit)) 349 stm32_usart_tx_interrupt_disable(port); 350 else 351 stm32_usart_tx_interrupt_enable(port); 352} 353 354static void stm32_usart_transmit_chars_dma(struct uart_port *port) 355{ 356 struct stm32_port *stm32port = to_stm32_port(port); 357 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 358 struct circ_buf *xmit = &port->state->xmit; 359 struct dma_async_tx_descriptor *desc = NULL; 360 unsigned int count, i; 361 362 if (stm32port->tx_dma_busy) 363 return; 364 365 stm32port->tx_dma_busy = true; 366 367 count = uart_circ_chars_pending(xmit); 368 369 if (count > TX_BUF_L) 370 count = TX_BUF_L; 371 372 if (xmit->tail < xmit->head) { 373 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 374 } else { 375 size_t one = UART_XMIT_SIZE - xmit->tail; 376 size_t two; 377 378 if (one > count) 379 one = count; 380 two = count - one; 381 382 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 383 if (two) 384 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 385 } 386 387 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 388 stm32port->tx_dma_buf, 389 count, 390 DMA_MEM_TO_DEV, 391 DMA_PREP_INTERRUPT); 392 393 if (!desc) 394 goto fallback_err; 395 396 desc->callback = stm32_usart_tx_dma_complete; 397 desc->callback_param = port; 398 399 /* Push current DMA TX transaction in the pending queue */ 400 if (dma_submit_error(dmaengine_submit(desc))) { 401 /* dma no yet started, safe to free resources */ 402 dmaengine_terminate_async(stm32port->tx_ch); 403 goto fallback_err; 404 } 405 406 /* Issue pending DMA TX requests */ 407 dma_async_issue_pending(stm32port->tx_ch); 408 409 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 410 411 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 412 port->icount.tx += count; 413 return; 414 415fallback_err: 416 for (i = count; i > 0; i--) 417 stm32_usart_transmit_chars_pio(port); 418} 419 420static void stm32_usart_transmit_chars(struct uart_port *port) 421{ 422 struct stm32_port *stm32_port = to_stm32_port(port); 423 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 424 struct circ_buf *xmit = &port->state->xmit; 425 u32 isr; 426 int ret; 427 428 if (port->x_char) { 429 if (stm32_port->tx_dma_busy) 430 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 431 432 /* Check that TDR is empty before filling FIFO */ 433 ret = 434 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 435 isr, 436 (isr & USART_SR_TXE), 437 10, 1000); 438 if (ret) 439 dev_warn(port->dev, "1 character may be erased\n"); 440 441 writel_relaxed(port->x_char, port->membase + ofs->tdr); 442 port->x_char = 0; 443 port->icount.tx++; 444 if (stm32_port->tx_dma_busy) 445 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 446 return; 447 } 448 449 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 450 stm32_usart_tx_interrupt_disable(port); 451 return; 452 } 453 454 if (ofs->icr == UNDEF_REG) 455 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 456 else 457 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 458 459 if (stm32_port->tx_ch) 460 stm32_usart_transmit_chars_dma(port); 461 else 462 stm32_usart_transmit_chars_pio(port); 463 464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 465 uart_write_wakeup(port); 466 467 if (uart_circ_empty(xmit)) 468 stm32_usart_tx_interrupt_disable(port); 469} 470 471static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 472{ 473 struct uart_port *port = ptr; 474 struct tty_port *tport = &port->state->port; 475 struct stm32_port *stm32_port = to_stm32_port(port); 476 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 477 u32 sr; 478 479 sr = readl_relaxed(port->membase + ofs->isr); 480 481 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 482 writel_relaxed(USART_ICR_RTOCF, 483 port->membase + ofs->icr); 484 485 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 486 /* Clear wake up flag and disable wake up interrupt */ 487 writel_relaxed(USART_ICR_WUCF, 488 port->membase + ofs->icr); 489 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 490 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 491 pm_wakeup_event(tport->tty->dev, 0); 492 } 493 494 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 495 stm32_usart_receive_chars(port, false); 496 497 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 498 spin_lock(&port->lock); 499 stm32_usart_transmit_chars(port); 500 spin_unlock(&port->lock); 501 } 502 503 if (stm32_port->rx_ch) 504 return IRQ_WAKE_THREAD; 505 else 506 return IRQ_HANDLED; 507} 508 509static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 510{ 511 struct uart_port *port = ptr; 512 struct stm32_port *stm32_port = to_stm32_port(port); 513 514 if (stm32_port->rx_ch) 515 stm32_usart_receive_chars(port, true); 516 517 return IRQ_HANDLED; 518} 519 520static unsigned int stm32_usart_tx_empty(struct uart_port *port) 521{ 522 struct stm32_port *stm32_port = to_stm32_port(port); 523 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 524 525 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 526 return TIOCSER_TEMT; 527 528 return 0; 529} 530 531static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 532{ 533 struct stm32_port *stm32_port = to_stm32_port(port); 534 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 535 536 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 537 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 538 else 539 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 540 541 mctrl_gpio_set(stm32_port->gpios, mctrl); 542} 543 544static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 545{ 546 struct stm32_port *stm32_port = to_stm32_port(port); 547 unsigned int ret; 548 549 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 550 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 551 552 return mctrl_gpio_get(stm32_port->gpios, &ret); 553} 554 555static void stm32_usart_enable_ms(struct uart_port *port) 556{ 557 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 558} 559 560static void stm32_usart_disable_ms(struct uart_port *port) 561{ 562 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 563} 564 565/* Transmit stop */ 566static void stm32_usart_stop_tx(struct uart_port *port) 567{ 568 struct stm32_port *stm32_port = to_stm32_port(port); 569 struct serial_rs485 *rs485conf = &port->rs485; 570 571 stm32_usart_tx_interrupt_disable(port); 572 573 if (rs485conf->flags & SER_RS485_ENABLED) { 574 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 575 mctrl_gpio_set(stm32_port->gpios, 576 stm32_port->port.mctrl & ~TIOCM_RTS); 577 } else { 578 mctrl_gpio_set(stm32_port->gpios, 579 stm32_port->port.mctrl | TIOCM_RTS); 580 } 581 } 582} 583 584/* There are probably characters waiting to be transmitted. */ 585static void stm32_usart_start_tx(struct uart_port *port) 586{ 587 struct stm32_port *stm32_port = to_stm32_port(port); 588 struct serial_rs485 *rs485conf = &port->rs485; 589 struct circ_buf *xmit = &port->state->xmit; 590 591 if (uart_circ_empty(xmit) && !port->x_char) 592 return; 593 594 if (rs485conf->flags & SER_RS485_ENABLED) { 595 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 596 mctrl_gpio_set(stm32_port->gpios, 597 stm32_port->port.mctrl | TIOCM_RTS); 598 } else { 599 mctrl_gpio_set(stm32_port->gpios, 600 stm32_port->port.mctrl & ~TIOCM_RTS); 601 } 602 } 603 604 stm32_usart_transmit_chars(port); 605} 606 607/* Throttle the remote when input buffer is about to overflow. */ 608static void stm32_usart_throttle(struct uart_port *port) 609{ 610 struct stm32_port *stm32_port = to_stm32_port(port); 611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 612 unsigned long flags; 613 614 spin_lock_irqsave(&port->lock, flags); 615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 616 if (stm32_port->cr3_irq) 617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 618 619 spin_unlock_irqrestore(&port->lock, flags); 620} 621 622/* Unthrottle the remote, the input buffer can now accept data. */ 623static void stm32_usart_unthrottle(struct uart_port *port) 624{ 625 struct stm32_port *stm32_port = to_stm32_port(port); 626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 627 unsigned long flags; 628 629 spin_lock_irqsave(&port->lock, flags); 630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 631 if (stm32_port->cr3_irq) 632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 633 634 spin_unlock_irqrestore(&port->lock, flags); 635} 636 637/* Receive stop */ 638static void stm32_usart_stop_rx(struct uart_port *port) 639{ 640 struct stm32_port *stm32_port = to_stm32_port(port); 641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 642 643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 644 if (stm32_port->cr3_irq) 645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 646} 647 648/* Handle breaks - ignored by us */ 649static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 650{ 651} 652 653static int stm32_usart_startup(struct uart_port *port) 654{ 655 struct stm32_port *stm32_port = to_stm32_port(port); 656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 658 const char *name = to_platform_device(port->dev)->name; 659 u32 val; 660 int ret; 661 662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 663 stm32_usart_threaded_interrupt, 664 IRQF_ONESHOT | IRQF_NO_SUSPEND, 665 name, port); 666 if (ret) 667 return ret; 668 669 /* RX FIFO Flush */ 670 if (ofs->rqr != UNDEF_REG) 671 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 672 673 /* RX enabling */ 674 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 675 stm32_usart_set_bits(port, ofs->cr1, val); 676 677 return 0; 678} 679 680static void stm32_usart_shutdown(struct uart_port *port) 681{ 682 struct stm32_port *stm32_port = to_stm32_port(port); 683 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 684 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 685 u32 val, isr; 686 int ret; 687 688 /* Disable modem control interrupts */ 689 stm32_usart_disable_ms(port); 690 691 val = USART_CR1_TXEIE | USART_CR1_TE; 692 val |= stm32_port->cr1_irq | USART_CR1_RE; 693 val |= BIT(cfg->uart_enable_bit); 694 if (stm32_port->fifoen) 695 val |= USART_CR1_FIFOEN; 696 697 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 698 isr, (isr & USART_SR_TC), 699 10, 100000); 700 701 if (ret) 702 dev_err(port->dev, "transmission complete not set\n"); 703 704 /* flush RX & TX FIFO */ 705 if (ofs->rqr != UNDEF_REG) 706 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 707 port->membase + ofs->rqr); 708 709 stm32_usart_clr_bits(port, ofs->cr1, val); 710 711 free_irq(port->irq, port); 712} 713 714static unsigned int stm32_usart_get_databits(struct ktermios *termios) 715{ 716 unsigned int bits; 717 718 tcflag_t cflag = termios->c_cflag; 719 720 switch (cflag & CSIZE) { 721 /* 722 * CSIZE settings are not necessarily supported in hardware. 723 * CSIZE unsupported configurations are handled here to set word length 724 * to 8 bits word as default configuration and to print debug message. 725 */ 726 case CS5: 727 bits = 5; 728 break; 729 case CS6: 730 bits = 6; 731 break; 732 case CS7: 733 bits = 7; 734 break; 735 /* default including CS8 */ 736 default: 737 bits = 8; 738 break; 739 } 740 741 return bits; 742} 743 744static void stm32_usart_set_termios(struct uart_port *port, 745 struct ktermios *termios, 746 struct ktermios *old) 747{ 748 struct stm32_port *stm32_port = to_stm32_port(port); 749 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 750 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 751 struct serial_rs485 *rs485conf = &port->rs485; 752 unsigned int baud, bits; 753 u32 usartdiv, mantissa, fraction, oversampling; 754 tcflag_t cflag = termios->c_cflag; 755 u32 cr1, cr2, cr3, isr; 756 unsigned long flags; 757 int ret; 758 759 if (!stm32_port->hw_flow_control) 760 cflag &= ~CRTSCTS; 761 762 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 763 764 spin_lock_irqsave(&port->lock, flags); 765 766 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 767 isr, 768 (isr & USART_SR_TC), 769 10, 100000); 770 771 /* Send the TC error message only when ISR_TC is not set. */ 772 if (ret) 773 dev_err(port->dev, "Transmission is not complete\n"); 774 775 /* Stop serial port and reset value */ 776 writel_relaxed(0, port->membase + ofs->cr1); 777 778 /* flush RX & TX FIFO */ 779 if (ofs->rqr != UNDEF_REG) 780 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 781 port->membase + ofs->rqr); 782 783 cr1 = USART_CR1_TE | USART_CR1_RE; 784 if (stm32_port->fifoen) 785 cr1 |= USART_CR1_FIFOEN; 786 cr2 = 0; 787 788 /* Tx and RX FIFO configuration */ 789 cr3 = readl_relaxed(port->membase + ofs->cr3); 790 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 791 if (stm32_port->fifoen) { 792 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 793 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 794 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 795 } 796 797 if (cflag & CSTOPB) 798 cr2 |= USART_CR2_STOP_2B; 799 800 bits = stm32_usart_get_databits(termios); 801 stm32_port->rdr_mask = (BIT(bits) - 1); 802 803 if (cflag & PARENB) { 804 bits++; 805 cr1 |= USART_CR1_PCE; 806 } 807 808 /* 809 * Word length configuration: 810 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 811 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 812 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 813 * M0 and M1 already cleared by cr1 initialization. 814 */ 815 if (bits == 9) { 816 cr1 |= USART_CR1_M0; 817 } else if ((bits == 7) && cfg->has_7bits_data) { 818 cr1 |= USART_CR1_M1; 819 } else if (bits != 8) { 820 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 821 , bits); 822 cflag &= ~CSIZE; 823 cflag |= CS8; 824 termios->c_cflag = cflag; 825 bits = 8; 826 if (cflag & PARENB) { 827 bits++; 828 cr1 |= USART_CR1_M0; 829 } 830 } 831 832 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 833 stm32_port->fifoen)) { 834 if (cflag & CSTOPB) 835 bits = bits + 3; /* 1 start bit + 2 stop bits */ 836 else 837 bits = bits + 2; /* 1 start bit + 1 stop bit */ 838 839 /* RX timeout irq to occur after last stop bit + bits */ 840 stm32_port->cr1_irq = USART_CR1_RTOIE; 841 writel_relaxed(bits, port->membase + ofs->rtor); 842 cr2 |= USART_CR2_RTOEN; 843 /* Not using dma, enable fifo threshold irq */ 844 if (!stm32_port->rx_ch) 845 stm32_port->cr3_irq = USART_CR3_RXFTIE; 846 } 847 848 cr1 |= stm32_port->cr1_irq; 849 cr3 |= stm32_port->cr3_irq; 850 851 if (cflag & PARODD) 852 cr1 |= USART_CR1_PS; 853 854 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 855 if (cflag & CRTSCTS) { 856 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 857 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 858 } 859 860 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 861 862 /* 863 * The USART supports 16 or 8 times oversampling. 864 * By default we prefer 16 times oversampling, so that the receiver 865 * has a better tolerance to clock deviations. 866 * 8 times oversampling is only used to achieve higher speeds. 867 */ 868 if (usartdiv < 16) { 869 oversampling = 8; 870 cr1 |= USART_CR1_OVER8; 871 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 872 } else { 873 oversampling = 16; 874 cr1 &= ~USART_CR1_OVER8; 875 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 876 } 877 878 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 879 fraction = usartdiv % oversampling; 880 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 881 882 uart_update_timeout(port, cflag, baud); 883 884 port->read_status_mask = USART_SR_ORE; 885 if (termios->c_iflag & INPCK) 886 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 887 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 888 port->read_status_mask |= USART_SR_FE; 889 890 /* Characters to ignore */ 891 port->ignore_status_mask = 0; 892 if (termios->c_iflag & IGNPAR) 893 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 894 if (termios->c_iflag & IGNBRK) { 895 port->ignore_status_mask |= USART_SR_FE; 896 /* 897 * If we're ignoring parity and break indicators, 898 * ignore overruns too (for real raw support). 899 */ 900 if (termios->c_iflag & IGNPAR) 901 port->ignore_status_mask |= USART_SR_ORE; 902 } 903 904 /* Ignore all characters if CREAD is not set */ 905 if ((termios->c_cflag & CREAD) == 0) 906 port->ignore_status_mask |= USART_SR_DUMMY_RX; 907 908 if (stm32_port->rx_ch) 909 cr3 |= USART_CR3_DMAR; 910 911 if (rs485conf->flags & SER_RS485_ENABLED) { 912 stm32_usart_config_reg_rs485(&cr1, &cr3, 913 rs485conf->delay_rts_before_send, 914 rs485conf->delay_rts_after_send, 915 baud); 916 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 917 cr3 &= ~USART_CR3_DEP; 918 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 919 } else { 920 cr3 |= USART_CR3_DEP; 921 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 922 } 923 924 } else { 925 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 926 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 927 } 928 929 /* Configure wake up from low power on start bit detection */ 930 if (stm32_port->wakeirq > 0) { 931 cr3 &= ~USART_CR3_WUS_MASK; 932 cr3 |= USART_CR3_WUS_START_BIT; 933 } 934 935 writel_relaxed(cr3, port->membase + ofs->cr3); 936 writel_relaxed(cr2, port->membase + ofs->cr2); 937 writel_relaxed(cr1, port->membase + ofs->cr1); 938 939 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 940 spin_unlock_irqrestore(&port->lock, flags); 941 942 /* Handle modem control interrupts */ 943 if (UART_ENABLE_MS(port, termios->c_cflag)) 944 stm32_usart_enable_ms(port); 945 else 946 stm32_usart_disable_ms(port); 947} 948 949static const char *stm32_usart_type(struct uart_port *port) 950{ 951 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 952} 953 954static void stm32_usart_release_port(struct uart_port *port) 955{ 956} 957 958static int stm32_usart_request_port(struct uart_port *port) 959{ 960 return 0; 961} 962 963static void stm32_usart_config_port(struct uart_port *port, int flags) 964{ 965 if (flags & UART_CONFIG_TYPE) 966 port->type = PORT_STM32; 967} 968 969static int 970stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 971{ 972 /* No user changeable parameters */ 973 return -EINVAL; 974} 975 976static void stm32_usart_pm(struct uart_port *port, unsigned int state, 977 unsigned int oldstate) 978{ 979 struct stm32_port *stm32port = container_of(port, 980 struct stm32_port, port); 981 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 982 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 983 unsigned long flags = 0; 984 985 switch (state) { 986 case UART_PM_STATE_ON: 987 pm_runtime_get_sync(port->dev); 988 break; 989 case UART_PM_STATE_OFF: 990 spin_lock_irqsave(&port->lock, flags); 991 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 992 spin_unlock_irqrestore(&port->lock, flags); 993 pm_runtime_put_sync(port->dev); 994 break; 995 } 996} 997 998static const struct uart_ops stm32_uart_ops = { 999 .tx_empty = stm32_usart_tx_empty, 1000 .set_mctrl = stm32_usart_set_mctrl, 1001 .get_mctrl = stm32_usart_get_mctrl, 1002 .stop_tx = stm32_usart_stop_tx, 1003 .start_tx = stm32_usart_start_tx, 1004 .throttle = stm32_usart_throttle, 1005 .unthrottle = stm32_usart_unthrottle, 1006 .stop_rx = stm32_usart_stop_rx, 1007 .enable_ms = stm32_usart_enable_ms, 1008 .break_ctl = stm32_usart_break_ctl, 1009 .startup = stm32_usart_startup, 1010 .shutdown = stm32_usart_shutdown, 1011 .set_termios = stm32_usart_set_termios, 1012 .pm = stm32_usart_pm, 1013 .type = stm32_usart_type, 1014 .release_port = stm32_usart_release_port, 1015 .request_port = stm32_usart_request_port, 1016 .config_port = stm32_usart_config_port, 1017 .verify_port = stm32_usart_verify_port, 1018}; 1019 1020static int stm32_usart_init_port(struct stm32_port *stm32port, 1021 struct platform_device *pdev) 1022{ 1023 struct uart_port *port = &stm32port->port; 1024 struct resource *res; 1025 int ret; 1026 1027 ret = platform_get_irq(pdev, 0); 1028 if (ret <= 0) 1029 return ret ? : -ENODEV; 1030 1031 port->iotype = UPIO_MEM; 1032 port->flags = UPF_BOOT_AUTOCONF; 1033 port->ops = &stm32_uart_ops; 1034 port->dev = &pdev->dev; 1035 port->fifosize = stm32port->info->cfg.fifosize; 1036 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1037 port->irq = ret; 1038 port->rs485_config = stm32_usart_config_rs485; 1039 1040 ret = stm32_usart_init_rs485(port, pdev); 1041 if (ret) 1042 return ret; 1043 1044 if (stm32port->info->cfg.has_wakeup) { 1045 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1046 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1047 return stm32port->wakeirq ? : -ENODEV; 1048 } 1049 1050 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1051 1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1053 port->membase = devm_ioremap_resource(&pdev->dev, res); 1054 if (IS_ERR(port->membase)) 1055 return PTR_ERR(port->membase); 1056 port->mapbase = res->start; 1057 1058 spin_lock_init(&port->lock); 1059 1060 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1061 if (IS_ERR(stm32port->clk)) 1062 return PTR_ERR(stm32port->clk); 1063 1064 /* Ensure that clk rate is correct by enabling the clk */ 1065 ret = clk_prepare_enable(stm32port->clk); 1066 if (ret) 1067 return ret; 1068 1069 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1070 if (!stm32port->port.uartclk) { 1071 ret = -EINVAL; 1072 goto err_clk; 1073 } 1074 1075 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1076 if (IS_ERR(stm32port->gpios)) { 1077 ret = PTR_ERR(stm32port->gpios); 1078 goto err_clk; 1079 } 1080 1081 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ 1082 if (stm32port->hw_flow_control) { 1083 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1084 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1085 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1086 ret = -EINVAL; 1087 goto err_clk; 1088 } 1089 } 1090 1091 return ret; 1092 1093err_clk: 1094 clk_disable_unprepare(stm32port->clk); 1095 1096 return ret; 1097} 1098 1099static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1100{ 1101 struct device_node *np = pdev->dev.of_node; 1102 int id; 1103 1104 if (!np) 1105 return NULL; 1106 1107 id = of_alias_get_id(np, "serial"); 1108 if (id < 0) { 1109 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1110 return NULL; 1111 } 1112 1113 if (WARN_ON(id >= STM32_MAX_PORTS)) 1114 return NULL; 1115 1116 stm32_ports[id].hw_flow_control = 1117 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1118 of_property_read_bool (np, "uart-has-rtscts"); 1119 stm32_ports[id].port.line = id; 1120 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1121 stm32_ports[id].cr3_irq = 0; 1122 stm32_ports[id].last_res = RX_BUF_L; 1123 return &stm32_ports[id]; 1124} 1125 1126#ifdef CONFIG_OF 1127static const struct of_device_id stm32_match[] = { 1128 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1129 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1130 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1131 {}, 1132}; 1133 1134MODULE_DEVICE_TABLE(of, stm32_match); 1135#endif 1136 1137static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1138 struct platform_device *pdev) 1139{ 1140 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1141 struct uart_port *port = &stm32port->port; 1142 struct device *dev = &pdev->dev; 1143 struct dma_slave_config config; 1144 struct dma_async_tx_descriptor *desc = NULL; 1145 int ret; 1146 1147 /* 1148 * Using DMA and threaded handler for the console could lead to 1149 * deadlocks. 1150 */ 1151 if (uart_console(port)) 1152 return -ENODEV; 1153 1154 /* Request DMA RX channel */ 1155 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1156 if (!stm32port->rx_ch) { 1157 dev_info(dev, "rx dma alloc failed\n"); 1158 return -ENODEV; 1159 } 1160 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1161 &stm32port->rx_dma_buf, 1162 GFP_KERNEL); 1163 if (!stm32port->rx_buf) { 1164 ret = -ENOMEM; 1165 goto alloc_err; 1166 } 1167 1168 /* Configure DMA channel */ 1169 memset(&config, 0, sizeof(config)); 1170 config.src_addr = port->mapbase + ofs->rdr; 1171 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1172 1173 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1174 if (ret < 0) { 1175 dev_err(dev, "rx dma channel config failed\n"); 1176 ret = -ENODEV; 1177 goto config_err; 1178 } 1179 1180 /* Prepare a DMA cyclic transaction */ 1181 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1182 stm32port->rx_dma_buf, 1183 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1184 DMA_PREP_INTERRUPT); 1185 if (!desc) { 1186 dev_err(dev, "rx dma prep cyclic failed\n"); 1187 ret = -ENODEV; 1188 goto config_err; 1189 } 1190 1191 /* No callback as dma buffer is drained on usart interrupt */ 1192 desc->callback = NULL; 1193 desc->callback_param = NULL; 1194 1195 /* Push current DMA transaction in the pending queue */ 1196 ret = dma_submit_error(dmaengine_submit(desc)); 1197 if (ret) { 1198 dmaengine_terminate_sync(stm32port->rx_ch); 1199 goto config_err; 1200 } 1201 1202 /* Issue pending DMA requests */ 1203 dma_async_issue_pending(stm32port->rx_ch); 1204 1205 return 0; 1206 1207config_err: 1208 dma_free_coherent(&pdev->dev, 1209 RX_BUF_L, stm32port->rx_buf, 1210 stm32port->rx_dma_buf); 1211 1212alloc_err: 1213 dma_release_channel(stm32port->rx_ch); 1214 stm32port->rx_ch = NULL; 1215 1216 return ret; 1217} 1218 1219static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1220 struct platform_device *pdev) 1221{ 1222 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1223 struct uart_port *port = &stm32port->port; 1224 struct device *dev = &pdev->dev; 1225 struct dma_slave_config config; 1226 int ret; 1227 1228 stm32port->tx_dma_busy = false; 1229 1230 /* Request DMA TX channel */ 1231 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1232 if (!stm32port->tx_ch) { 1233 dev_info(dev, "tx dma alloc failed\n"); 1234 return -ENODEV; 1235 } 1236 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1237 &stm32port->tx_dma_buf, 1238 GFP_KERNEL); 1239 if (!stm32port->tx_buf) { 1240 ret = -ENOMEM; 1241 goto alloc_err; 1242 } 1243 1244 /* Configure DMA channel */ 1245 memset(&config, 0, sizeof(config)); 1246 config.dst_addr = port->mapbase + ofs->tdr; 1247 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1248 1249 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1250 if (ret < 0) { 1251 dev_err(dev, "tx dma channel config failed\n"); 1252 ret = -ENODEV; 1253 goto config_err; 1254 } 1255 1256 return 0; 1257 1258config_err: 1259 dma_free_coherent(&pdev->dev, 1260 TX_BUF_L, stm32port->tx_buf, 1261 stm32port->tx_dma_buf); 1262 1263alloc_err: 1264 dma_release_channel(stm32port->tx_ch); 1265 stm32port->tx_ch = NULL; 1266 1267 return ret; 1268} 1269 1270static int stm32_usart_serial_probe(struct platform_device *pdev) 1271{ 1272 struct stm32_port *stm32port; 1273 int ret; 1274 1275 stm32port = stm32_usart_of_get_port(pdev); 1276 if (!stm32port) 1277 return -ENODEV; 1278 1279 stm32port->info = of_device_get_match_data(&pdev->dev); 1280 if (!stm32port->info) 1281 return -EINVAL; 1282 1283 ret = stm32_usart_init_port(stm32port, pdev); 1284 if (ret) 1285 return ret; 1286 1287 if (stm32port->wakeirq > 0) { 1288 ret = device_init_wakeup(&pdev->dev, true); 1289 if (ret) 1290 goto err_uninit; 1291 1292 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1293 stm32port->wakeirq); 1294 if (ret) 1295 goto err_nowup; 1296 1297 device_set_wakeup_enable(&pdev->dev, false); 1298 } 1299 1300 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1301 if (ret) 1302 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1303 1304 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1305 if (ret) 1306 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1307 1308 platform_set_drvdata(pdev, &stm32port->port); 1309 1310 pm_runtime_get_noresume(&pdev->dev); 1311 pm_runtime_set_active(&pdev->dev); 1312 pm_runtime_enable(&pdev->dev); 1313 1314 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1315 if (ret) 1316 goto err_port; 1317 1318 pm_runtime_put_sync(&pdev->dev); 1319 1320 return 0; 1321 1322err_port: 1323 pm_runtime_disable(&pdev->dev); 1324 pm_runtime_set_suspended(&pdev->dev); 1325 pm_runtime_put_noidle(&pdev->dev); 1326 1327 if (stm32port->rx_ch) { 1328 dmaengine_terminate_async(stm32port->rx_ch); 1329 dma_release_channel(stm32port->rx_ch); 1330 } 1331 1332 if (stm32port->rx_dma_buf) 1333 dma_free_coherent(&pdev->dev, 1334 RX_BUF_L, stm32port->rx_buf, 1335 stm32port->rx_dma_buf); 1336 1337 if (stm32port->tx_ch) { 1338 dmaengine_terminate_async(stm32port->tx_ch); 1339 dma_release_channel(stm32port->tx_ch); 1340 } 1341 1342 if (stm32port->tx_dma_buf) 1343 dma_free_coherent(&pdev->dev, 1344 TX_BUF_L, stm32port->tx_buf, 1345 stm32port->tx_dma_buf); 1346 1347 if (stm32port->wakeirq > 0) 1348 dev_pm_clear_wake_irq(&pdev->dev); 1349 1350err_nowup: 1351 if (stm32port->wakeirq > 0) 1352 device_init_wakeup(&pdev->dev, false); 1353 1354err_uninit: 1355 clk_disable_unprepare(stm32port->clk); 1356 1357 return ret; 1358} 1359 1360static int stm32_usart_serial_remove(struct platform_device *pdev) 1361{ 1362 struct uart_port *port = platform_get_drvdata(pdev); 1363 struct stm32_port *stm32_port = to_stm32_port(port); 1364 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1365 int err; 1366 1367 pm_runtime_get_sync(&pdev->dev); 1368 err = uart_remove_one_port(&stm32_usart_driver, port); 1369 if (err) 1370 return(err); 1371 1372 pm_runtime_disable(&pdev->dev); 1373 pm_runtime_set_suspended(&pdev->dev); 1374 pm_runtime_put_noidle(&pdev->dev); 1375 1376 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1377 1378 if (stm32_port->rx_ch) { 1379 dmaengine_terminate_async(stm32_port->rx_ch); 1380 dma_release_channel(stm32_port->rx_ch); 1381 } 1382 1383 if (stm32_port->rx_dma_buf) 1384 dma_free_coherent(&pdev->dev, 1385 RX_BUF_L, stm32_port->rx_buf, 1386 stm32_port->rx_dma_buf); 1387 1388 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1389 1390 if (stm32_port->tx_ch) { 1391 dmaengine_terminate_async(stm32_port->tx_ch); 1392 dma_release_channel(stm32_port->tx_ch); 1393 } 1394 1395 if (stm32_port->tx_dma_buf) 1396 dma_free_coherent(&pdev->dev, 1397 TX_BUF_L, stm32_port->tx_buf, 1398 stm32_port->tx_dma_buf); 1399 1400 if (stm32_port->wakeirq > 0) { 1401 dev_pm_clear_wake_irq(&pdev->dev); 1402 device_init_wakeup(&pdev->dev, false); 1403 } 1404 1405 clk_disable_unprepare(stm32_port->clk); 1406 1407 return 0; 1408} 1409 1410#ifdef CONFIG_SERIAL_STM32_CONSOLE 1411static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1412{ 1413 struct stm32_port *stm32_port = to_stm32_port(port); 1414 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1415 1416 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1417 cpu_relax(); 1418 1419 writel_relaxed(ch, port->membase + ofs->tdr); 1420} 1421 1422static void stm32_usart_console_write(struct console *co, const char *s, 1423 unsigned int cnt) 1424{ 1425 struct uart_port *port = &stm32_ports[co->index].port; 1426 struct stm32_port *stm32_port = to_stm32_port(port); 1427 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1428 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1429 unsigned long flags; 1430 u32 old_cr1, new_cr1; 1431 int locked = 1; 1432 1433 local_irq_save(flags); 1434 if (port->sysrq) 1435 locked = 0; 1436 else if (oops_in_progress) 1437 locked = spin_trylock(&port->lock); 1438 else 1439 spin_lock(&port->lock); 1440 1441 /* Save and disable interrupts, enable the transmitter */ 1442 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1443 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1444 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1445 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1446 1447 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1448 1449 /* Restore interrupt state */ 1450 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1451 1452 if (locked) 1453 spin_unlock(&port->lock); 1454 local_irq_restore(flags); 1455} 1456 1457static int stm32_usart_console_setup(struct console *co, char *options) 1458{ 1459 struct stm32_port *stm32port; 1460 int baud = 9600; 1461 int bits = 8; 1462 int parity = 'n'; 1463 int flow = 'n'; 1464 1465 if (co->index >= STM32_MAX_PORTS) 1466 return -ENODEV; 1467 1468 stm32port = &stm32_ports[co->index]; 1469 1470 /* 1471 * This driver does not support early console initialization 1472 * (use ARM early printk support instead), so we only expect 1473 * this to be called during the uart port registration when the 1474 * driver gets probed and the port should be mapped at that point. 1475 */ 1476 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1477 return -ENXIO; 1478 1479 if (options) 1480 uart_parse_options(options, &baud, &parity, &bits, &flow); 1481 1482 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1483} 1484 1485static struct console stm32_console = { 1486 .name = STM32_SERIAL_NAME, 1487 .device = uart_console_device, 1488 .write = stm32_usart_console_write, 1489 .setup = stm32_usart_console_setup, 1490 .flags = CON_PRINTBUFFER, 1491 .index = -1, 1492 .data = &stm32_usart_driver, 1493}; 1494 1495#define STM32_SERIAL_CONSOLE (&stm32_console) 1496 1497#else 1498#define STM32_SERIAL_CONSOLE NULL 1499#endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1500 1501static struct uart_driver stm32_usart_driver = { 1502 .driver_name = DRIVER_NAME, 1503 .dev_name = STM32_SERIAL_NAME, 1504 .major = 0, 1505 .minor = 0, 1506 .nr = STM32_MAX_PORTS, 1507 .cons = STM32_SERIAL_CONSOLE, 1508}; 1509 1510static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1511 bool enable) 1512{ 1513 struct stm32_port *stm32_port = to_stm32_port(port); 1514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1515 1516 if (stm32_port->wakeirq <= 0) 1517 return; 1518 1519 /* 1520 * Enable low-power wake-up and wake-up irq if argument is set to 1521 * "enable", disable low-power wake-up and wake-up irq otherwise 1522 */ 1523 if (enable) { 1524 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1525 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 1526 } else { 1527 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1528 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 1529 } 1530} 1531 1532static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1533{ 1534 struct uart_port *port = dev_get_drvdata(dev); 1535 1536 uart_suspend_port(&stm32_usart_driver, port); 1537 1538 if (device_may_wakeup(dev)) 1539 stm32_usart_serial_en_wakeup(port, true); 1540 else 1541 stm32_usart_serial_en_wakeup(port, false); 1542 1543 /* 1544 * When "no_console_suspend" is enabled, keep the pinctrl default state 1545 * and rely on bootloader stage to restore this state upon resume. 1546 * Otherwise, apply the idle or sleep states depending on wakeup 1547 * capabilities. 1548 */ 1549 if (console_suspend_enabled || !uart_console(port)) { 1550 if (device_may_wakeup(dev)) 1551 pinctrl_pm_select_idle_state(dev); 1552 else 1553 pinctrl_pm_select_sleep_state(dev); 1554 } 1555 1556 return 0; 1557} 1558 1559static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1560{ 1561 struct uart_port *port = dev_get_drvdata(dev); 1562 1563 pinctrl_pm_select_default_state(dev); 1564 1565 if (device_may_wakeup(dev)) 1566 stm32_usart_serial_en_wakeup(port, false); 1567 1568 return uart_resume_port(&stm32_usart_driver, port); 1569} 1570 1571static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1572{ 1573 struct uart_port *port = dev_get_drvdata(dev); 1574 struct stm32_port *stm32port = container_of(port, 1575 struct stm32_port, port); 1576 1577 clk_disable_unprepare(stm32port->clk); 1578 1579 return 0; 1580} 1581 1582static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1583{ 1584 struct uart_port *port = dev_get_drvdata(dev); 1585 struct stm32_port *stm32port = container_of(port, 1586 struct stm32_port, port); 1587 1588 return clk_prepare_enable(stm32port->clk); 1589} 1590 1591static const struct dev_pm_ops stm32_serial_pm_ops = { 1592 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1593 stm32_usart_runtime_resume, NULL) 1594 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1595 stm32_usart_serial_resume) 1596}; 1597 1598static struct platform_driver stm32_serial_driver = { 1599 .probe = stm32_usart_serial_probe, 1600 .remove = stm32_usart_serial_remove, 1601 .driver = { 1602 .name = DRIVER_NAME, 1603 .pm = &stm32_serial_pm_ops, 1604 .of_match_table = of_match_ptr(stm32_match), 1605 }, 1606}; 1607 1608static int __init stm32_usart_init(void) 1609{ 1610 static char banner[] __initdata = "STM32 USART driver initialized"; 1611 int ret; 1612 1613 pr_info("%s\n", banner); 1614 1615 ret = uart_register_driver(&stm32_usart_driver); 1616 if (ret) 1617 return ret; 1618 1619 ret = platform_driver_register(&stm32_serial_driver); 1620 if (ret) 1621 uart_unregister_driver(&stm32_usart_driver); 1622 1623 return ret; 1624} 1625 1626static void __exit stm32_usart_exit(void) 1627{ 1628 platform_driver_unregister(&stm32_serial_driver); 1629 uart_unregister_driver(&stm32_usart_driver); 1630} 1631 1632module_init(stm32_usart_init); 1633module_exit(stm32_usart_exit); 1634 1635MODULE_ALIAS("platform:" DRIVER_NAME); 1636MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1637MODULE_LICENSE("GPL v2"); 1638