1// SPDX-License-Identifier: GPL-2.0+ 2/* 3* *************************************************************************** 4* Marvell Armada-3700 Serial Driver 5* Author: Wilson Ding <dingwei@marvell.com> 6* Copyright (C) 2015 Marvell International Ltd. 7* *************************************************************************** 8*/ 9 10#include <linux/clk.h> 11#include <linux/console.h> 12#include <linux/delay.h> 13#include <linux/device.h> 14#include <linux/init.h> 15#include <linux/io.h> 16#include <linux/iopoll.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/of_device.h> 20#include <linux/of_irq.h> 21#include <linux/of_platform.h> 22#include <linux/platform_device.h> 23#include <linux/serial.h> 24#include <linux/serial_core.h> 25#include <linux/slab.h> 26#include <linux/tty.h> 27#include <linux/tty_flip.h> 28 29/* Register Map */ 30#define UART_STD_RBR 0x00 31#define UART_EXT_RBR 0x18 32 33#define UART_STD_TSH 0x04 34#define UART_EXT_TSH 0x1C 35 36#define UART_STD_CTRL1 0x08 37#define UART_EXT_CTRL1 0x04 38#define CTRL_SOFT_RST BIT(31) 39#define CTRL_TXFIFO_RST BIT(15) 40#define CTRL_RXFIFO_RST BIT(14) 41#define CTRL_SND_BRK_SEQ BIT(11) 42#define CTRL_BRK_DET_INT BIT(3) 43#define CTRL_FRM_ERR_INT BIT(2) 44#define CTRL_PAR_ERR_INT BIT(1) 45#define CTRL_OVR_ERR_INT BIT(0) 46#define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \ 47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) 48 49#define UART_STD_CTRL2 UART_STD_CTRL1 50#define UART_EXT_CTRL2 0x20 51#define CTRL_STD_TX_RDY_INT BIT(5) 52#define CTRL_EXT_TX_RDY_INT BIT(6) 53#define CTRL_STD_RX_RDY_INT BIT(4) 54#define CTRL_EXT_RX_RDY_INT BIT(5) 55 56#define UART_STAT 0x0C 57#define STAT_TX_FIFO_EMP BIT(13) 58#define STAT_TX_FIFO_FUL BIT(11) 59#define STAT_TX_EMP BIT(6) 60#define STAT_STD_TX_RDY BIT(5) 61#define STAT_EXT_TX_RDY BIT(15) 62#define STAT_STD_RX_RDY BIT(4) 63#define STAT_EXT_RX_RDY BIT(14) 64#define STAT_BRK_DET BIT(3) 65#define STAT_FRM_ERR BIT(2) 66#define STAT_PAR_ERR BIT(1) 67#define STAT_OVR_ERR BIT(0) 68#define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \ 69 | STAT_PAR_ERR | STAT_OVR_ERR) 70 71#define UART_BRDV 0x10 72#define BRDV_BAUD_MASK 0x3FF 73 74#define UART_OSAMP 0x14 75#define OSAMP_DEFAULT_DIVISOR 16 76#define OSAMP_DIVISORS_MASK 0x3F3F3F3F 77 78#define MVEBU_NR_UARTS 2 79 80#define MVEBU_UART_TYPE "mvebu-uart" 81#define DRIVER_NAME "mvebu_serial" 82 83enum { 84 /* Either there is only one summed IRQ... */ 85 UART_IRQ_SUM = 0, 86 /* ...or there are two separate IRQ for RX and TX */ 87 UART_RX_IRQ = 0, 88 UART_TX_IRQ, 89 UART_IRQ_COUNT 90}; 91 92/* Diverging register offsets */ 93struct uart_regs_layout { 94 unsigned int rbr; 95 unsigned int tsh; 96 unsigned int ctrl; 97 unsigned int intr; 98}; 99 100/* Diverging flags */ 101struct uart_flags { 102 unsigned int ctrl_tx_rdy_int; 103 unsigned int ctrl_rx_rdy_int; 104 unsigned int stat_tx_rdy; 105 unsigned int stat_rx_rdy; 106}; 107 108/* Driver data, a structure for each UART port */ 109struct mvebu_uart_driver_data { 110 bool is_ext; 111 struct uart_regs_layout regs; 112 struct uart_flags flags; 113}; 114 115/* Saved registers during suspend */ 116struct mvebu_uart_pm_regs { 117 unsigned int rbr; 118 unsigned int tsh; 119 unsigned int ctrl; 120 unsigned int intr; 121 unsigned int stat; 122 unsigned int brdv; 123 unsigned int osamp; 124}; 125 126/* MVEBU UART driver structure */ 127struct mvebu_uart { 128 struct uart_port *port; 129 struct clk *clk; 130 int irq[UART_IRQ_COUNT]; 131 unsigned char __iomem *nb; 132 struct mvebu_uart_driver_data *data; 133#if defined(CONFIG_PM) 134 struct mvebu_uart_pm_regs pm_regs; 135#endif /* CONFIG_PM */ 136}; 137 138static struct mvebu_uart *to_mvuart(struct uart_port *port) 139{ 140 return (struct mvebu_uart *)port->private_data; 141} 142 143#define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext) 144 145#define UART_RBR(port) (to_mvuart(port)->data->regs.rbr) 146#define UART_TSH(port) (to_mvuart(port)->data->regs.tsh) 147#define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl) 148#define UART_INTR(port) (to_mvuart(port)->data->regs.intr) 149 150#define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int) 151#define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int) 152#define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy) 153#define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy) 154 155static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; 156 157/* Core UART Driver Operations */ 158static unsigned int mvebu_uart_tx_empty(struct uart_port *port) 159{ 160 unsigned long flags; 161 unsigned int st; 162 163 spin_lock_irqsave(&port->lock, flags); 164 st = readl(port->membase + UART_STAT); 165 spin_unlock_irqrestore(&port->lock, flags); 166 167 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0; 168} 169 170static unsigned int mvebu_uart_get_mctrl(struct uart_port *port) 171{ 172 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 173} 174 175static void mvebu_uart_set_mctrl(struct uart_port *port, 176 unsigned int mctrl) 177{ 178/* 179 * Even if we do not support configuring the modem control lines, this 180 * function must be proided to the serial core 181 */ 182} 183 184static void mvebu_uart_stop_tx(struct uart_port *port) 185{ 186 unsigned int ctl = readl(port->membase + UART_INTR(port)); 187 188 ctl &= ~CTRL_TX_RDY_INT(port); 189 writel(ctl, port->membase + UART_INTR(port)); 190} 191 192static void mvebu_uart_start_tx(struct uart_port *port) 193{ 194 unsigned int ctl; 195 struct circ_buf *xmit = &port->state->xmit; 196 197 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { 198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 199 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 200 port->icount.tx++; 201 } 202 203 ctl = readl(port->membase + UART_INTR(port)); 204 ctl |= CTRL_TX_RDY_INT(port); 205 writel(ctl, port->membase + UART_INTR(port)); 206} 207 208static void mvebu_uart_stop_rx(struct uart_port *port) 209{ 210 unsigned int ctl; 211 212 ctl = readl(port->membase + UART_CTRL(port)); 213 ctl &= ~CTRL_BRK_INT; 214 writel(ctl, port->membase + UART_CTRL(port)); 215 216 ctl = readl(port->membase + UART_INTR(port)); 217 ctl &= ~CTRL_RX_RDY_INT(port); 218 writel(ctl, port->membase + UART_INTR(port)); 219} 220 221static void mvebu_uart_break_ctl(struct uart_port *port, int brk) 222{ 223 unsigned int ctl; 224 unsigned long flags; 225 226 spin_lock_irqsave(&port->lock, flags); 227 ctl = readl(port->membase + UART_CTRL(port)); 228 if (brk == -1) 229 ctl |= CTRL_SND_BRK_SEQ; 230 else 231 ctl &= ~CTRL_SND_BRK_SEQ; 232 writel(ctl, port->membase + UART_CTRL(port)); 233 spin_unlock_irqrestore(&port->lock, flags); 234} 235 236static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) 237{ 238 struct tty_port *tport = &port->state->port; 239 unsigned char ch = 0; 240 char flag = 0; 241 int ret; 242 243 do { 244 if (status & STAT_RX_RDY(port)) { 245 ch = readl(port->membase + UART_RBR(port)); 246 ch &= 0xff; 247 flag = TTY_NORMAL; 248 port->icount.rx++; 249 250 if (status & STAT_PAR_ERR) 251 port->icount.parity++; 252 } 253 254 /* 255 * For UART2, error bits are not cleared on buffer read. 256 * This causes interrupt loop and system hang. 257 */ 258 if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) { 259 ret = readl(port->membase + UART_STAT); 260 ret |= STAT_BRK_ERR; 261 writel(ret, port->membase + UART_STAT); 262 } 263 264 if (status & STAT_BRK_DET) { 265 port->icount.brk++; 266 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR); 267 if (uart_handle_break(port)) 268 goto ignore_char; 269 } 270 271 if (status & STAT_OVR_ERR) 272 port->icount.overrun++; 273 274 if (status & STAT_FRM_ERR) 275 port->icount.frame++; 276 277 if (uart_handle_sysrq_char(port, ch)) 278 goto ignore_char; 279 280 if (status & port->ignore_status_mask & STAT_PAR_ERR) 281 status &= ~STAT_RX_RDY(port); 282 283 status &= port->read_status_mask; 284 285 if (status & STAT_PAR_ERR) 286 flag = TTY_PARITY; 287 288 status &= ~port->ignore_status_mask; 289 290 if (status & STAT_RX_RDY(port)) 291 tty_insert_flip_char(tport, ch, flag); 292 293 if (status & STAT_BRK_DET) 294 tty_insert_flip_char(tport, 0, TTY_BREAK); 295 296 if (status & STAT_FRM_ERR) 297 tty_insert_flip_char(tport, 0, TTY_FRAME); 298 299 if (status & STAT_OVR_ERR) 300 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 301 302ignore_char: 303 status = readl(port->membase + UART_STAT); 304 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET)); 305 306 tty_flip_buffer_push(tport); 307} 308 309static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) 310{ 311 struct circ_buf *xmit = &port->state->xmit; 312 unsigned int count; 313 unsigned int st; 314 315 if (port->x_char) { 316 writel(port->x_char, port->membase + UART_TSH(port)); 317 port->icount.tx++; 318 port->x_char = 0; 319 return; 320 } 321 322 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 323 mvebu_uart_stop_tx(port); 324 return; 325 } 326 327 for (count = 0; count < port->fifosize; count++) { 328 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 329 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 330 port->icount.tx++; 331 332 if (uart_circ_empty(xmit)) 333 break; 334 335 st = readl(port->membase + UART_STAT); 336 if (st & STAT_TX_FIFO_FUL) 337 break; 338 } 339 340 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 341 uart_write_wakeup(port); 342 343 if (uart_circ_empty(xmit)) 344 mvebu_uart_stop_tx(port); 345} 346 347static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) 348{ 349 struct uart_port *port = (struct uart_port *)dev_id; 350 unsigned int st = readl(port->membase + UART_STAT); 351 352 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 353 STAT_BRK_DET)) 354 mvebu_uart_rx_chars(port, st); 355 356 if (st & STAT_TX_RDY(port)) 357 mvebu_uart_tx_chars(port, st); 358 359 return IRQ_HANDLED; 360} 361 362static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) 363{ 364 struct uart_port *port = (struct uart_port *)dev_id; 365 unsigned int st = readl(port->membase + UART_STAT); 366 367 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 368 STAT_BRK_DET)) 369 mvebu_uart_rx_chars(port, st); 370 371 return IRQ_HANDLED; 372} 373 374static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) 375{ 376 struct uart_port *port = (struct uart_port *)dev_id; 377 unsigned int st = readl(port->membase + UART_STAT); 378 379 if (st & STAT_TX_RDY(port)) 380 mvebu_uart_tx_chars(port, st); 381 382 return IRQ_HANDLED; 383} 384 385static int mvebu_uart_startup(struct uart_port *port) 386{ 387 struct mvebu_uart *mvuart = to_mvuart(port); 388 unsigned int ctl; 389 int ret; 390 391 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, 392 port->membase + UART_CTRL(port)); 393 udelay(1); 394 395 /* Clear the error bits of state register before IRQ request */ 396 ret = readl(port->membase + UART_STAT); 397 ret |= STAT_BRK_ERR; 398 writel(ret, port->membase + UART_STAT); 399 400 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); 401 402 ctl = readl(port->membase + UART_INTR(port)); 403 ctl |= CTRL_RX_RDY_INT(port); 404 writel(ctl, port->membase + UART_INTR(port)); 405 406 if (!mvuart->irq[UART_TX_IRQ]) { 407 /* Old bindings with just one interrupt (UART0 only) */ 408 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], 409 mvebu_uart_isr, port->irqflags, 410 dev_name(port->dev), port); 411 if (ret) { 412 dev_err(port->dev, "unable to request IRQ %d\n", 413 mvuart->irq[UART_IRQ_SUM]); 414 return ret; 415 } 416 } else { 417 /* New bindings with an IRQ for RX and TX (both UART) */ 418 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], 419 mvebu_uart_rx_isr, port->irqflags, 420 dev_name(port->dev), port); 421 if (ret) { 422 dev_err(port->dev, "unable to request IRQ %d\n", 423 mvuart->irq[UART_RX_IRQ]); 424 return ret; 425 } 426 427 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], 428 mvebu_uart_tx_isr, port->irqflags, 429 dev_name(port->dev), 430 port); 431 if (ret) { 432 dev_err(port->dev, "unable to request IRQ %d\n", 433 mvuart->irq[UART_TX_IRQ]); 434 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], 435 port); 436 return ret; 437 } 438 } 439 440 return 0; 441} 442 443static void mvebu_uart_shutdown(struct uart_port *port) 444{ 445 struct mvebu_uart *mvuart = to_mvuart(port); 446 447 writel(0, port->membase + UART_INTR(port)); 448 449 if (!mvuart->irq[UART_TX_IRQ]) { 450 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); 451 } else { 452 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); 453 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); 454 } 455} 456 457static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) 458{ 459 unsigned int d_divisor, m_divisor; 460 u32 brdv, osamp; 461 462 if (!port->uartclk) 463 return 0; 464 465 /* 466 * The baudrate is derived from the UART clock thanks to two divisors: 467 * > D ("baud generator"): can divide the clock from 2 to 2^10 - 1. 468 * > M ("fractional divisor"): allows a better accuracy for 469 * baudrates higher than 230400. 470 * 471 * As the derivation of M is rather complicated, the code sticks to its 472 * default value (x16) when all the prescalers are zeroed, and only 473 * makes use of D to configure the desired baudrate. 474 */ 475 m_divisor = OSAMP_DEFAULT_DIVISOR; 476 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 477 478 brdv = readl(port->membase + UART_BRDV); 479 brdv &= ~BRDV_BAUD_MASK; 480 brdv |= d_divisor; 481 writel(brdv, port->membase + UART_BRDV); 482 483 osamp = readl(port->membase + UART_OSAMP); 484 osamp &= ~OSAMP_DIVISORS_MASK; 485 writel(osamp, port->membase + UART_OSAMP); 486 487 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); 488} 489 490static void mvebu_uart_set_termios(struct uart_port *port, 491 struct ktermios *termios, 492 struct ktermios *old) 493{ 494 unsigned long flags; 495 unsigned int baud, min_baud, max_baud; 496 497 spin_lock_irqsave(&port->lock, flags); 498 499 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | 500 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; 501 502 if (termios->c_iflag & INPCK) 503 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; 504 505 port->ignore_status_mask = 0; 506 if (termios->c_iflag & IGNPAR) 507 port->ignore_status_mask |= 508 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; 509 510 if ((termios->c_cflag & CREAD) == 0) 511 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; 512 513 /* 514 * Maximal divisor is 1023 * 16 when using default (x16) scheme. 515 * Maximum achievable frequency with simple baudrate divisor is 230400. 516 * Since the error per bit frame would be of more than 15%, achieving 517 * higher frequencies would require to implement the fractional divisor 518 * feature. 519 */ 520 min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16); 521 max_baud = 230400; 522 523 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud); 524 baud = mvebu_uart_baud_rate_set(port, baud); 525 526 /* In case baudrate cannot be changed, report previous old value */ 527 if (baud == 0 && old) 528 baud = tty_termios_baud_rate(old); 529 530 /* Only the following flag changes are supported */ 531 if (old) { 532 termios->c_iflag &= INPCK | IGNPAR; 533 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); 534 termios->c_cflag &= CREAD | CBAUD; 535 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); 536 termios->c_cflag |= CS8; 537 } 538 539 if (baud != 0) { 540 tty_termios_encode_baud_rate(termios, baud, baud); 541 uart_update_timeout(port, termios->c_cflag, baud); 542 } 543 544 spin_unlock_irqrestore(&port->lock, flags); 545} 546 547static const char *mvebu_uart_type(struct uart_port *port) 548{ 549 return MVEBU_UART_TYPE; 550} 551 552static void mvebu_uart_release_port(struct uart_port *port) 553{ 554 /* Nothing to do here */ 555} 556 557static int mvebu_uart_request_port(struct uart_port *port) 558{ 559 return 0; 560} 561 562#ifdef CONFIG_CONSOLE_POLL 563static int mvebu_uart_get_poll_char(struct uart_port *port) 564{ 565 unsigned int st = readl(port->membase + UART_STAT); 566 567 if (!(st & STAT_RX_RDY(port))) 568 return NO_POLL_CHAR; 569 570 return readl(port->membase + UART_RBR(port)); 571} 572 573static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) 574{ 575 unsigned int st; 576 577 for (;;) { 578 st = readl(port->membase + UART_STAT); 579 580 if (!(st & STAT_TX_FIFO_FUL)) 581 break; 582 583 udelay(1); 584 } 585 586 writel(c, port->membase + UART_TSH(port)); 587} 588#endif 589 590static const struct uart_ops mvebu_uart_ops = { 591 .tx_empty = mvebu_uart_tx_empty, 592 .set_mctrl = mvebu_uart_set_mctrl, 593 .get_mctrl = mvebu_uart_get_mctrl, 594 .stop_tx = mvebu_uart_stop_tx, 595 .start_tx = mvebu_uart_start_tx, 596 .stop_rx = mvebu_uart_stop_rx, 597 .break_ctl = mvebu_uart_break_ctl, 598 .startup = mvebu_uart_startup, 599 .shutdown = mvebu_uart_shutdown, 600 .set_termios = mvebu_uart_set_termios, 601 .type = mvebu_uart_type, 602 .release_port = mvebu_uart_release_port, 603 .request_port = mvebu_uart_request_port, 604#ifdef CONFIG_CONSOLE_POLL 605 .poll_get_char = mvebu_uart_get_poll_char, 606 .poll_put_char = mvebu_uart_put_poll_char, 607#endif 608}; 609 610/* Console Driver Operations */ 611 612#ifdef CONFIG_SERIAL_MVEBU_CONSOLE 613/* Early Console */ 614static void mvebu_uart_putc(struct uart_port *port, int c) 615{ 616 unsigned int st; 617 618 for (;;) { 619 st = readl(port->membase + UART_STAT); 620 if (!(st & STAT_TX_FIFO_FUL)) 621 break; 622 } 623 624 /* At early stage, DT is not parsed yet, only use UART0 */ 625 writel(c, port->membase + UART_STD_TSH); 626 627 for (;;) { 628 st = readl(port->membase + UART_STAT); 629 if (st & STAT_TX_FIFO_EMP) 630 break; 631 } 632} 633 634static void mvebu_uart_putc_early_write(struct console *con, 635 const char *s, 636 unsigned n) 637{ 638 struct earlycon_device *dev = con->data; 639 640 uart_console_write(&dev->port, s, n, mvebu_uart_putc); 641} 642 643static int __init 644mvebu_uart_early_console_setup(struct earlycon_device *device, 645 const char *opt) 646{ 647 if (!device->port.membase) 648 return -ENODEV; 649 650 device->con->write = mvebu_uart_putc_early_write; 651 652 return 0; 653} 654 655EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup); 656OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart", 657 mvebu_uart_early_console_setup); 658 659static void wait_for_xmitr(struct uart_port *port) 660{ 661 u32 val; 662 663 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 664 (val & STAT_TX_RDY(port)), 1, 10000); 665} 666 667static void wait_for_xmite(struct uart_port *port) 668{ 669 u32 val; 670 671 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 672 (val & STAT_TX_EMP), 1, 10000); 673} 674 675static void mvebu_uart_console_putchar(struct uart_port *port, int ch) 676{ 677 wait_for_xmitr(port); 678 writel(ch, port->membase + UART_TSH(port)); 679} 680 681static void mvebu_uart_console_write(struct console *co, const char *s, 682 unsigned int count) 683{ 684 struct uart_port *port = &mvebu_uart_ports[co->index]; 685 unsigned long flags; 686 unsigned int ier, intr, ctl; 687 int locked = 1; 688 689 if (oops_in_progress) 690 locked = spin_trylock_irqsave(&port->lock, flags); 691 else 692 spin_lock_irqsave(&port->lock, flags); 693 694 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; 695 intr = readl(port->membase + UART_INTR(port)) & 696 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port)); 697 writel(0, port->membase + UART_CTRL(port)); 698 writel(0, port->membase + UART_INTR(port)); 699 700 uart_console_write(port, s, count, mvebu_uart_console_putchar); 701 702 wait_for_xmite(port); 703 704 if (ier) 705 writel(ier, port->membase + UART_CTRL(port)); 706 707 if (intr) { 708 ctl = intr | readl(port->membase + UART_INTR(port)); 709 writel(ctl, port->membase + UART_INTR(port)); 710 } 711 712 if (locked) 713 spin_unlock_irqrestore(&port->lock, flags); 714} 715 716static int mvebu_uart_console_setup(struct console *co, char *options) 717{ 718 struct uart_port *port; 719 int baud = 9600; 720 int bits = 8; 721 int parity = 'n'; 722 int flow = 'n'; 723 724 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) 725 return -EINVAL; 726 727 port = &mvebu_uart_ports[co->index]; 728 729 if (!port->mapbase || !port->membase) { 730 pr_debug("console on ttyMV%i not present\n", co->index); 731 return -ENODEV; 732 } 733 734 if (options) 735 uart_parse_options(options, &baud, &parity, &bits, &flow); 736 737 return uart_set_options(port, co, baud, parity, bits, flow); 738} 739 740static struct uart_driver mvebu_uart_driver; 741 742static struct console mvebu_uart_console = { 743 .name = "ttyMV", 744 .write = mvebu_uart_console_write, 745 .device = uart_console_device, 746 .setup = mvebu_uart_console_setup, 747 .flags = CON_PRINTBUFFER, 748 .index = -1, 749 .data = &mvebu_uart_driver, 750}; 751 752static int __init mvebu_uart_console_init(void) 753{ 754 register_console(&mvebu_uart_console); 755 return 0; 756} 757 758console_initcall(mvebu_uart_console_init); 759 760 761#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */ 762 763static struct uart_driver mvebu_uart_driver = { 764 .owner = THIS_MODULE, 765 .driver_name = DRIVER_NAME, 766 .dev_name = "ttyMV", 767 .nr = MVEBU_NR_UARTS, 768#ifdef CONFIG_SERIAL_MVEBU_CONSOLE 769 .cons = &mvebu_uart_console, 770#endif 771}; 772 773#if defined(CONFIG_PM) 774static int mvebu_uart_suspend(struct device *dev) 775{ 776 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 777 struct uart_port *port = mvuart->port; 778 779 uart_suspend_port(&mvebu_uart_driver, port); 780 781 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); 782 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); 783 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); 784 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); 785 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); 786 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); 787 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); 788 789 device_set_wakeup_enable(dev, true); 790 791 return 0; 792} 793 794static int mvebu_uart_resume(struct device *dev) 795{ 796 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 797 struct uart_port *port = mvuart->port; 798 799 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); 800 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); 801 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); 802 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); 803 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); 804 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); 805 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); 806 807 uart_resume_port(&mvebu_uart_driver, port); 808 809 return 0; 810} 811 812static const struct dev_pm_ops mvebu_uart_pm_ops = { 813 .suspend = mvebu_uart_suspend, 814 .resume = mvebu_uart_resume, 815}; 816#endif /* CONFIG_PM */ 817 818static const struct of_device_id mvebu_uart_of_match[]; 819 820/* Counter to keep track of each UART port id when not using CONFIG_OF */ 821static int uart_num_counter; 822 823static int mvebu_uart_probe(struct platform_device *pdev) 824{ 825 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 826 const struct of_device_id *match = of_match_device(mvebu_uart_of_match, 827 &pdev->dev); 828 struct uart_port *port; 829 struct mvebu_uart *mvuart; 830 int id, irq; 831 832 if (!reg) { 833 dev_err(&pdev->dev, "no registers defined\n"); 834 return -EINVAL; 835 } 836 837 /* Assume that all UART ports have a DT alias or none has */ 838 id = of_alias_get_id(pdev->dev.of_node, "serial"); 839 if (!pdev->dev.of_node || id < 0) 840 pdev->id = uart_num_counter++; 841 else 842 pdev->id = id; 843 844 if (pdev->id >= MVEBU_NR_UARTS) { 845 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", 846 MVEBU_NR_UARTS); 847 return -EINVAL; 848 } 849 850 port = &mvebu_uart_ports[pdev->id]; 851 852 spin_lock_init(&port->lock); 853 854 port->dev = &pdev->dev; 855 port->type = PORT_MVEBU; 856 port->ops = &mvebu_uart_ops; 857 port->regshift = 0; 858 859 port->fifosize = 32; 860 port->iotype = UPIO_MEM32; 861 port->flags = UPF_FIXED_PORT; 862 port->line = pdev->id; 863 864 /* 865 * IRQ number is not stored in this structure because we may have two of 866 * them per port (RX and TX). Instead, use the driver UART structure 867 * array so called ->irq[]. 868 */ 869 port->irq = 0; 870 port->irqflags = 0; 871 port->mapbase = reg->start; 872 873 port->membase = devm_ioremap_resource(&pdev->dev, reg); 874 if (IS_ERR(port->membase)) 875 return PTR_ERR(port->membase); 876 877 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), 878 GFP_KERNEL); 879 if (!mvuart) 880 return -ENOMEM; 881 882 /* Get controller data depending on the compatible string */ 883 mvuart->data = (struct mvebu_uart_driver_data *)match->data; 884 mvuart->port = port; 885 886 port->private_data = mvuart; 887 platform_set_drvdata(pdev, mvuart); 888 889 /* Get fixed clock frequency */ 890 mvuart->clk = devm_clk_get(&pdev->dev, NULL); 891 if (IS_ERR(mvuart->clk)) { 892 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) 893 return PTR_ERR(mvuart->clk); 894 895 if (IS_EXTENDED(port)) { 896 dev_err(&pdev->dev, "unable to get UART clock\n"); 897 return PTR_ERR(mvuart->clk); 898 } 899 } else { 900 if (!clk_prepare_enable(mvuart->clk)) 901 port->uartclk = clk_get_rate(mvuart->clk); 902 } 903 904 /* Manage interrupts */ 905 if (platform_irq_count(pdev) == 1) { 906 /* Old bindings: no name on the single unamed UART0 IRQ */ 907 irq = platform_get_irq(pdev, 0); 908 if (irq < 0) 909 return irq; 910 911 mvuart->irq[UART_IRQ_SUM] = irq; 912 } else { 913 /* 914 * New bindings: named interrupts (RX, TX) for both UARTS, 915 * only make use of uart-rx and uart-tx interrupts, do not use 916 * uart-sum of UART0 port. 917 */ 918 irq = platform_get_irq_byname(pdev, "uart-rx"); 919 if (irq < 0) 920 return irq; 921 922 mvuart->irq[UART_RX_IRQ] = irq; 923 924 irq = platform_get_irq_byname(pdev, "uart-tx"); 925 if (irq < 0) 926 return irq; 927 928 mvuart->irq[UART_TX_IRQ] = irq; 929 } 930 931 /* UART Soft Reset*/ 932 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); 933 udelay(1); 934 writel(0, port->membase + UART_CTRL(port)); 935 936 return uart_add_one_port(&mvebu_uart_driver, port); 937} 938 939static struct mvebu_uart_driver_data uart_std_driver_data = { 940 .is_ext = false, 941 .regs.rbr = UART_STD_RBR, 942 .regs.tsh = UART_STD_TSH, 943 .regs.ctrl = UART_STD_CTRL1, 944 .regs.intr = UART_STD_CTRL2, 945 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT, 946 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT, 947 .flags.stat_tx_rdy = STAT_STD_TX_RDY, 948 .flags.stat_rx_rdy = STAT_STD_RX_RDY, 949}; 950 951static struct mvebu_uart_driver_data uart_ext_driver_data = { 952 .is_ext = true, 953 .regs.rbr = UART_EXT_RBR, 954 .regs.tsh = UART_EXT_TSH, 955 .regs.ctrl = UART_EXT_CTRL1, 956 .regs.intr = UART_EXT_CTRL2, 957 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT, 958 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT, 959 .flags.stat_tx_rdy = STAT_EXT_TX_RDY, 960 .flags.stat_rx_rdy = STAT_EXT_RX_RDY, 961}; 962 963/* Match table for of_platform binding */ 964static const struct of_device_id mvebu_uart_of_match[] = { 965 { 966 .compatible = "marvell,armada-3700-uart", 967 .data = (void *)&uart_std_driver_data, 968 }, 969 { 970 .compatible = "marvell,armada-3700-uart-ext", 971 .data = (void *)&uart_ext_driver_data, 972 }, 973 {} 974}; 975 976static struct platform_driver mvebu_uart_platform_driver = { 977 .probe = mvebu_uart_probe, 978 .driver = { 979 .name = "mvebu-uart", 980 .of_match_table = of_match_ptr(mvebu_uart_of_match), 981 .suppress_bind_attrs = true, 982#if defined(CONFIG_PM) 983 .pm = &mvebu_uart_pm_ops, 984#endif /* CONFIG_PM */ 985 }, 986}; 987 988static int __init mvebu_uart_init(void) 989{ 990 int ret; 991 992 ret = uart_register_driver(&mvebu_uart_driver); 993 if (ret) 994 return ret; 995 996 ret = platform_driver_register(&mvebu_uart_platform_driver); 997 if (ret) 998 uart_unregister_driver(&mvebu_uart_driver); 999 1000 return ret; 1001} 1002arch_initcall(mvebu_uart_init); 1003