1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. 4 * 5 * FIXME According to the usermanual the status bits in the status register 6 * are only updated when the peripherals access the FIFO and not when the 7 * CPU access them. So since we use this bits to know when we stop writing 8 * and reading, they may not be updated in-time and a race condition may 9 * exists. But I haven't be able to prove this and I don't care. But if 10 * any problem arises, it might worth checking. The TX/RX FIFO Stats 11 * registers should be used in addition. 12 * Update: Actually, they seem updated ... At least the bits we use. 13 * 14 * 15 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 16 * 17 * Some of the code has been inspired/copied from the 2.4 code written 18 * by Dale Farnsworth <dfarnsworth@mvista.com>. 19 * 20 * Copyright (C) 2008 Freescale Semiconductor Inc. 21 * John Rigby <jrigby@gmail.com> 22 * Added support for MPC5121 23 * Copyright (C) 2006 Secret Lab Technologies Ltd. 24 * Grant Likely <grant.likely@secretlab.ca> 25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> 26 * Copyright (C) 2003 MontaVista, Software, Inc. 27 */ 28 29#undef DEBUG 30 31#include <linux/device.h> 32#include <linux/module.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/serial.h> 36#include <linux/sysrq.h> 37#include <linux/console.h> 38#include <linux/delay.h> 39#include <linux/io.h> 40#include <linux/of.h> 41#include <linux/of_platform.h> 42#include <linux/clk.h> 43 44#include <asm/mpc52xx.h> 45#include <asm/mpc52xx_psc.h> 46 47#include <linux/serial_core.h> 48 49 50/* We've been assigned a range on the "Low-density serial ports" major */ 51#define SERIAL_PSC_MAJOR 204 52#define SERIAL_PSC_MINOR 148 53 54 55#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ 56 57 58static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; 59 /* Rem: - We use the read_status_mask as a shadow of 60 * psc->mpc52xx_psc_imr 61 * - It's important that is array is all zero on start as we 62 * use it to know if it's initialized or not ! If it's not sure 63 * it's cleared, then a memset(...,0,...) should be added to 64 * the console_init 65 */ 66 67/* lookup table for matching device nodes to index numbers */ 68static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; 69 70static void mpc52xx_uart_of_enumerate(void); 71 72 73#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) 74 75 76/* Forward declaration of the interruption handling routine */ 77static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); 78static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); 79 80/* ======================================================================== */ 81/* PSC fifo operations for isolating differences between 52xx and 512x */ 82/* ======================================================================== */ 83 84struct psc_ops { 85 void (*fifo_init)(struct uart_port *port); 86 int (*raw_rx_rdy)(struct uart_port *port); 87 int (*raw_tx_rdy)(struct uart_port *port); 88 int (*rx_rdy)(struct uart_port *port); 89 int (*tx_rdy)(struct uart_port *port); 90 int (*tx_empty)(struct uart_port *port); 91 void (*stop_rx)(struct uart_port *port); 92 void (*start_tx)(struct uart_port *port); 93 void (*stop_tx)(struct uart_port *port); 94 void (*rx_clr_irq)(struct uart_port *port); 95 void (*tx_clr_irq)(struct uart_port *port); 96 void (*write_char)(struct uart_port *port, unsigned char c); 97 unsigned char (*read_char)(struct uart_port *port); 98 void (*cw_disable_ints)(struct uart_port *port); 99 void (*cw_restore_ints)(struct uart_port *port); 100 unsigned int (*set_baudrate)(struct uart_port *port, 101 struct ktermios *new, 102 struct ktermios *old); 103 int (*clock_alloc)(struct uart_port *port); 104 void (*clock_relse)(struct uart_port *port); 105 int (*clock)(struct uart_port *port, int enable); 106 int (*fifoc_init)(void); 107 void (*fifoc_uninit)(void); 108 void (*get_irq)(struct uart_port *, struct device_node *); 109 irqreturn_t (*handle_irq)(struct uart_port *port); 110 u16 (*get_status)(struct uart_port *port); 111 u8 (*get_ipcr)(struct uart_port *port); 112 void (*command)(struct uart_port *port, u8 cmd); 113 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); 114 void (*set_rts)(struct uart_port *port, int state); 115 void (*enable_ms)(struct uart_port *port); 116 void (*set_sicr)(struct uart_port *port, u32 val); 117 void (*set_imr)(struct uart_port *port, u16 val); 118 u8 (*get_mr1)(struct uart_port *port); 119}; 120 121/* setting the prescaler and divisor reg is common for all chips */ 122static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, 123 u16 prescaler, unsigned int divisor) 124{ 125 /* select prescaler */ 126 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); 127 out_8(&psc->ctur, divisor >> 8); 128 out_8(&psc->ctlr, divisor & 0xff); 129} 130 131static u16 mpc52xx_psc_get_status(struct uart_port *port) 132{ 133 return in_be16(&PSC(port)->mpc52xx_psc_status); 134} 135 136static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) 137{ 138 return in_8(&PSC(port)->mpc52xx_psc_ipcr); 139} 140 141static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) 142{ 143 out_8(&PSC(port)->command, cmd); 144} 145 146static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 147{ 148 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 149 out_8(&PSC(port)->mode, mr1); 150 out_8(&PSC(port)->mode, mr2); 151} 152 153static void mpc52xx_psc_set_rts(struct uart_port *port, int state) 154{ 155 if (state) 156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); 157 else 158 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); 159} 160 161static void mpc52xx_psc_enable_ms(struct uart_port *port) 162{ 163 struct mpc52xx_psc __iomem *psc = PSC(port); 164 165 /* clear D_*-bits by reading them */ 166 in_8(&psc->mpc52xx_psc_ipcr); 167 /* enable CTS and DCD as IPC interrupts */ 168 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 169 170 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 171 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 172} 173 174static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) 175{ 176 out_be32(&PSC(port)->sicr, val); 177} 178 179static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) 180{ 181 out_be16(&PSC(port)->mpc52xx_psc_imr, val); 182} 183 184static u8 mpc52xx_psc_get_mr1(struct uart_port *port) 185{ 186 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 187 return in_8(&PSC(port)->mode); 188} 189 190#ifdef CONFIG_PPC_MPC52xx 191#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) 192static void mpc52xx_psc_fifo_init(struct uart_port *port) 193{ 194 struct mpc52xx_psc __iomem *psc = PSC(port); 195 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); 196 197 out_8(&fifo->rfcntl, 0x00); 198 out_be16(&fifo->rfalarm, 0x1ff); 199 out_8(&fifo->tfcntl, 0x07); 200 out_be16(&fifo->tfalarm, 0x80); 201 202 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; 203 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 204} 205 206static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) 207{ 208 return in_be16(&PSC(port)->mpc52xx_psc_status) 209 & MPC52xx_PSC_SR_RXRDY; 210} 211 212static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) 213{ 214 return in_be16(&PSC(port)->mpc52xx_psc_status) 215 & MPC52xx_PSC_SR_TXRDY; 216} 217 218 219static int mpc52xx_psc_rx_rdy(struct uart_port *port) 220{ 221 return in_be16(&PSC(port)->mpc52xx_psc_isr) 222 & port->read_status_mask 223 & MPC52xx_PSC_IMR_RXRDY; 224} 225 226static int mpc52xx_psc_tx_rdy(struct uart_port *port) 227{ 228 return in_be16(&PSC(port)->mpc52xx_psc_isr) 229 & port->read_status_mask 230 & MPC52xx_PSC_IMR_TXRDY; 231} 232 233static int mpc52xx_psc_tx_empty(struct uart_port *port) 234{ 235 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status); 236 237 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; 238} 239 240static void mpc52xx_psc_start_tx(struct uart_port *port) 241{ 242 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 243 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 244} 245 246static void mpc52xx_psc_stop_tx(struct uart_port *port) 247{ 248 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; 249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 250} 251 252static void mpc52xx_psc_stop_rx(struct uart_port *port) 253{ 254 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; 255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 256} 257 258static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) 259{ 260} 261 262static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) 263{ 264} 265 266static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) 267{ 268 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); 269} 270 271static unsigned char mpc52xx_psc_read_char(struct uart_port *port) 272{ 273 return in_8(&PSC(port)->mpc52xx_psc_buffer_8); 274} 275 276static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) 277{ 278 out_be16(&PSC(port)->mpc52xx_psc_imr, 0); 279} 280 281static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) 282{ 283 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 284} 285 286static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, 287 struct ktermios *new, 288 struct ktermios *old) 289{ 290 unsigned int baud; 291 unsigned int divisor; 292 293 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ 294 baud = uart_get_baud_rate(port, new, old, 295 port->uartclk / (32 * 0xffff) + 1, 296 port->uartclk / 32); 297 divisor = (port->uartclk + 16 * baud) / (32 * baud); 298 299 /* enable the /32 prescaler and set the divisor */ 300 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 301 return baud; 302} 303 304static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, 305 struct ktermios *new, 306 struct ktermios *old) 307{ 308 unsigned int baud; 309 unsigned int divisor; 310 u16 prescaler; 311 312 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the 313 * ipb freq */ 314 baud = uart_get_baud_rate(port, new, old, 315 port->uartclk / (32 * 0xffff) + 1, 316 port->uartclk / 4); 317 divisor = (port->uartclk + 2 * baud) / (4 * baud); 318 319 /* select the proper prescaler and set the divisor 320 * prefer high prescaler for more tolerance on low baudrates */ 321 if (divisor > 0xffff || baud <= 115200) { 322 divisor = (divisor + 4) / 8; 323 prescaler = 0xdd00; /* /32 */ 324 } else 325 prescaler = 0xff00; /* /4 */ 326 mpc52xx_set_divisor(PSC(port), prescaler, divisor); 327 return baud; 328} 329 330static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) 331{ 332 port->irqflags = 0; 333 port->irq = irq_of_parse_and_map(np, 0); 334} 335 336/* 52xx specific interrupt handler. The caller holds the port lock */ 337static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) 338{ 339 return mpc5xxx_uart_process_int(port); 340} 341 342static const struct psc_ops mpc52xx_psc_ops = { 343 .fifo_init = mpc52xx_psc_fifo_init, 344 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 345 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 346 .rx_rdy = mpc52xx_psc_rx_rdy, 347 .tx_rdy = mpc52xx_psc_tx_rdy, 348 .tx_empty = mpc52xx_psc_tx_empty, 349 .stop_rx = mpc52xx_psc_stop_rx, 350 .start_tx = mpc52xx_psc_start_tx, 351 .stop_tx = mpc52xx_psc_stop_tx, 352 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 353 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 354 .write_char = mpc52xx_psc_write_char, 355 .read_char = mpc52xx_psc_read_char, 356 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 357 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 358 .set_baudrate = mpc5200_psc_set_baudrate, 359 .get_irq = mpc52xx_psc_get_irq, 360 .handle_irq = mpc52xx_psc_handle_irq, 361 .get_status = mpc52xx_psc_get_status, 362 .get_ipcr = mpc52xx_psc_get_ipcr, 363 .command = mpc52xx_psc_command, 364 .set_mode = mpc52xx_psc_set_mode, 365 .set_rts = mpc52xx_psc_set_rts, 366 .enable_ms = mpc52xx_psc_enable_ms, 367 .set_sicr = mpc52xx_psc_set_sicr, 368 .set_imr = mpc52xx_psc_set_imr, 369 .get_mr1 = mpc52xx_psc_get_mr1, 370}; 371 372static const struct psc_ops mpc5200b_psc_ops = { 373 .fifo_init = mpc52xx_psc_fifo_init, 374 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 375 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 376 .rx_rdy = mpc52xx_psc_rx_rdy, 377 .tx_rdy = mpc52xx_psc_tx_rdy, 378 .tx_empty = mpc52xx_psc_tx_empty, 379 .stop_rx = mpc52xx_psc_stop_rx, 380 .start_tx = mpc52xx_psc_start_tx, 381 .stop_tx = mpc52xx_psc_stop_tx, 382 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 383 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 384 .write_char = mpc52xx_psc_write_char, 385 .read_char = mpc52xx_psc_read_char, 386 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 387 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 388 .set_baudrate = mpc5200b_psc_set_baudrate, 389 .get_irq = mpc52xx_psc_get_irq, 390 .handle_irq = mpc52xx_psc_handle_irq, 391 .get_status = mpc52xx_psc_get_status, 392 .get_ipcr = mpc52xx_psc_get_ipcr, 393 .command = mpc52xx_psc_command, 394 .set_mode = mpc52xx_psc_set_mode, 395 .set_rts = mpc52xx_psc_set_rts, 396 .enable_ms = mpc52xx_psc_enable_ms, 397 .set_sicr = mpc52xx_psc_set_sicr, 398 .set_imr = mpc52xx_psc_set_imr, 399 .get_mr1 = mpc52xx_psc_get_mr1, 400}; 401 402#endif /* CONFIG_PPC_MPC52xx */ 403 404#ifdef CONFIG_PPC_MPC512x 405#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) 406 407/* PSC FIFO Controller for mpc512x */ 408struct psc_fifoc { 409 u32 fifoc_cmd; 410 u32 fifoc_int; 411 u32 fifoc_dma; 412 u32 fifoc_axe; 413 u32 fifoc_debug; 414}; 415 416static struct psc_fifoc __iomem *psc_fifoc; 417static unsigned int psc_fifoc_irq; 418static struct clk *psc_fifoc_clk; 419 420static void mpc512x_psc_fifo_init(struct uart_port *port) 421{ 422 /* /32 prescaler */ 423 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); 424 425 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 426 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 427 out_be32(&FIFO_512x(port)->txalarm, 1); 428 out_be32(&FIFO_512x(port)->tximr, 0); 429 430 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 431 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 432 out_be32(&FIFO_512x(port)->rxalarm, 1); 433 out_be32(&FIFO_512x(port)->rximr, 0); 434 435 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); 436 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); 437} 438 439static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) 440{ 441 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 442} 443 444static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) 445{ 446 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); 447} 448 449static int mpc512x_psc_rx_rdy(struct uart_port *port) 450{ 451 return in_be32(&FIFO_512x(port)->rxsr) 452 & in_be32(&FIFO_512x(port)->rximr) 453 & MPC512x_PSC_FIFO_ALARM; 454} 455 456static int mpc512x_psc_tx_rdy(struct uart_port *port) 457{ 458 return in_be32(&FIFO_512x(port)->txsr) 459 & in_be32(&FIFO_512x(port)->tximr) 460 & MPC512x_PSC_FIFO_ALARM; 461} 462 463static int mpc512x_psc_tx_empty(struct uart_port *port) 464{ 465 return in_be32(&FIFO_512x(port)->txsr) 466 & MPC512x_PSC_FIFO_EMPTY; 467} 468 469static void mpc512x_psc_stop_rx(struct uart_port *port) 470{ 471 unsigned long rx_fifo_imr; 472 473 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); 474 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 475 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); 476} 477 478static void mpc512x_psc_start_tx(struct uart_port *port) 479{ 480 unsigned long tx_fifo_imr; 481 482 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 483 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 484 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 485} 486 487static void mpc512x_psc_stop_tx(struct uart_port *port) 488{ 489 unsigned long tx_fifo_imr; 490 491 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 492 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 493 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 494} 495 496static void mpc512x_psc_rx_clr_irq(struct uart_port *port) 497{ 498 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); 499} 500 501static void mpc512x_psc_tx_clr_irq(struct uart_port *port) 502{ 503 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); 504} 505 506static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) 507{ 508 out_8(&FIFO_512x(port)->txdata_8, c); 509} 510 511static unsigned char mpc512x_psc_read_char(struct uart_port *port) 512{ 513 return in_8(&FIFO_512x(port)->rxdata_8); 514} 515 516static void mpc512x_psc_cw_disable_ints(struct uart_port *port) 517{ 518 port->read_status_mask = 519 in_be32(&FIFO_512x(port)->tximr) << 16 | 520 in_be32(&FIFO_512x(port)->rximr); 521 out_be32(&FIFO_512x(port)->tximr, 0); 522 out_be32(&FIFO_512x(port)->rximr, 0); 523} 524 525static void mpc512x_psc_cw_restore_ints(struct uart_port *port) 526{ 527 out_be32(&FIFO_512x(port)->tximr, 528 (port->read_status_mask >> 16) & 0x7f); 529 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); 530} 531 532static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, 533 struct ktermios *new, 534 struct ktermios *old) 535{ 536 unsigned int baud; 537 unsigned int divisor; 538 539 /* 540 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on 541 * pg. 30-10 that the chip supports a /32 and a /10 prescaler. 542 * Furthermore, it states that "After reset, the prescaler by 10 543 * for the UART mode is selected", but the reset register value is 544 * 0x0000 which means a /32 prescaler. This is wrong. 545 * 546 * In reality using /32 prescaler doesn't work, as it is not supported! 547 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", 548 * Chapter 4.1 PSC in UART Mode. 549 * Calculate with a /16 prescaler here. 550 */ 551 552 /* uartclk contains the ips freq */ 553 baud = uart_get_baud_rate(port, new, old, 554 port->uartclk / (16 * 0xffff) + 1, 555 port->uartclk / 16); 556 divisor = (port->uartclk + 8 * baud) / (16 * baud); 557 558 /* enable the /16 prescaler and set the divisor */ 559 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 560 return baud; 561} 562 563/* Init PSC FIFO Controller */ 564static int __init mpc512x_psc_fifoc_init(void) 565{ 566 int err; 567 struct device_node *np; 568 struct clk *clk; 569 570 /* default error code, potentially overwritten by clock calls */ 571 err = -ENODEV; 572 573 np = of_find_compatible_node(NULL, NULL, 574 "fsl,mpc5121-psc-fifo"); 575 if (!np) { 576 pr_err("%s: Can't find FIFOC node\n", __func__); 577 goto out_err; 578 } 579 580 clk = of_clk_get(np, 0); 581 if (IS_ERR(clk)) { 582 /* backwards compat with device trees that lack clock specs */ 583 clk = clk_get_sys(np->name, "ipg"); 584 } 585 if (IS_ERR(clk)) { 586 pr_err("%s: Can't lookup FIFO clock\n", __func__); 587 err = PTR_ERR(clk); 588 goto out_ofnode_put; 589 } 590 if (clk_prepare_enable(clk)) { 591 pr_err("%s: Can't enable FIFO clock\n", __func__); 592 clk_put(clk); 593 goto out_ofnode_put; 594 } 595 psc_fifoc_clk = clk; 596 597 psc_fifoc = of_iomap(np, 0); 598 if (!psc_fifoc) { 599 pr_err("%s: Can't map FIFOC\n", __func__); 600 goto out_clk_disable; 601 } 602 603 psc_fifoc_irq = irq_of_parse_and_map(np, 0); 604 if (psc_fifoc_irq == 0) { 605 pr_err("%s: Can't get FIFOC irq\n", __func__); 606 goto out_unmap; 607 } 608 609 of_node_put(np); 610 return 0; 611 612out_unmap: 613 iounmap(psc_fifoc); 614out_clk_disable: 615 clk_disable_unprepare(psc_fifoc_clk); 616 clk_put(psc_fifoc_clk); 617out_ofnode_put: 618 of_node_put(np); 619out_err: 620 return err; 621} 622 623static void __exit mpc512x_psc_fifoc_uninit(void) 624{ 625 iounmap(psc_fifoc); 626 627 /* disable the clock, errors are not fatal */ 628 if (psc_fifoc_clk) { 629 clk_disable_unprepare(psc_fifoc_clk); 630 clk_put(psc_fifoc_clk); 631 psc_fifoc_clk = NULL; 632 } 633} 634 635/* 512x specific interrupt handler. The caller holds the port lock */ 636static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) 637{ 638 unsigned long fifoc_int; 639 int psc_num; 640 641 /* Read pending PSC FIFOC interrupts */ 642 fifoc_int = in_be32(&psc_fifoc->fifoc_int); 643 644 /* Check if it is an interrupt for this port */ 645 psc_num = (port->mapbase & 0xf00) >> 8; 646 if (test_bit(psc_num, &fifoc_int) || 647 test_bit(psc_num + 16, &fifoc_int)) 648 return mpc5xxx_uart_process_int(port); 649 650 return IRQ_NONE; 651} 652 653static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM]; 654static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM]; 655 656/* called from within the .request_port() callback (allocation) */ 657static int mpc512x_psc_alloc_clock(struct uart_port *port) 658{ 659 int psc_num; 660 struct clk *clk; 661 int err; 662 663 psc_num = (port->mapbase & 0xf00) >> 8; 664 665 clk = devm_clk_get(port->dev, "mclk"); 666 if (IS_ERR(clk)) { 667 dev_err(port->dev, "Failed to get MCLK!\n"); 668 err = PTR_ERR(clk); 669 goto out_err; 670 } 671 err = clk_prepare_enable(clk); 672 if (err) { 673 dev_err(port->dev, "Failed to enable MCLK!\n"); 674 goto out_err; 675 } 676 psc_mclk_clk[psc_num] = clk; 677 678 clk = devm_clk_get(port->dev, "ipg"); 679 if (IS_ERR(clk)) { 680 dev_err(port->dev, "Failed to get IPG clock!\n"); 681 err = PTR_ERR(clk); 682 goto out_err; 683 } 684 err = clk_prepare_enable(clk); 685 if (err) { 686 dev_err(port->dev, "Failed to enable IPG clock!\n"); 687 goto out_err; 688 } 689 psc_ipg_clk[psc_num] = clk; 690 691 return 0; 692 693out_err: 694 if (psc_mclk_clk[psc_num]) { 695 clk_disable_unprepare(psc_mclk_clk[psc_num]); 696 psc_mclk_clk[psc_num] = NULL; 697 } 698 if (psc_ipg_clk[psc_num]) { 699 clk_disable_unprepare(psc_ipg_clk[psc_num]); 700 psc_ipg_clk[psc_num] = NULL; 701 } 702 return err; 703} 704 705/* called from within the .release_port() callback (release) */ 706static void mpc512x_psc_relse_clock(struct uart_port *port) 707{ 708 int psc_num; 709 struct clk *clk; 710 711 psc_num = (port->mapbase & 0xf00) >> 8; 712 clk = psc_mclk_clk[psc_num]; 713 if (clk) { 714 clk_disable_unprepare(clk); 715 psc_mclk_clk[psc_num] = NULL; 716 } 717 if (psc_ipg_clk[psc_num]) { 718 clk_disable_unprepare(psc_ipg_clk[psc_num]); 719 psc_ipg_clk[psc_num] = NULL; 720 } 721} 722 723/* implementation of the .clock() callback (enable/disable) */ 724static int mpc512x_psc_endis_clock(struct uart_port *port, int enable) 725{ 726 int psc_num; 727 struct clk *psc_clk; 728 int ret; 729 730 if (uart_console(port)) 731 return 0; 732 733 psc_num = (port->mapbase & 0xf00) >> 8; 734 psc_clk = psc_mclk_clk[psc_num]; 735 if (!psc_clk) { 736 dev_err(port->dev, "Failed to get PSC clock entry!\n"); 737 return -ENODEV; 738 } 739 740 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis"); 741 if (enable) { 742 ret = clk_enable(psc_clk); 743 if (ret) 744 dev_err(port->dev, "Failed to enable MCLK!\n"); 745 return ret; 746 } else { 747 clk_disable(psc_clk); 748 return 0; 749 } 750} 751 752static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) 753{ 754 port->irqflags = IRQF_SHARED; 755 port->irq = psc_fifoc_irq; 756} 757#endif 758 759#ifdef CONFIG_PPC_MPC512x 760 761#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) 762#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) 763 764static void mpc5125_psc_fifo_init(struct uart_port *port) 765{ 766 /* /32 prescaler */ 767 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); 768 769 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 770 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 771 out_be32(&FIFO_5125(port)->txalarm, 1); 772 out_be32(&FIFO_5125(port)->tximr, 0); 773 774 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 775 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 776 out_be32(&FIFO_5125(port)->rxalarm, 1); 777 out_be32(&FIFO_5125(port)->rximr, 0); 778 779 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); 780 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); 781} 782 783static int mpc5125_psc_raw_rx_rdy(struct uart_port *port) 784{ 785 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 786} 787 788static int mpc5125_psc_raw_tx_rdy(struct uart_port *port) 789{ 790 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); 791} 792 793static int mpc5125_psc_rx_rdy(struct uart_port *port) 794{ 795 return in_be32(&FIFO_5125(port)->rxsr) & 796 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; 797} 798 799static int mpc5125_psc_tx_rdy(struct uart_port *port) 800{ 801 return in_be32(&FIFO_5125(port)->txsr) & 802 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; 803} 804 805static int mpc5125_psc_tx_empty(struct uart_port *port) 806{ 807 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; 808} 809 810static void mpc5125_psc_stop_rx(struct uart_port *port) 811{ 812 unsigned long rx_fifo_imr; 813 814 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); 815 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 816 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); 817} 818 819static void mpc5125_psc_start_tx(struct uart_port *port) 820{ 821 unsigned long tx_fifo_imr; 822 823 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 824 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 825 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 826} 827 828static void mpc5125_psc_stop_tx(struct uart_port *port) 829{ 830 unsigned long tx_fifo_imr; 831 832 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 833 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 834 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 835} 836 837static void mpc5125_psc_rx_clr_irq(struct uart_port *port) 838{ 839 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); 840} 841 842static void mpc5125_psc_tx_clr_irq(struct uart_port *port) 843{ 844 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); 845} 846 847static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) 848{ 849 out_8(&FIFO_5125(port)->txdata_8, c); 850} 851 852static unsigned char mpc5125_psc_read_char(struct uart_port *port) 853{ 854 return in_8(&FIFO_5125(port)->rxdata_8); 855} 856 857static void mpc5125_psc_cw_disable_ints(struct uart_port *port) 858{ 859 port->read_status_mask = 860 in_be32(&FIFO_5125(port)->tximr) << 16 | 861 in_be32(&FIFO_5125(port)->rximr); 862 out_be32(&FIFO_5125(port)->tximr, 0); 863 out_be32(&FIFO_5125(port)->rximr, 0); 864} 865 866static void mpc5125_psc_cw_restore_ints(struct uart_port *port) 867{ 868 out_be32(&FIFO_5125(port)->tximr, 869 (port->read_status_mask >> 16) & 0x7f); 870 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); 871} 872 873static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, 874 u8 prescaler, unsigned int divisor) 875{ 876 /* select prescaler */ 877 out_8(&psc->mpc52xx_psc_clock_select, prescaler); 878 out_8(&psc->ctur, divisor >> 8); 879 out_8(&psc->ctlr, divisor & 0xff); 880} 881 882static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, 883 struct ktermios *new, 884 struct ktermios *old) 885{ 886 unsigned int baud; 887 unsigned int divisor; 888 889 /* 890 * Calculate with a /16 prescaler here. 891 */ 892 893 /* uartclk contains the ips freq */ 894 baud = uart_get_baud_rate(port, new, old, 895 port->uartclk / (16 * 0xffff) + 1, 896 port->uartclk / 16); 897 divisor = (port->uartclk + 8 * baud) / (16 * baud); 898 899 /* enable the /16 prescaler and set the divisor */ 900 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); 901 return baud; 902} 903 904/* 905 * MPC5125 have compatible PSC FIFO Controller. 906 * Special init not needed. 907 */ 908static u16 mpc5125_psc_get_status(struct uart_port *port) 909{ 910 return in_be16(&PSC_5125(port)->mpc52xx_psc_status); 911} 912 913static u8 mpc5125_psc_get_ipcr(struct uart_port *port) 914{ 915 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); 916} 917 918static void mpc5125_psc_command(struct uart_port *port, u8 cmd) 919{ 920 out_8(&PSC_5125(port)->command, cmd); 921} 922 923static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 924{ 925 out_8(&PSC_5125(port)->mr1, mr1); 926 out_8(&PSC_5125(port)->mr2, mr2); 927} 928 929static void mpc5125_psc_set_rts(struct uart_port *port, int state) 930{ 931 if (state & TIOCM_RTS) 932 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); 933 else 934 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); 935} 936 937static void mpc5125_psc_enable_ms(struct uart_port *port) 938{ 939 struct mpc5125_psc __iomem *psc = PSC_5125(port); 940 941 /* clear D_*-bits by reading them */ 942 in_8(&psc->mpc52xx_psc_ipcr); 943 /* enable CTS and DCD as IPC interrupts */ 944 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 945 946 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 947 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 948} 949 950static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) 951{ 952 out_be32(&PSC_5125(port)->sicr, val); 953} 954 955static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) 956{ 957 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); 958} 959 960static u8 mpc5125_psc_get_mr1(struct uart_port *port) 961{ 962 return in_8(&PSC_5125(port)->mr1); 963} 964 965static const struct psc_ops mpc5125_psc_ops = { 966 .fifo_init = mpc5125_psc_fifo_init, 967 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, 968 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, 969 .rx_rdy = mpc5125_psc_rx_rdy, 970 .tx_rdy = mpc5125_psc_tx_rdy, 971 .tx_empty = mpc5125_psc_tx_empty, 972 .stop_rx = mpc5125_psc_stop_rx, 973 .start_tx = mpc5125_psc_start_tx, 974 .stop_tx = mpc5125_psc_stop_tx, 975 .rx_clr_irq = mpc5125_psc_rx_clr_irq, 976 .tx_clr_irq = mpc5125_psc_tx_clr_irq, 977 .write_char = mpc5125_psc_write_char, 978 .read_char = mpc5125_psc_read_char, 979 .cw_disable_ints = mpc5125_psc_cw_disable_ints, 980 .cw_restore_ints = mpc5125_psc_cw_restore_ints, 981 .set_baudrate = mpc5125_psc_set_baudrate, 982 .clock_alloc = mpc512x_psc_alloc_clock, 983 .clock_relse = mpc512x_psc_relse_clock, 984 .clock = mpc512x_psc_endis_clock, 985 .fifoc_init = mpc512x_psc_fifoc_init, 986 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 987 .get_irq = mpc512x_psc_get_irq, 988 .handle_irq = mpc512x_psc_handle_irq, 989 .get_status = mpc5125_psc_get_status, 990 .get_ipcr = mpc5125_psc_get_ipcr, 991 .command = mpc5125_psc_command, 992 .set_mode = mpc5125_psc_set_mode, 993 .set_rts = mpc5125_psc_set_rts, 994 .enable_ms = mpc5125_psc_enable_ms, 995 .set_sicr = mpc5125_psc_set_sicr, 996 .set_imr = mpc5125_psc_set_imr, 997 .get_mr1 = mpc5125_psc_get_mr1, 998}; 999 1000static const struct psc_ops mpc512x_psc_ops = { 1001 .fifo_init = mpc512x_psc_fifo_init, 1002 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, 1003 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, 1004 .rx_rdy = mpc512x_psc_rx_rdy, 1005 .tx_rdy = mpc512x_psc_tx_rdy, 1006 .tx_empty = mpc512x_psc_tx_empty, 1007 .stop_rx = mpc512x_psc_stop_rx, 1008 .start_tx = mpc512x_psc_start_tx, 1009 .stop_tx = mpc512x_psc_stop_tx, 1010 .rx_clr_irq = mpc512x_psc_rx_clr_irq, 1011 .tx_clr_irq = mpc512x_psc_tx_clr_irq, 1012 .write_char = mpc512x_psc_write_char, 1013 .read_char = mpc512x_psc_read_char, 1014 .cw_disable_ints = mpc512x_psc_cw_disable_ints, 1015 .cw_restore_ints = mpc512x_psc_cw_restore_ints, 1016 .set_baudrate = mpc512x_psc_set_baudrate, 1017 .clock_alloc = mpc512x_psc_alloc_clock, 1018 .clock_relse = mpc512x_psc_relse_clock, 1019 .clock = mpc512x_psc_endis_clock, 1020 .fifoc_init = mpc512x_psc_fifoc_init, 1021 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 1022 .get_irq = mpc512x_psc_get_irq, 1023 .handle_irq = mpc512x_psc_handle_irq, 1024 .get_status = mpc52xx_psc_get_status, 1025 .get_ipcr = mpc52xx_psc_get_ipcr, 1026 .command = mpc52xx_psc_command, 1027 .set_mode = mpc52xx_psc_set_mode, 1028 .set_rts = mpc52xx_psc_set_rts, 1029 .enable_ms = mpc52xx_psc_enable_ms, 1030 .set_sicr = mpc52xx_psc_set_sicr, 1031 .set_imr = mpc52xx_psc_set_imr, 1032 .get_mr1 = mpc52xx_psc_get_mr1, 1033}; 1034#endif /* CONFIG_PPC_MPC512x */ 1035 1036 1037static const struct psc_ops *psc_ops; 1038 1039/* ======================================================================== */ 1040/* UART operations */ 1041/* ======================================================================== */ 1042 1043static unsigned int 1044mpc52xx_uart_tx_empty(struct uart_port *port) 1045{ 1046 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; 1047} 1048 1049static void 1050mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1051{ 1052 psc_ops->set_rts(port, mctrl & TIOCM_RTS); 1053} 1054 1055static unsigned int 1056mpc52xx_uart_get_mctrl(struct uart_port *port) 1057{ 1058 unsigned int ret = TIOCM_DSR; 1059 u8 status = psc_ops->get_ipcr(port); 1060 1061 if (!(status & MPC52xx_PSC_CTS)) 1062 ret |= TIOCM_CTS; 1063 if (!(status & MPC52xx_PSC_DCD)) 1064 ret |= TIOCM_CAR; 1065 1066 return ret; 1067} 1068 1069static void 1070mpc52xx_uart_stop_tx(struct uart_port *port) 1071{ 1072 /* port->lock taken by caller */ 1073 psc_ops->stop_tx(port); 1074} 1075 1076static void 1077mpc52xx_uart_start_tx(struct uart_port *port) 1078{ 1079 /* port->lock taken by caller */ 1080 psc_ops->start_tx(port); 1081} 1082 1083static void 1084mpc52xx_uart_stop_rx(struct uart_port *port) 1085{ 1086 /* port->lock taken by caller */ 1087 psc_ops->stop_rx(port); 1088} 1089 1090static void 1091mpc52xx_uart_enable_ms(struct uart_port *port) 1092{ 1093 psc_ops->enable_ms(port); 1094} 1095 1096static void 1097mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 1098{ 1099 unsigned long flags; 1100 spin_lock_irqsave(&port->lock, flags); 1101 1102 if (ctl == -1) 1103 psc_ops->command(port, MPC52xx_PSC_START_BRK); 1104 else 1105 psc_ops->command(port, MPC52xx_PSC_STOP_BRK); 1106 1107 spin_unlock_irqrestore(&port->lock, flags); 1108} 1109 1110static int 1111mpc52xx_uart_startup(struct uart_port *port) 1112{ 1113 int ret; 1114 1115 if (psc_ops->clock) { 1116 ret = psc_ops->clock(port, 1); 1117 if (ret) 1118 return ret; 1119 } 1120 1121 /* Request IRQ */ 1122 ret = request_irq(port->irq, mpc52xx_uart_int, 1123 port->irqflags, "mpc52xx_psc_uart", port); 1124 if (ret) 1125 return ret; 1126 1127 /* Reset/activate the port, clear and enable interrupts */ 1128 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1129 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1130 1131 /* 1132 * According to Freescale's support the RST_TX command can produce a 1133 * spike on the TX pin. So they recommend to delay "for one character". 1134 * One millisecond should be enough for everyone. 1135 */ 1136 msleep(1); 1137 1138 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ 1139 1140 psc_ops->fifo_init(port); 1141 1142 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1143 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1144 1145 return 0; 1146} 1147 1148static void 1149mpc52xx_uart_shutdown(struct uart_port *port) 1150{ 1151 /* Shut down the port. Leave TX active if on a console port */ 1152 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1153 if (!uart_console(port)) 1154 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1155 1156 port->read_status_mask = 0; 1157 psc_ops->set_imr(port, port->read_status_mask); 1158 1159 if (psc_ops->clock) 1160 psc_ops->clock(port, 0); 1161 1162 /* Disable interrupt */ 1163 psc_ops->cw_disable_ints(port); 1164 1165 /* Release interrupt */ 1166 free_irq(port->irq, port); 1167} 1168 1169static void 1170mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, 1171 struct ktermios *old) 1172{ 1173 unsigned long flags; 1174 unsigned char mr1, mr2; 1175 unsigned int j; 1176 unsigned int baud; 1177 1178 /* Prepare what we're gonna write */ 1179 mr1 = 0; 1180 1181 switch (new->c_cflag & CSIZE) { 1182 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; 1183 break; 1184 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; 1185 break; 1186 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; 1187 break; 1188 case CS8: 1189 default: mr1 |= MPC52xx_PSC_MODE_8_BITS; 1190 } 1191 1192 if (new->c_cflag & PARENB) { 1193 if (new->c_cflag & CMSPAR) 1194 mr1 |= MPC52xx_PSC_MODE_PARFORCE; 1195 1196 /* With CMSPAR, PARODD also means high parity (same as termios) */ 1197 mr1 |= (new->c_cflag & PARODD) ? 1198 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 1199 } else { 1200 mr1 |= MPC52xx_PSC_MODE_PARNONE; 1201 } 1202 1203 mr2 = 0; 1204 1205 if (new->c_cflag & CSTOPB) 1206 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; 1207 else 1208 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? 1209 MPC52xx_PSC_MODE_ONE_STOP_5_BITS : 1210 MPC52xx_PSC_MODE_ONE_STOP; 1211 1212 if (new->c_cflag & CRTSCTS) { 1213 mr1 |= MPC52xx_PSC_MODE_RXRTS; 1214 mr2 |= MPC52xx_PSC_MODE_TXCTS; 1215 } 1216 1217 /* Get the lock */ 1218 spin_lock_irqsave(&port->lock, flags); 1219 1220 /* Do our best to flush TX & RX, so we don't lose anything */ 1221 /* But we don't wait indefinitely ! */ 1222 j = 5000000; /* Maximum wait */ 1223 /* FIXME Can't receive chars since set_termios might be called at early 1224 * boot for the console, all stuff is not yet ready to receive at that 1225 * time and that just makes the kernel oops */ 1226 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ 1227 while (!mpc52xx_uart_tx_empty(port) && --j) 1228 udelay(1); 1229 1230 if (!j) 1231 printk(KERN_ERR "mpc52xx_uart.c: " 1232 "Unable to flush RX & TX fifos in-time in set_termios." 1233 "Some chars may have been lost.\n"); 1234 1235 /* Reset the TX & RX */ 1236 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1237 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1238 1239 /* Send new mode settings */ 1240 psc_ops->set_mode(port, mr1, mr2); 1241 baud = psc_ops->set_baudrate(port, new, old); 1242 1243 /* Update the per-port timeout */ 1244 uart_update_timeout(port, new->c_cflag, baud); 1245 1246 if (UART_ENABLE_MS(port, new->c_cflag)) 1247 mpc52xx_uart_enable_ms(port); 1248 1249 /* Reenable TX & RX */ 1250 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1251 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1252 1253 /* We're all set, release the lock */ 1254 spin_unlock_irqrestore(&port->lock, flags); 1255} 1256 1257static const char * 1258mpc52xx_uart_type(struct uart_port *port) 1259{ 1260 /* 1261 * We keep using PORT_MPC52xx for historic reasons although it applies 1262 * for MPC512x, too, but print "MPC5xxx" to not irritate users 1263 */ 1264 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; 1265} 1266 1267static void 1268mpc52xx_uart_release_port(struct uart_port *port) 1269{ 1270 if (psc_ops->clock_relse) 1271 psc_ops->clock_relse(port); 1272 1273 /* remapped by us ? */ 1274 if (port->flags & UPF_IOREMAP) { 1275 iounmap(port->membase); 1276 port->membase = NULL; 1277 } 1278 1279 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1280} 1281 1282static int 1283mpc52xx_uart_request_port(struct uart_port *port) 1284{ 1285 int err; 1286 1287 if (port->flags & UPF_IOREMAP) /* Need to remap ? */ 1288 port->membase = ioremap(port->mapbase, 1289 sizeof(struct mpc52xx_psc)); 1290 1291 if (!port->membase) 1292 return -EINVAL; 1293 1294 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), 1295 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; 1296 1297 if (err) 1298 goto out_membase; 1299 1300 if (psc_ops->clock_alloc) { 1301 err = psc_ops->clock_alloc(port); 1302 if (err) 1303 goto out_mapregion; 1304 } 1305 1306 return 0; 1307 1308out_mapregion: 1309 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1310out_membase: 1311 if (port->flags & UPF_IOREMAP) { 1312 iounmap(port->membase); 1313 port->membase = NULL; 1314 } 1315 return err; 1316} 1317 1318static void 1319mpc52xx_uart_config_port(struct uart_port *port, int flags) 1320{ 1321 if ((flags & UART_CONFIG_TYPE) 1322 && (mpc52xx_uart_request_port(port) == 0)) 1323 port->type = PORT_MPC52xx; 1324} 1325 1326static int 1327mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1328{ 1329 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) 1330 return -EINVAL; 1331 1332 if ((ser->irq != port->irq) || 1333 (ser->io_type != UPIO_MEM) || 1334 (ser->baud_base != port->uartclk) || 1335 (ser->iomem_base != (void *)port->mapbase) || 1336 (ser->hub6 != 0)) 1337 return -EINVAL; 1338 1339 return 0; 1340} 1341 1342 1343static const struct uart_ops mpc52xx_uart_ops = { 1344 .tx_empty = mpc52xx_uart_tx_empty, 1345 .set_mctrl = mpc52xx_uart_set_mctrl, 1346 .get_mctrl = mpc52xx_uart_get_mctrl, 1347 .stop_tx = mpc52xx_uart_stop_tx, 1348 .start_tx = mpc52xx_uart_start_tx, 1349 .stop_rx = mpc52xx_uart_stop_rx, 1350 .enable_ms = mpc52xx_uart_enable_ms, 1351 .break_ctl = mpc52xx_uart_break_ctl, 1352 .startup = mpc52xx_uart_startup, 1353 .shutdown = mpc52xx_uart_shutdown, 1354 .set_termios = mpc52xx_uart_set_termios, 1355/* .pm = mpc52xx_uart_pm, Not supported yet */ 1356 .type = mpc52xx_uart_type, 1357 .release_port = mpc52xx_uart_release_port, 1358 .request_port = mpc52xx_uart_request_port, 1359 .config_port = mpc52xx_uart_config_port, 1360 .verify_port = mpc52xx_uart_verify_port 1361}; 1362 1363 1364/* ======================================================================== */ 1365/* Interrupt handling */ 1366/* ======================================================================== */ 1367 1368static inline int 1369mpc52xx_uart_int_rx_chars(struct uart_port *port) 1370{ 1371 struct tty_port *tport = &port->state->port; 1372 unsigned char ch, flag; 1373 unsigned short status; 1374 1375 /* While we can read, do so ! */ 1376 while (psc_ops->raw_rx_rdy(port)) { 1377 /* Get the char */ 1378 ch = psc_ops->read_char(port); 1379 1380 /* Handle sysreq char */ 1381 if (uart_handle_sysrq_char(port, ch)) 1382 continue; 1383 1384 /* Store it */ 1385 1386 flag = TTY_NORMAL; 1387 port->icount.rx++; 1388 1389 status = psc_ops->get_status(port); 1390 1391 if (status & (MPC52xx_PSC_SR_PE | 1392 MPC52xx_PSC_SR_FE | 1393 MPC52xx_PSC_SR_RB)) { 1394 1395 if (status & MPC52xx_PSC_SR_RB) { 1396 flag = TTY_BREAK; 1397 uart_handle_break(port); 1398 port->icount.brk++; 1399 } else if (status & MPC52xx_PSC_SR_PE) { 1400 flag = TTY_PARITY; 1401 port->icount.parity++; 1402 } 1403 else if (status & MPC52xx_PSC_SR_FE) { 1404 flag = TTY_FRAME; 1405 port->icount.frame++; 1406 } 1407 1408 /* Clear error condition */ 1409 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); 1410 1411 } 1412 tty_insert_flip_char(tport, ch, flag); 1413 if (status & MPC52xx_PSC_SR_OE) { 1414 /* 1415 * Overrun is special, since it's 1416 * reported immediately, and doesn't 1417 * affect the current character 1418 */ 1419 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1420 port->icount.overrun++; 1421 } 1422 } 1423 1424 spin_unlock(&port->lock); 1425 tty_flip_buffer_push(tport); 1426 spin_lock(&port->lock); 1427 1428 return psc_ops->raw_rx_rdy(port); 1429} 1430 1431static inline int 1432mpc52xx_uart_int_tx_chars(struct uart_port *port) 1433{ 1434 struct circ_buf *xmit = &port->state->xmit; 1435 1436 /* Process out of band chars */ 1437 if (port->x_char) { 1438 psc_ops->write_char(port, port->x_char); 1439 port->icount.tx++; 1440 port->x_char = 0; 1441 return 1; 1442 } 1443 1444 /* Nothing to do ? */ 1445 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 1446 mpc52xx_uart_stop_tx(port); 1447 return 0; 1448 } 1449 1450 /* Send chars */ 1451 while (psc_ops->raw_tx_rdy(port)) { 1452 psc_ops->write_char(port, xmit->buf[xmit->tail]); 1453 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1454 port->icount.tx++; 1455 if (uart_circ_empty(xmit)) 1456 break; 1457 } 1458 1459 /* Wake up */ 1460 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1461 uart_write_wakeup(port); 1462 1463 /* Maybe we're done after all */ 1464 if (uart_circ_empty(xmit)) { 1465 mpc52xx_uart_stop_tx(port); 1466 return 0; 1467 } 1468 1469 return 1; 1470} 1471 1472static irqreturn_t 1473mpc5xxx_uart_process_int(struct uart_port *port) 1474{ 1475 unsigned long pass = ISR_PASS_LIMIT; 1476 unsigned int keepgoing; 1477 u8 status; 1478 1479 /* While we have stuff to do, we continue */ 1480 do { 1481 /* If we don't find anything to do, we stop */ 1482 keepgoing = 0; 1483 1484 psc_ops->rx_clr_irq(port); 1485 if (psc_ops->rx_rdy(port)) 1486 keepgoing |= mpc52xx_uart_int_rx_chars(port); 1487 1488 psc_ops->tx_clr_irq(port); 1489 if (psc_ops->tx_rdy(port)) 1490 keepgoing |= mpc52xx_uart_int_tx_chars(port); 1491 1492 status = psc_ops->get_ipcr(port); 1493 if (status & MPC52xx_PSC_D_DCD) 1494 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); 1495 1496 if (status & MPC52xx_PSC_D_CTS) 1497 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); 1498 1499 /* Limit number of iteration */ 1500 if (!(--pass)) 1501 keepgoing = 0; 1502 1503 } while (keepgoing); 1504 1505 return IRQ_HANDLED; 1506} 1507 1508static irqreturn_t 1509mpc52xx_uart_int(int irq, void *dev_id) 1510{ 1511 struct uart_port *port = dev_id; 1512 irqreturn_t ret; 1513 1514 spin_lock(&port->lock); 1515 1516 ret = psc_ops->handle_irq(port); 1517 1518 spin_unlock(&port->lock); 1519 1520 return ret; 1521} 1522 1523/* ======================================================================== */ 1524/* Console ( if applicable ) */ 1525/* ======================================================================== */ 1526 1527#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE 1528 1529static void __init 1530mpc52xx_console_get_options(struct uart_port *port, 1531 int *baud, int *parity, int *bits, int *flow) 1532{ 1533 unsigned char mr1; 1534 1535 pr_debug("mpc52xx_console_get_options(port=%p)\n", port); 1536 1537 /* Read the mode registers */ 1538 mr1 = psc_ops->get_mr1(port); 1539 1540 /* CT{U,L}R are write-only ! */ 1541 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1542 1543 /* Parse them */ 1544 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { 1545 case MPC52xx_PSC_MODE_5_BITS: 1546 *bits = 5; 1547 break; 1548 case MPC52xx_PSC_MODE_6_BITS: 1549 *bits = 6; 1550 break; 1551 case MPC52xx_PSC_MODE_7_BITS: 1552 *bits = 7; 1553 break; 1554 case MPC52xx_PSC_MODE_8_BITS: 1555 default: 1556 *bits = 8; 1557 } 1558 1559 if (mr1 & MPC52xx_PSC_MODE_PARNONE) 1560 *parity = 'n'; 1561 else 1562 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; 1563} 1564 1565static void 1566mpc52xx_console_write(struct console *co, const char *s, unsigned int count) 1567{ 1568 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1569 unsigned int i, j; 1570 1571 /* Disable interrupts */ 1572 psc_ops->cw_disable_ints(port); 1573 1574 /* Wait the TX buffer to be empty */ 1575 j = 5000000; /* Maximum wait */ 1576 while (!mpc52xx_uart_tx_empty(port) && --j) 1577 udelay(1); 1578 1579 /* Write all the chars */ 1580 for (i = 0; i < count; i++, s++) { 1581 /* Line return handling */ 1582 if (*s == '\n') 1583 psc_ops->write_char(port, '\r'); 1584 1585 /* Send the char */ 1586 psc_ops->write_char(port, *s); 1587 1588 /* Wait the TX buffer to be empty */ 1589 j = 20000; /* Maximum wait */ 1590 while (!mpc52xx_uart_tx_empty(port) && --j) 1591 udelay(1); 1592 } 1593 1594 /* Restore interrupt state */ 1595 psc_ops->cw_restore_ints(port); 1596} 1597 1598 1599static int __init 1600mpc52xx_console_setup(struct console *co, char *options) 1601{ 1602 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1603 struct device_node *np = mpc52xx_uart_nodes[co->index]; 1604 unsigned int uartclk; 1605 struct resource res; 1606 int ret; 1607 1608 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1609 int bits = 8; 1610 int parity = 'n'; 1611 int flow = 'n'; 1612 1613 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", 1614 co, co->index, options); 1615 1616 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { 1617 pr_debug("PSC%x out of range\n", co->index); 1618 return -EINVAL; 1619 } 1620 1621 if (!np) { 1622 pr_debug("PSC%x not found in device tree\n", co->index); 1623 return -EINVAL; 1624 } 1625 1626 pr_debug("Console on ttyPSC%x is %pOF\n", 1627 co->index, mpc52xx_uart_nodes[co->index]); 1628 1629 /* Fetch register locations */ 1630 ret = of_address_to_resource(np, 0, &res); 1631 if (ret) { 1632 pr_debug("Could not get resources for PSC%x\n", co->index); 1633 return ret; 1634 } 1635 1636 uartclk = mpc5xxx_get_bus_frequency(np); 1637 if (uartclk == 0) { 1638 pr_debug("Could not find uart clock frequency!\n"); 1639 return -EINVAL; 1640 } 1641 1642 /* Basic port init. Needed since we use some uart_??? func before 1643 * real init for early access */ 1644 spin_lock_init(&port->lock); 1645 port->uartclk = uartclk; 1646 port->ops = &mpc52xx_uart_ops; 1647 port->mapbase = res.start; 1648 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); 1649 port->irq = irq_of_parse_and_map(np, 0); 1650 1651 if (port->membase == NULL) 1652 return -EINVAL; 1653 1654 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", 1655 (void *)port->mapbase, port->membase, 1656 port->irq, port->uartclk); 1657 1658 /* Setup the port parameters accoding to options */ 1659 if (options) 1660 uart_parse_options(options, &baud, &parity, &bits, &flow); 1661 else 1662 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); 1663 1664 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", 1665 baud, bits, parity, flow); 1666 1667 return uart_set_options(port, co, baud, parity, bits, flow); 1668} 1669 1670 1671static struct uart_driver mpc52xx_uart_driver; 1672 1673static struct console mpc52xx_console = { 1674 .name = "ttyPSC", 1675 .write = mpc52xx_console_write, 1676 .device = uart_console_device, 1677 .setup = mpc52xx_console_setup, 1678 .flags = CON_PRINTBUFFER, 1679 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ 1680 .data = &mpc52xx_uart_driver, 1681}; 1682 1683 1684static int __init 1685mpc52xx_console_init(void) 1686{ 1687 mpc52xx_uart_of_enumerate(); 1688 register_console(&mpc52xx_console); 1689 return 0; 1690} 1691 1692console_initcall(mpc52xx_console_init); 1693 1694#define MPC52xx_PSC_CONSOLE &mpc52xx_console 1695#else 1696#define MPC52xx_PSC_CONSOLE NULL 1697#endif 1698 1699 1700/* ======================================================================== */ 1701/* UART Driver */ 1702/* ======================================================================== */ 1703 1704static struct uart_driver mpc52xx_uart_driver = { 1705 .driver_name = "mpc52xx_psc_uart", 1706 .dev_name = "ttyPSC", 1707 .major = SERIAL_PSC_MAJOR, 1708 .minor = SERIAL_PSC_MINOR, 1709 .nr = MPC52xx_PSC_MAXNUM, 1710 .cons = MPC52xx_PSC_CONSOLE, 1711}; 1712 1713/* ======================================================================== */ 1714/* OF Platform Driver */ 1715/* ======================================================================== */ 1716 1717static const struct of_device_id mpc52xx_uart_of_match[] = { 1718#ifdef CONFIG_PPC_MPC52xx 1719 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, 1720 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1721 /* binding used by old lite5200 device trees: */ 1722 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1723 /* binding used by efika: */ 1724 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, 1725#endif 1726#ifdef CONFIG_PPC_MPC512x 1727 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, 1728 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, }, 1729#endif 1730 {}, 1731}; 1732 1733static int mpc52xx_uart_of_probe(struct platform_device *op) 1734{ 1735 int idx = -1; 1736 unsigned int uartclk; 1737 struct uart_port *port = NULL; 1738 struct resource res; 1739 int ret; 1740 1741 /* Check validity & presence */ 1742 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) 1743 if (mpc52xx_uart_nodes[idx] == op->dev.of_node) 1744 break; 1745 if (idx >= MPC52xx_PSC_MAXNUM) 1746 return -EINVAL; 1747 pr_debug("Found %pOF assigned to ttyPSC%x\n", 1748 mpc52xx_uart_nodes[idx], idx); 1749 1750 /* set the uart clock to the input clock of the psc, the different 1751 * prescalers are taken into account in the set_baudrate() methods 1752 * of the respective chip */ 1753 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); 1754 if (uartclk == 0) { 1755 dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); 1756 return -EINVAL; 1757 } 1758 1759 /* Init the port structure */ 1760 port = &mpc52xx_uart_ports[idx]; 1761 1762 spin_lock_init(&port->lock); 1763 port->uartclk = uartclk; 1764 port->fifosize = 512; 1765 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE); 1766 port->iotype = UPIO_MEM; 1767 port->flags = UPF_BOOT_AUTOCONF | 1768 (uart_console(port) ? 0 : UPF_IOREMAP); 1769 port->line = idx; 1770 port->ops = &mpc52xx_uart_ops; 1771 port->dev = &op->dev; 1772 1773 /* Search for IRQ and mapbase */ 1774 ret = of_address_to_resource(op->dev.of_node, 0, &res); 1775 if (ret) 1776 return ret; 1777 1778 port->mapbase = res.start; 1779 if (!port->mapbase) { 1780 dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); 1781 return -EINVAL; 1782 } 1783 1784 psc_ops->get_irq(port, op->dev.of_node); 1785 if (port->irq == 0) { 1786 dev_dbg(&op->dev, "Could not get irq\n"); 1787 return -EINVAL; 1788 } 1789 1790 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", 1791 (void *)port->mapbase, port->irq, port->uartclk); 1792 1793 /* Add the port to the uart sub-system */ 1794 ret = uart_add_one_port(&mpc52xx_uart_driver, port); 1795 if (ret) 1796 return ret; 1797 1798 platform_set_drvdata(op, (void *)port); 1799 return 0; 1800} 1801 1802static int 1803mpc52xx_uart_of_remove(struct platform_device *op) 1804{ 1805 struct uart_port *port = platform_get_drvdata(op); 1806 1807 if (port) 1808 uart_remove_one_port(&mpc52xx_uart_driver, port); 1809 1810 return 0; 1811} 1812 1813#ifdef CONFIG_PM 1814static int 1815mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) 1816{ 1817 struct uart_port *port = platform_get_drvdata(op); 1818 1819 if (port) 1820 uart_suspend_port(&mpc52xx_uart_driver, port); 1821 1822 return 0; 1823} 1824 1825static int 1826mpc52xx_uart_of_resume(struct platform_device *op) 1827{ 1828 struct uart_port *port = platform_get_drvdata(op); 1829 1830 if (port) 1831 uart_resume_port(&mpc52xx_uart_driver, port); 1832 1833 return 0; 1834} 1835#endif 1836 1837static void 1838mpc52xx_uart_of_assign(struct device_node *np) 1839{ 1840 int i; 1841 1842 /* Find the first free PSC number */ 1843 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1844 if (mpc52xx_uart_nodes[i] == NULL) { 1845 of_node_get(np); 1846 mpc52xx_uart_nodes[i] = np; 1847 return; 1848 } 1849 } 1850} 1851 1852static void 1853mpc52xx_uart_of_enumerate(void) 1854{ 1855 static int enum_done; 1856 struct device_node *np; 1857 const struct of_device_id *match; 1858 int i; 1859 1860 if (enum_done) 1861 return; 1862 1863 /* Assign index to each PSC in device tree */ 1864 for_each_matching_node(np, mpc52xx_uart_of_match) { 1865 match = of_match_node(mpc52xx_uart_of_match, np); 1866 psc_ops = match->data; 1867 mpc52xx_uart_of_assign(np); 1868 } 1869 1870 enum_done = 1; 1871 1872 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1873 if (mpc52xx_uart_nodes[i]) 1874 pr_debug("%pOF assigned to ttyPSC%x\n", 1875 mpc52xx_uart_nodes[i], i); 1876 } 1877} 1878 1879MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); 1880 1881static struct platform_driver mpc52xx_uart_of_driver = { 1882 .probe = mpc52xx_uart_of_probe, 1883 .remove = mpc52xx_uart_of_remove, 1884#ifdef CONFIG_PM 1885 .suspend = mpc52xx_uart_of_suspend, 1886 .resume = mpc52xx_uart_of_resume, 1887#endif 1888 .driver = { 1889 .name = "mpc52xx-psc-uart", 1890 .of_match_table = mpc52xx_uart_of_match, 1891 }, 1892}; 1893 1894 1895/* ======================================================================== */ 1896/* Module */ 1897/* ======================================================================== */ 1898 1899static int __init 1900mpc52xx_uart_init(void) 1901{ 1902 int ret; 1903 1904 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); 1905 1906 ret = uart_register_driver(&mpc52xx_uart_driver); 1907 if (ret) { 1908 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", 1909 __FILE__, ret); 1910 return ret; 1911 } 1912 1913 mpc52xx_uart_of_enumerate(); 1914 1915 /* 1916 * Map the PSC FIFO Controller and init if on MPC512x. 1917 */ 1918 if (psc_ops && psc_ops->fifoc_init) { 1919 ret = psc_ops->fifoc_init(); 1920 if (ret) 1921 goto err_init; 1922 } 1923 1924 ret = platform_driver_register(&mpc52xx_uart_of_driver); 1925 if (ret) { 1926 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", 1927 __FILE__, ret); 1928 goto err_reg; 1929 } 1930 1931 return 0; 1932err_reg: 1933 if (psc_ops && psc_ops->fifoc_uninit) 1934 psc_ops->fifoc_uninit(); 1935err_init: 1936 uart_unregister_driver(&mpc52xx_uart_driver); 1937 return ret; 1938} 1939 1940static void __exit 1941mpc52xx_uart_exit(void) 1942{ 1943 if (psc_ops->fifoc_uninit) 1944 psc_ops->fifoc_uninit(); 1945 1946 platform_driver_unregister(&mpc52xx_uart_of_driver); 1947 uart_unregister_driver(&mpc52xx_uart_driver); 1948} 1949 1950 1951module_init(mpc52xx_uart_init); 1952module_exit(mpc52xx_uart_exit); 1953 1954MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 1955MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); 1956MODULE_LICENSE("GPL"); 1957