1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Based on meson_uart.c, by AMLOGIC, INC. 4 * 5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org> 6 */ 7 8#include <linux/clk.h> 9#include <linux/console.h> 10#include <linux/delay.h> 11#include <linux/init.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/serial.h> 19#include <linux/serial_core.h> 20#include <linux/tty.h> 21#include <linux/tty_flip.h> 22 23/* Register offsets */ 24#define AML_UART_WFIFO 0x00 25#define AML_UART_RFIFO 0x04 26#define AML_UART_CONTROL 0x08 27#define AML_UART_STATUS 0x0c 28#define AML_UART_MISC 0x10 29#define AML_UART_REG5 0x14 30 31/* AML_UART_CONTROL bits */ 32#define AML_UART_TX_EN BIT(12) 33#define AML_UART_RX_EN BIT(13) 34#define AML_UART_TWO_WIRE_EN BIT(15) 35#define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) 36#define AML_UART_STOP_BIT_1SB (0x00 << 16) 37#define AML_UART_STOP_BIT_2SB (0x01 << 16) 38#define AML_UART_PARITY_TYPE BIT(18) 39#define AML_UART_PARITY_EN BIT(19) 40#define AML_UART_TX_RST BIT(22) 41#define AML_UART_RX_RST BIT(23) 42#define AML_UART_CLEAR_ERR BIT(24) 43#define AML_UART_RX_INT_EN BIT(27) 44#define AML_UART_TX_INT_EN BIT(28) 45#define AML_UART_DATA_LEN_MASK (0x03 << 20) 46#define AML_UART_DATA_LEN_8BIT (0x00 << 20) 47#define AML_UART_DATA_LEN_7BIT (0x01 << 20) 48#define AML_UART_DATA_LEN_6BIT (0x02 << 20) 49#define AML_UART_DATA_LEN_5BIT (0x03 << 20) 50 51/* AML_UART_STATUS bits */ 52#define AML_UART_PARITY_ERR BIT(16) 53#define AML_UART_FRAME_ERR BIT(17) 54#define AML_UART_TX_FIFO_WERR BIT(18) 55#define AML_UART_RX_EMPTY BIT(20) 56#define AML_UART_TX_FULL BIT(21) 57#define AML_UART_TX_EMPTY BIT(22) 58#define AML_UART_XMIT_BUSY BIT(25) 59#define AML_UART_ERR (AML_UART_PARITY_ERR | \ 60 AML_UART_FRAME_ERR | \ 61 AML_UART_TX_FIFO_WERR) 62 63/* AML_UART_MISC bits */ 64#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) 65#define AML_UART_RECV_IRQ(c) ((c) & 0xff) 66 67/* AML_UART_REG5 bits */ 68#define AML_UART_BAUD_MASK 0x7fffff 69#define AML_UART_BAUD_USE BIT(23) 70#define AML_UART_BAUD_XTAL BIT(24) 71 72#define AML_UART_PORT_NUM 12 73#define AML_UART_PORT_OFFSET 6 74#define AML_UART_DEV_NAME "ttyAML" 75 76#define AML_UART_POLL_USEC 5 77#define AML_UART_TIMEOUT_USEC 10000 78 79static struct uart_driver meson_uart_driver; 80 81static struct uart_port *meson_ports[AML_UART_PORT_NUM]; 82 83static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 84{ 85} 86 87static unsigned int meson_uart_get_mctrl(struct uart_port *port) 88{ 89 return TIOCM_CTS; 90} 91 92static unsigned int meson_uart_tx_empty(struct uart_port *port) 93{ 94 u32 val; 95 96 val = readl(port->membase + AML_UART_STATUS); 97 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); 98 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; 99} 100 101static void meson_uart_stop_tx(struct uart_port *port) 102{ 103 u32 val; 104 105 val = readl(port->membase + AML_UART_CONTROL); 106 val &= ~AML_UART_TX_INT_EN; 107 writel(val, port->membase + AML_UART_CONTROL); 108} 109 110static void meson_uart_stop_rx(struct uart_port *port) 111{ 112 u32 val; 113 114 val = readl(port->membase + AML_UART_CONTROL); 115 val &= ~AML_UART_RX_EN; 116 writel(val, port->membase + AML_UART_CONTROL); 117} 118 119static void meson_uart_shutdown(struct uart_port *port) 120{ 121 unsigned long flags; 122 u32 val; 123 124 free_irq(port->irq, port); 125 126 spin_lock_irqsave(&port->lock, flags); 127 128 val = readl(port->membase + AML_UART_CONTROL); 129 val &= ~AML_UART_RX_EN; 130 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 131 writel(val, port->membase + AML_UART_CONTROL); 132 133 spin_unlock_irqrestore(&port->lock, flags); 134} 135 136static void meson_uart_start_tx(struct uart_port *port) 137{ 138 struct circ_buf *xmit = &port->state->xmit; 139 unsigned int ch; 140 u32 val; 141 142 if (uart_tx_stopped(port)) { 143 meson_uart_stop_tx(port); 144 return; 145 } 146 147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 148 if (port->x_char) { 149 writel(port->x_char, port->membase + AML_UART_WFIFO); 150 port->icount.tx++; 151 port->x_char = 0; 152 continue; 153 } 154 155 if (uart_circ_empty(xmit)) 156 break; 157 158 ch = xmit->buf[xmit->tail]; 159 writel(ch, port->membase + AML_UART_WFIFO); 160 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1); 161 port->icount.tx++; 162 } 163 164 if (!uart_circ_empty(xmit)) { 165 val = readl(port->membase + AML_UART_CONTROL); 166 val |= AML_UART_TX_INT_EN; 167 writel(val, port->membase + AML_UART_CONTROL); 168 } 169 170 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 171 uart_write_wakeup(port); 172} 173 174static void meson_receive_chars(struct uart_port *port) 175{ 176 struct tty_port *tport = &port->state->port; 177 char flag; 178 u32 ostatus, status, ch, mode; 179 180 do { 181 flag = TTY_NORMAL; 182 port->icount.rx++; 183 ostatus = status = readl(port->membase + AML_UART_STATUS); 184 185 if (status & AML_UART_ERR) { 186 if (status & AML_UART_TX_FIFO_WERR) 187 port->icount.overrun++; 188 else if (status & AML_UART_FRAME_ERR) 189 port->icount.frame++; 190 else if (status & AML_UART_PARITY_ERR) 191 port->icount.frame++; 192 193 mode = readl(port->membase + AML_UART_CONTROL); 194 mode |= AML_UART_CLEAR_ERR; 195 writel(mode, port->membase + AML_UART_CONTROL); 196 197 /* It doesn't clear to 0 automatically */ 198 mode &= ~AML_UART_CLEAR_ERR; 199 writel(mode, port->membase + AML_UART_CONTROL); 200 201 status &= port->read_status_mask; 202 if (status & AML_UART_FRAME_ERR) 203 flag = TTY_FRAME; 204 else if (status & AML_UART_PARITY_ERR) 205 flag = TTY_PARITY; 206 } 207 208 ch = readl(port->membase + AML_UART_RFIFO); 209 ch &= 0xff; 210 211 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { 212 port->icount.brk++; 213 flag = TTY_BREAK; 214 if (uart_handle_break(port)) 215 continue; 216 } 217 218 if (uart_handle_sysrq_char(port, ch)) 219 continue; 220 221 if ((status & port->ignore_status_mask) == 0) 222 tty_insert_flip_char(tport, ch, flag); 223 224 if (status & AML_UART_TX_FIFO_WERR) 225 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 226 227 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); 228 229 spin_unlock(&port->lock); 230 tty_flip_buffer_push(tport); 231 spin_lock(&port->lock); 232} 233 234static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) 235{ 236 struct uart_port *port = (struct uart_port *)dev_id; 237 238 spin_lock(&port->lock); 239 240 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 241 meson_receive_chars(port); 242 243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 244 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) 245 meson_uart_start_tx(port); 246 } 247 248 spin_unlock(&port->lock); 249 250 return IRQ_HANDLED; 251} 252 253static const char *meson_uart_type(struct uart_port *port) 254{ 255 return (port->type == PORT_MESON) ? "meson_uart" : NULL; 256} 257 258/* 259 * This function is called only from probe() using a temporary io mapping 260 * in order to perform a reset before setting up the device. Since the 261 * temporarily mapped region was successfully requested, there can be no 262 * console on this port at this time. Hence it is not necessary for this 263 * function to acquire the port->lock. (Since there is no console on this 264 * port at this time, the port->lock is not initialized yet.) 265 */ 266static void meson_uart_reset(struct uart_port *port) 267{ 268 u32 val; 269 270 val = readl(port->membase + AML_UART_CONTROL); 271 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 272 writel(val, port->membase + AML_UART_CONTROL); 273 274 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 275 writel(val, port->membase + AML_UART_CONTROL); 276} 277 278static int meson_uart_startup(struct uart_port *port) 279{ 280 unsigned long flags; 281 u32 val; 282 int ret = 0; 283 284 spin_lock_irqsave(&port->lock, flags); 285 286 val = readl(port->membase + AML_UART_CONTROL); 287 val |= AML_UART_CLEAR_ERR; 288 writel(val, port->membase + AML_UART_CONTROL); 289 val &= ~AML_UART_CLEAR_ERR; 290 writel(val, port->membase + AML_UART_CONTROL); 291 292 val |= (AML_UART_RX_EN | AML_UART_TX_EN); 293 writel(val, port->membase + AML_UART_CONTROL); 294 295 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 296 writel(val, port->membase + AML_UART_CONTROL); 297 298 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 299 writel(val, port->membase + AML_UART_MISC); 300 301 spin_unlock_irqrestore(&port->lock, flags); 302 303 ret = request_irq(port->irq, meson_uart_interrupt, 0, 304 port->name, port); 305 306 return ret; 307} 308 309static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) 310{ 311 u32 val; 312 313 while (!meson_uart_tx_empty(port)) 314 cpu_relax(); 315 316 if (port->uartclk == 24000000) { 317 val = ((port->uartclk / 3) / baud) - 1; 318 val |= AML_UART_BAUD_XTAL; 319 } else { 320 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; 321 } 322 val |= AML_UART_BAUD_USE; 323 writel(val, port->membase + AML_UART_REG5); 324} 325 326static void meson_uart_set_termios(struct uart_port *port, 327 struct ktermios *termios, 328 struct ktermios *old) 329{ 330 unsigned int cflags, iflags, baud; 331 unsigned long flags; 332 u32 val; 333 334 spin_lock_irqsave(&port->lock, flags); 335 336 cflags = termios->c_cflag; 337 iflags = termios->c_iflag; 338 339 val = readl(port->membase + AML_UART_CONTROL); 340 341 val &= ~AML_UART_DATA_LEN_MASK; 342 switch (cflags & CSIZE) { 343 case CS8: 344 val |= AML_UART_DATA_LEN_8BIT; 345 break; 346 case CS7: 347 val |= AML_UART_DATA_LEN_7BIT; 348 break; 349 case CS6: 350 val |= AML_UART_DATA_LEN_6BIT; 351 break; 352 case CS5: 353 val |= AML_UART_DATA_LEN_5BIT; 354 break; 355 } 356 357 if (cflags & PARENB) 358 val |= AML_UART_PARITY_EN; 359 else 360 val &= ~AML_UART_PARITY_EN; 361 362 if (cflags & PARODD) 363 val |= AML_UART_PARITY_TYPE; 364 else 365 val &= ~AML_UART_PARITY_TYPE; 366 367 val &= ~AML_UART_STOP_BIT_LEN_MASK; 368 if (cflags & CSTOPB) 369 val |= AML_UART_STOP_BIT_2SB; 370 else 371 val |= AML_UART_STOP_BIT_1SB; 372 373 if (cflags & CRTSCTS) { 374 if (port->flags & UPF_HARD_FLOW) 375 val &= ~AML_UART_TWO_WIRE_EN; 376 else 377 termios->c_cflag &= ~CRTSCTS; 378 } else { 379 val |= AML_UART_TWO_WIRE_EN; 380 } 381 382 writel(val, port->membase + AML_UART_CONTROL); 383 384 baud = uart_get_baud_rate(port, termios, old, 50, 4000000); 385 meson_uart_change_speed(port, baud); 386 387 port->read_status_mask = AML_UART_TX_FIFO_WERR; 388 if (iflags & INPCK) 389 port->read_status_mask |= AML_UART_PARITY_ERR | 390 AML_UART_FRAME_ERR; 391 392 port->ignore_status_mask = 0; 393 if (iflags & IGNPAR) 394 port->ignore_status_mask |= AML_UART_PARITY_ERR | 395 AML_UART_FRAME_ERR; 396 397 uart_update_timeout(port, termios->c_cflag, baud); 398 spin_unlock_irqrestore(&port->lock, flags); 399} 400 401static int meson_uart_verify_port(struct uart_port *port, 402 struct serial_struct *ser) 403{ 404 int ret = 0; 405 406 if (port->type != PORT_MESON) 407 ret = -EINVAL; 408 if (port->irq != ser->irq) 409 ret = -EINVAL; 410 if (ser->baud_base < 9600) 411 ret = -EINVAL; 412 return ret; 413} 414 415static void meson_uart_release_port(struct uart_port *port) 416{ 417 devm_iounmap(port->dev, port->membase); 418 port->membase = NULL; 419 devm_release_mem_region(port->dev, port->mapbase, port->mapsize); 420} 421 422static int meson_uart_request_port(struct uart_port *port) 423{ 424 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, 425 dev_name(port->dev))) { 426 dev_err(port->dev, "Memory region busy\n"); 427 return -EBUSY; 428 } 429 430 port->membase = devm_ioremap(port->dev, port->mapbase, 431 port->mapsize); 432 if (!port->membase) 433 return -ENOMEM; 434 435 return 0; 436} 437 438static void meson_uart_config_port(struct uart_port *port, int flags) 439{ 440 if (flags & UART_CONFIG_TYPE) { 441 port->type = PORT_MESON; 442 meson_uart_request_port(port); 443 } 444} 445 446#ifdef CONFIG_CONSOLE_POLL 447/* 448 * Console polling routines for writing and reading from the uart while 449 * in an interrupt or debug context (i.e. kgdb). 450 */ 451 452static int meson_uart_poll_get_char(struct uart_port *port) 453{ 454 u32 c; 455 unsigned long flags; 456 457 spin_lock_irqsave(&port->lock, flags); 458 459 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) 460 c = NO_POLL_CHAR; 461 else 462 c = readl(port->membase + AML_UART_RFIFO); 463 464 spin_unlock_irqrestore(&port->lock, flags); 465 466 return c; 467} 468 469static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c) 470{ 471 unsigned long flags; 472 u32 reg; 473 int ret; 474 475 spin_lock_irqsave(&port->lock, flags); 476 477 /* Wait until FIFO is empty or timeout */ 478 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 479 reg & AML_UART_TX_EMPTY, 480 AML_UART_POLL_USEC, 481 AML_UART_TIMEOUT_USEC); 482 if (ret == -ETIMEDOUT) { 483 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 484 goto out; 485 } 486 487 /* Write the character */ 488 writel(c, port->membase + AML_UART_WFIFO); 489 490 /* Wait until FIFO is empty or timeout */ 491 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 492 reg & AML_UART_TX_EMPTY, 493 AML_UART_POLL_USEC, 494 AML_UART_TIMEOUT_USEC); 495 if (ret == -ETIMEDOUT) 496 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 497 498out: 499 spin_unlock_irqrestore(&port->lock, flags); 500} 501 502#endif /* CONFIG_CONSOLE_POLL */ 503 504static const struct uart_ops meson_uart_ops = { 505 .set_mctrl = meson_uart_set_mctrl, 506 .get_mctrl = meson_uart_get_mctrl, 507 .tx_empty = meson_uart_tx_empty, 508 .start_tx = meson_uart_start_tx, 509 .stop_tx = meson_uart_stop_tx, 510 .stop_rx = meson_uart_stop_rx, 511 .startup = meson_uart_startup, 512 .shutdown = meson_uart_shutdown, 513 .set_termios = meson_uart_set_termios, 514 .type = meson_uart_type, 515 .config_port = meson_uart_config_port, 516 .request_port = meson_uart_request_port, 517 .release_port = meson_uart_release_port, 518 .verify_port = meson_uart_verify_port, 519#ifdef CONFIG_CONSOLE_POLL 520 .poll_get_char = meson_uart_poll_get_char, 521 .poll_put_char = meson_uart_poll_put_char, 522#endif 523}; 524 525#ifdef CONFIG_SERIAL_MESON_CONSOLE 526static void meson_uart_enable_tx_engine(struct uart_port *port) 527{ 528 u32 val; 529 530 val = readl(port->membase + AML_UART_CONTROL); 531 val |= AML_UART_TX_EN; 532 writel(val, port->membase + AML_UART_CONTROL); 533} 534 535static void meson_console_putchar(struct uart_port *port, int ch) 536{ 537 if (!port->membase) 538 return; 539 540 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) 541 cpu_relax(); 542 writel(ch, port->membase + AML_UART_WFIFO); 543} 544 545static void meson_serial_port_write(struct uart_port *port, const char *s, 546 u_int count) 547{ 548 unsigned long flags; 549 int locked; 550 u32 val, tmp; 551 552 local_irq_save(flags); 553 if (port->sysrq) { 554 locked = 0; 555 } else if (oops_in_progress) { 556 locked = spin_trylock(&port->lock); 557 } else { 558 spin_lock(&port->lock); 559 locked = 1; 560 } 561 562 val = readl(port->membase + AML_UART_CONTROL); 563 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); 564 writel(tmp, port->membase + AML_UART_CONTROL); 565 566 uart_console_write(port, s, count, meson_console_putchar); 567 writel(val, port->membase + AML_UART_CONTROL); 568 569 if (locked) 570 spin_unlock(&port->lock); 571 local_irq_restore(flags); 572} 573 574static void meson_serial_console_write(struct console *co, const char *s, 575 u_int count) 576{ 577 struct uart_port *port; 578 579 port = meson_ports[co->index]; 580 if (!port) 581 return; 582 583 meson_serial_port_write(port, s, count); 584} 585 586static int meson_serial_console_setup(struct console *co, char *options) 587{ 588 struct uart_port *port; 589 int baud = 115200; 590 int bits = 8; 591 int parity = 'n'; 592 int flow = 'n'; 593 594 if (co->index < 0 || co->index >= AML_UART_PORT_NUM) 595 return -EINVAL; 596 597 port = meson_ports[co->index]; 598 if (!port || !port->membase) 599 return -ENODEV; 600 601 meson_uart_enable_tx_engine(port); 602 603 if (options) 604 uart_parse_options(options, &baud, &parity, &bits, &flow); 605 606 return uart_set_options(port, co, baud, parity, bits, flow); 607} 608 609static struct console meson_serial_console = { 610 .name = AML_UART_DEV_NAME, 611 .write = meson_serial_console_write, 612 .device = uart_console_device, 613 .setup = meson_serial_console_setup, 614 .flags = CON_PRINTBUFFER, 615 .index = -1, 616 .data = &meson_uart_driver, 617}; 618 619static int __init meson_serial_console_init(void) 620{ 621 register_console(&meson_serial_console); 622 return 0; 623} 624console_initcall(meson_serial_console_init); 625 626static void meson_serial_early_console_write(struct console *co, 627 const char *s, 628 u_int count) 629{ 630 struct earlycon_device *dev = co->data; 631 632 meson_serial_port_write(&dev->port, s, count); 633} 634 635static int __init 636meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) 637{ 638 if (!device->port.membase) 639 return -ENODEV; 640 641 meson_uart_enable_tx_engine(&device->port); 642 device->con->write = meson_serial_early_console_write; 643 return 0; 644} 645/* Legacy bindings, should be removed when no more used */ 646OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart", 647 meson_serial_early_console_setup); 648/* Stable bindings */ 649OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", 650 meson_serial_early_console_setup); 651 652#define MESON_SERIAL_CONSOLE (&meson_serial_console) 653#else 654#define MESON_SERIAL_CONSOLE NULL 655#endif 656 657static struct uart_driver meson_uart_driver = { 658 .owner = THIS_MODULE, 659 .driver_name = "meson_uart", 660 .dev_name = AML_UART_DEV_NAME, 661 .nr = AML_UART_PORT_NUM, 662 .cons = MESON_SERIAL_CONSOLE, 663}; 664 665static inline struct clk *meson_uart_probe_clock(struct device *dev, 666 const char *id) 667{ 668 struct clk *clk = NULL; 669 int ret; 670 671 clk = devm_clk_get(dev, id); 672 if (IS_ERR(clk)) 673 return clk; 674 675 ret = clk_prepare_enable(clk); 676 if (ret) { 677 dev_err(dev, "couldn't enable clk\n"); 678 return ERR_PTR(ret); 679 } 680 681 devm_add_action_or_reset(dev, 682 (void(*)(void *))clk_disable_unprepare, 683 clk); 684 685 return clk; 686} 687 688/* 689 * This function gets clocks in the legacy non-stable DT bindings. 690 * This code will be remove once all the platforms switch to the 691 * new DT bindings. 692 */ 693static int meson_uart_probe_clocks_legacy(struct platform_device *pdev, 694 struct uart_port *port) 695{ 696 struct clk *clk = NULL; 697 698 clk = meson_uart_probe_clock(&pdev->dev, NULL); 699 if (IS_ERR(clk)) 700 return PTR_ERR(clk); 701 702 port->uartclk = clk_get_rate(clk); 703 704 return 0; 705} 706 707static int meson_uart_probe_clocks(struct platform_device *pdev, 708 struct uart_port *port) 709{ 710 struct clk *clk_xtal = NULL; 711 struct clk *clk_pclk = NULL; 712 struct clk *clk_baud = NULL; 713 714 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk"); 715 if (IS_ERR(clk_pclk)) 716 return PTR_ERR(clk_pclk); 717 718 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal"); 719 if (IS_ERR(clk_xtal)) 720 return PTR_ERR(clk_xtal); 721 722 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud"); 723 if (IS_ERR(clk_baud)) 724 return PTR_ERR(clk_baud); 725 726 port->uartclk = clk_get_rate(clk_baud); 727 728 return 0; 729} 730 731static int meson_uart_probe(struct platform_device *pdev) 732{ 733 struct resource *res_mem; 734 struct uart_port *port; 735 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ 736 int ret = 0; 737 int irq; 738 bool has_rtscts; 739 740 if (pdev->dev.of_node) 741 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 742 743 if (pdev->id < 0) { 744 int id; 745 746 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { 747 if (!meson_ports[id]) { 748 pdev->id = id; 749 break; 750 } 751 } 752 } 753 754 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) 755 return -EINVAL; 756 757 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 758 if (!res_mem) 759 return -ENODEV; 760 761 irq = platform_get_irq(pdev, 0); 762 if (irq < 0) 763 return irq; 764 765 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); 766 has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts"); 767 768 if (meson_ports[pdev->id]) { 769 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); 770 return -EBUSY; 771 } 772 773 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); 774 if (!port) 775 return -ENOMEM; 776 777 /* Use legacy way until all platforms switch to new bindings */ 778 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart")) 779 ret = meson_uart_probe_clocks_legacy(pdev, port); 780 else 781 ret = meson_uart_probe_clocks(pdev, port); 782 783 if (ret) 784 return ret; 785 786 port->iotype = UPIO_MEM; 787 port->mapbase = res_mem->start; 788 port->mapsize = resource_size(res_mem); 789 port->irq = irq; 790 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 791 if (has_rtscts) 792 port->flags |= UPF_HARD_FLOW; 793 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); 794 port->dev = &pdev->dev; 795 port->line = pdev->id; 796 port->type = PORT_MESON; 797 port->x_char = 0; 798 port->ops = &meson_uart_ops; 799 port->fifosize = fifosize; 800 801 meson_ports[pdev->id] = port; 802 platform_set_drvdata(pdev, port); 803 804 /* reset port before registering (and possibly registering console) */ 805 if (meson_uart_request_port(port) >= 0) { 806 meson_uart_reset(port); 807 meson_uart_release_port(port); 808 } 809 810 ret = uart_add_one_port(&meson_uart_driver, port); 811 if (ret) 812 meson_ports[pdev->id] = NULL; 813 814 return ret; 815} 816 817static int meson_uart_remove(struct platform_device *pdev) 818{ 819 struct uart_port *port; 820 821 port = platform_get_drvdata(pdev); 822 uart_remove_one_port(&meson_uart_driver, port); 823 meson_ports[pdev->id] = NULL; 824 825 return 0; 826} 827 828static const struct of_device_id meson_uart_dt_match[] = { 829 /* Legacy bindings, should be removed when no more used */ 830 { .compatible = "amlogic,meson-uart" }, 831 /* Stable bindings */ 832 { .compatible = "amlogic,meson6-uart" }, 833 { .compatible = "amlogic,meson8-uart" }, 834 { .compatible = "amlogic,meson8b-uart" }, 835 { .compatible = "amlogic,meson-gx-uart" }, 836 { /* sentinel */ }, 837}; 838MODULE_DEVICE_TABLE(of, meson_uart_dt_match); 839 840static struct platform_driver meson_uart_platform_driver = { 841 .probe = meson_uart_probe, 842 .remove = meson_uart_remove, 843 .driver = { 844 .name = "meson_uart", 845 .of_match_table = meson_uart_dt_match, 846 }, 847}; 848 849static int __init meson_uart_init(void) 850{ 851 int ret; 852 853 ret = uart_register_driver(&meson_uart_driver); 854 if (ret) 855 return ret; 856 857 ret = platform_driver_register(&meson_uart_platform_driver); 858 if (ret) 859 uart_unregister_driver(&meson_uart_driver); 860 861 return ret; 862} 863 864static void __exit meson_uart_exit(void) 865{ 866 platform_driver_unregister(&meson_uart_platform_driver); 867 uart_unregister_driver(&meson_uart_driver); 868} 869 870module_init(meson_uart_init); 871module_exit(meson_uart_exit); 872 873MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 874MODULE_DESCRIPTION("Amlogic Meson serial port driver"); 875MODULE_LICENSE("GPL v2"); 876