1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12#include <linux/bitops.h> 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/device.h> 16#include <linux/gpio/driver.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_device.h> 20#include <linux/regmap.h> 21#include <linux/serial_core.h> 22#include <linux/serial.h> 23#include <linux/tty.h> 24#include <linux/tty_flip.h> 25#include <linux/spi/spi.h> 26#include <linux/uaccess.h> 27 28#define MAX310X_NAME "max310x" 29#define MAX310X_MAJOR 204 30#define MAX310X_MINOR 209 31#define MAX310X_UART_NRMAX 16 32 33/* MAX310X register definitions */ 34#define MAX310X_RHR_REG (0x00) /* RX FIFO */ 35#define MAX310X_THR_REG (0x00) /* TX FIFO */ 36#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 37#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 38#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 39#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 40#define MAX310X_REG_05 (0x05) 41#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 42#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 43#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 44#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 45#define MAX310X_MODE1_REG (0x09) /* MODE1 */ 46#define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 47#define MAX310X_LCR_REG (0x0b) /* LCR */ 48#define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 49#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 50#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 51#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 52#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 53#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 54#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 55#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 56#define MAX310X_XON1_REG (0x14) /* XON1 character */ 57#define MAX310X_XON2_REG (0x15) /* XON2 character */ 58#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 59#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 60#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 61#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 62#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 63#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 64#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 65#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 66#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 67#define MAX310X_REG_1F (0x1f) 68 69#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 70 71#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 72#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 73 74/* Extended registers */ 75#define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 76 77/* IRQ register bits */ 78#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 79#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 80#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 81#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 82#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 83#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 84#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 85#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 86 87/* LSR register bits */ 88#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 89#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 90#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 91#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 92#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 93#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 94#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 95 96/* Special character register bits */ 97#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 98#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 99#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 100#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 101#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 102#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 103 104/* Status register bits */ 105#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 106#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 107#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 108#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 109#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 110#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 111 112/* MODE1 register bits */ 113#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 114#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 115#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 116#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 117#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 118#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 119#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 120#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 121 122/* MODE2 register bits */ 123#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 124#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 125#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 126#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 127#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 128#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 129#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 130#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 131 132/* LCR register bits */ 133#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 134#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 135 * 136 * Word length bits table: 137 * 00 -> 5 bit words 138 * 01 -> 6 bit words 139 * 10 -> 7 bit words 140 * 11 -> 8 bit words 141 */ 142#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 143 * 144 * STOP length bit table: 145 * 0 -> 1 stop bit 146 * 1 -> 1-1.5 stop bits if 147 * word length is 5, 148 * 2 stop bits otherwise 149 */ 150#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 151#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 152#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 153#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 154#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 155 156/* IRDA register bits */ 157#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 158#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 159 160/* Flow control trigger level register masks */ 161#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 162#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 163#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 164#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 165 166/* FIFO interrupt trigger level register masks */ 167#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 168#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 169#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 170#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 171 172/* Flow control register bits */ 173#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 174#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 175#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 176 * are used in conjunction with 177 * XOFF2 for definition of 178 * special character */ 179#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 180#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 181#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 182 * 183 * SWFLOW bits 1 & 0 table: 184 * 00 -> no transmitter flow 185 * control 186 * 01 -> receiver compares 187 * XON2 and XOFF2 188 * and controls 189 * transmitter 190 * 10 -> receiver compares 191 * XON1 and XOFF1 192 * and controls 193 * transmitter 194 * 11 -> receiver compares 195 * XON1, XON2, XOFF1 and 196 * XOFF2 and controls 197 * transmitter 198 */ 199#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 200#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 201 * 202 * SWFLOW bits 3 & 2 table: 203 * 00 -> no received flow 204 * control 205 * 01 -> transmitter generates 206 * XON2 and XOFF2 207 * 10 -> transmitter generates 208 * XON1 and XOFF1 209 * 11 -> transmitter generates 210 * XON1, XON2, XOFF1 and 211 * XOFF2 212 */ 213 214/* PLL configuration register masks */ 215#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 216#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 217 218/* Baud rate generator configuration register bits */ 219#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 220#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 221 222/* Clock source register bits */ 223#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 224#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 225#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 226#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 227#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 228 229/* Global commands */ 230#define MAX310X_EXTREG_ENBL (0xce) 231#define MAX310X_EXTREG_DSBL (0xcd) 232 233/* Misc definitions */ 234#define MAX310X_FIFO_SIZE (128) 235#define MAX310x_REV_MASK (0xf8) 236#define MAX310X_WRITE_BIT 0x80 237 238/* Crystal-related definitions */ 239#define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 240#define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 241 242/* MAX3107 specific */ 243#define MAX3107_REV_ID (0xa0) 244 245/* MAX3109 specific */ 246#define MAX3109_REV_ID (0xc0) 247 248/* MAX14830 specific */ 249#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 250#define MAX14830_REV_ID (0xb0) 251 252struct max310x_devtype { 253 char name[9]; 254 int nr; 255 u8 mode1; 256 int (*detect)(struct device *); 257 void (*power)(struct uart_port *, int); 258}; 259 260struct max310x_one { 261 struct uart_port port; 262 struct work_struct tx_work; 263 struct work_struct md_work; 264 struct work_struct rs_work; 265 266 u8 wr_header; 267 u8 rd_header; 268 u8 rx_buf[MAX310X_FIFO_SIZE]; 269}; 270#define to_max310x_port(_port) \ 271 container_of(_port, struct max310x_one, port) 272 273struct max310x_port { 274 struct max310x_devtype *devtype; 275 struct regmap *regmap; 276 struct clk *clk; 277#ifdef CONFIG_GPIOLIB 278 struct gpio_chip gpio; 279#endif 280 struct max310x_one p[0]; 281}; 282 283static struct uart_driver max310x_uart = { 284 .owner = THIS_MODULE, 285 .driver_name = MAX310X_NAME, 286 .dev_name = "ttyMAX", 287 .major = MAX310X_MAJOR, 288 .minor = MAX310X_MINOR, 289 .nr = MAX310X_UART_NRMAX, 290}; 291 292static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 293 294static u8 max310x_port_read(struct uart_port *port, u8 reg) 295{ 296 struct max310x_port *s = dev_get_drvdata(port->dev); 297 unsigned int val = 0; 298 299 regmap_read(s->regmap, port->iobase + reg, &val); 300 301 return val; 302} 303 304static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 305{ 306 struct max310x_port *s = dev_get_drvdata(port->dev); 307 308 regmap_write(s->regmap, port->iobase + reg, val); 309} 310 311static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 312{ 313 struct max310x_port *s = dev_get_drvdata(port->dev); 314 315 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); 316} 317 318static int max3107_detect(struct device *dev) 319{ 320 struct max310x_port *s = dev_get_drvdata(dev); 321 unsigned int val = 0; 322 int ret; 323 324 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 325 if (ret) 326 return ret; 327 328 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 329 dev_err(dev, 330 "%s ID 0x%02x does not match\n", s->devtype->name, val); 331 return -ENODEV; 332 } 333 334 return 0; 335} 336 337static int max3108_detect(struct device *dev) 338{ 339 struct max310x_port *s = dev_get_drvdata(dev); 340 unsigned int val = 0; 341 int ret; 342 343 /* MAX3108 have not REV ID register, we just check default value 344 * from clocksource register to make sure everything works. 345 */ 346 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 347 if (ret) 348 return ret; 349 350 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 351 dev_err(dev, "%s not present\n", s->devtype->name); 352 return -ENODEV; 353 } 354 355 return 0; 356} 357 358static int max3109_detect(struct device *dev) 359{ 360 struct max310x_port *s = dev_get_drvdata(dev); 361 unsigned int val = 0; 362 int ret; 363 364 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 365 MAX310X_EXTREG_ENBL); 366 if (ret) 367 return ret; 368 369 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 370 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 371 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 372 dev_err(dev, 373 "%s ID 0x%02x does not match\n", s->devtype->name, val); 374 return -ENODEV; 375 } 376 377 return 0; 378} 379 380static void max310x_power(struct uart_port *port, int on) 381{ 382 max310x_port_update(port, MAX310X_MODE1_REG, 383 MAX310X_MODE1_FORCESLEEP_BIT, 384 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 385 if (on) 386 msleep(50); 387} 388 389static int max14830_detect(struct device *dev) 390{ 391 struct max310x_port *s = dev_get_drvdata(dev); 392 unsigned int val = 0; 393 int ret; 394 395 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 396 MAX310X_EXTREG_ENBL); 397 if (ret) 398 return ret; 399 400 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 401 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 402 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 403 dev_err(dev, 404 "%s ID 0x%02x does not match\n", s->devtype->name, val); 405 return -ENODEV; 406 } 407 408 return 0; 409} 410 411static void max14830_power(struct uart_port *port, int on) 412{ 413 max310x_port_update(port, MAX310X_BRGCFG_REG, 414 MAX14830_BRGCFG_CLKDIS_BIT, 415 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 416 if (on) 417 msleep(50); 418} 419 420static const struct max310x_devtype max3107_devtype = { 421 .name = "MAX3107", 422 .nr = 1, 423 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 424 .detect = max3107_detect, 425 .power = max310x_power, 426}; 427 428static const struct max310x_devtype max3108_devtype = { 429 .name = "MAX3108", 430 .nr = 1, 431 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 432 .detect = max3108_detect, 433 .power = max310x_power, 434}; 435 436static const struct max310x_devtype max3109_devtype = { 437 .name = "MAX3109", 438 .nr = 2, 439 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 440 .detect = max3109_detect, 441 .power = max310x_power, 442}; 443 444static const struct max310x_devtype max14830_devtype = { 445 .name = "MAX14830", 446 .nr = 4, 447 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 448 .detect = max14830_detect, 449 .power = max14830_power, 450}; 451 452static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 453{ 454 switch (reg & 0x1f) { 455 case MAX310X_IRQSTS_REG: 456 case MAX310X_LSR_IRQSTS_REG: 457 case MAX310X_SPCHR_IRQSTS_REG: 458 case MAX310X_STS_IRQSTS_REG: 459 case MAX310X_TXFIFOLVL_REG: 460 case MAX310X_RXFIFOLVL_REG: 461 return false; 462 default: 463 break; 464 } 465 466 return true; 467} 468 469static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 470{ 471 switch (reg & 0x1f) { 472 case MAX310X_RHR_REG: 473 case MAX310X_IRQSTS_REG: 474 case MAX310X_LSR_IRQSTS_REG: 475 case MAX310X_SPCHR_IRQSTS_REG: 476 case MAX310X_STS_IRQSTS_REG: 477 case MAX310X_TXFIFOLVL_REG: 478 case MAX310X_RXFIFOLVL_REG: 479 case MAX310X_GPIODATA_REG: 480 case MAX310X_BRGDIVLSB_REG: 481 case MAX310X_REG_05: 482 case MAX310X_REG_1F: 483 return true; 484 default: 485 break; 486 } 487 488 return false; 489} 490 491static bool max310x_reg_precious(struct device *dev, unsigned int reg) 492{ 493 switch (reg & 0x1f) { 494 case MAX310X_RHR_REG: 495 case MAX310X_IRQSTS_REG: 496 case MAX310X_SPCHR_IRQSTS_REG: 497 case MAX310X_STS_IRQSTS_REG: 498 return true; 499 default: 500 break; 501 } 502 503 return false; 504} 505 506static int max310x_set_baud(struct uart_port *port, int baud) 507{ 508 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 509 510 /* 511 * Calculate the integer divisor first. Select a proper mode 512 * in case if the requested baud is too high for the pre-defined 513 * clocks frequency. 514 */ 515 div = port->uartclk / baud; 516 if (div < 8) { 517 /* Mode x4 */ 518 c = 4; 519 mode = MAX310X_BRGCFG_4XMODE_BIT; 520 } else if (div < 16) { 521 /* Mode x2 */ 522 c = 8; 523 mode = MAX310X_BRGCFG_2XMODE_BIT; 524 } else { 525 c = 16; 526 } 527 528 /* Calculate the divisor in accordance with the fraction coefficient */ 529 div /= c; 530 F = c*baud; 531 532 /* Calculate the baud rate fraction */ 533 if (div > 0) 534 frac = (16*(port->uartclk % F)) / F; 535 else 536 div = 1; 537 538 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 539 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 540 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 541 542 /* Return the actual baud rate we just programmed */ 543 return (16*port->uartclk) / (c*(16*div + frac)); 544} 545 546static int max310x_update_best_err(unsigned long f, long *besterr) 547{ 548 /* Use baudrate 115200 for calculate error */ 549 long err = f % (460800 * 16); 550 551 if ((*besterr < 0) || (*besterr > err)) { 552 *besterr = err; 553 return 0; 554 } 555 556 return 1; 557} 558 559static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 560 unsigned long freq, bool xtal) 561{ 562 unsigned int div, clksrc, pllcfg = 0; 563 long besterr = -1; 564 unsigned long fdiv, fmul, bestfreq = freq; 565 566 /* First, update error without PLL */ 567 max310x_update_best_err(freq, &besterr); 568 569 /* Try all possible PLL dividers */ 570 for (div = 1; (div <= 63) && besterr; div++) { 571 fdiv = DIV_ROUND_CLOSEST(freq, div); 572 573 /* Try multiplier 6 */ 574 fmul = fdiv * 6; 575 if ((fdiv >= 500000) && (fdiv <= 800000)) 576 if (!max310x_update_best_err(fmul, &besterr)) { 577 pllcfg = (0 << 6) | div; 578 bestfreq = fmul; 579 } 580 /* Try multiplier 48 */ 581 fmul = fdiv * 48; 582 if ((fdiv >= 850000) && (fdiv <= 1200000)) 583 if (!max310x_update_best_err(fmul, &besterr)) { 584 pllcfg = (1 << 6) | div; 585 bestfreq = fmul; 586 } 587 /* Try multiplier 96 */ 588 fmul = fdiv * 96; 589 if ((fdiv >= 425000) && (fdiv <= 1000000)) 590 if (!max310x_update_best_err(fmul, &besterr)) { 591 pllcfg = (2 << 6) | div; 592 bestfreq = fmul; 593 } 594 /* Try multiplier 144 */ 595 fmul = fdiv * 144; 596 if ((fdiv >= 390000) && (fdiv <= 667000)) 597 if (!max310x_update_best_err(fmul, &besterr)) { 598 pllcfg = (3 << 6) | div; 599 bestfreq = fmul; 600 } 601 } 602 603 /* Configure clock source */ 604 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 605 606 /* Configure PLL */ 607 if (pllcfg) { 608 clksrc |= MAX310X_CLKSRC_PLL_BIT; 609 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 610 } else 611 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 612 613 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 614 615 /* Wait for crystal */ 616 if (xtal) { 617 bool stable = false; 618 unsigned int try = 0, val = 0; 619 620 do { 621 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 622 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 623 624 if (val & MAX310X_STS_CLKREADY_BIT) 625 stable = true; 626 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 627 628 if (!stable) 629 dev_warn(dev, "clock is not stable yet\n"); 630 } 631 632 return (int)bestfreq; 633} 634 635static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 636{ 637 struct max310x_one *one = to_max310x_port(port); 638 struct spi_transfer xfer[] = { 639 { 640 .tx_buf = &one->wr_header, 641 .len = sizeof(one->wr_header), 642 }, { 643 .tx_buf = txbuf, 644 .len = len, 645 } 646 }; 647 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 648} 649 650static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 651{ 652 struct max310x_one *one = to_max310x_port(port); 653 struct spi_transfer xfer[] = { 654 { 655 .tx_buf = &one->rd_header, 656 .len = sizeof(one->rd_header), 657 }, { 658 .rx_buf = rxbuf, 659 .len = len, 660 } 661 }; 662 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 663} 664 665static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 666{ 667 struct max310x_one *one = to_max310x_port(port); 668 unsigned int sts, ch, flag, i; 669 670 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 671 /* We are just reading, happily ignoring any error conditions. 672 * Break condition, parity checking, framing errors -- they 673 * are all ignored. That means that we can do a batch-read. 674 * 675 * There is a small opportunity for race if the RX FIFO 676 * overruns while we're reading the buffer; the datasheets says 677 * that the LSR register applies to the "current" character. 678 * That's also the reason why we cannot do batched reads when 679 * asked to check the individual statuses. 680 * */ 681 682 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 683 max310x_batch_read(port, one->rx_buf, rxlen); 684 685 port->icount.rx += rxlen; 686 flag = TTY_NORMAL; 687 sts &= port->read_status_mask; 688 689 if (sts & MAX310X_LSR_RXOVR_BIT) { 690 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 691 port->icount.overrun++; 692 } 693 694 for (i = 0; i < (rxlen - 1); ++i) 695 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 696 697 /* 698 * Handle the overrun case for the last character only, since 699 * the RxFIFO overflow happens after it is pushed to the FIFO 700 * tail. 701 */ 702 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 703 one->rx_buf[rxlen-1], flag); 704 705 } else { 706 if (unlikely(rxlen >= port->fifosize)) { 707 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 708 port->icount.buf_overrun++; 709 /* Ensure sanity of RX level */ 710 rxlen = port->fifosize; 711 } 712 713 while (rxlen--) { 714 ch = max310x_port_read(port, MAX310X_RHR_REG); 715 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 716 717 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 718 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 719 720 port->icount.rx++; 721 flag = TTY_NORMAL; 722 723 if (unlikely(sts)) { 724 if (sts & MAX310X_LSR_RXBRK_BIT) { 725 port->icount.brk++; 726 if (uart_handle_break(port)) 727 continue; 728 } else if (sts & MAX310X_LSR_RXPAR_BIT) 729 port->icount.parity++; 730 else if (sts & MAX310X_LSR_FRERR_BIT) 731 port->icount.frame++; 732 else if (sts & MAX310X_LSR_RXOVR_BIT) 733 port->icount.overrun++; 734 735 sts &= port->read_status_mask; 736 if (sts & MAX310X_LSR_RXBRK_BIT) 737 flag = TTY_BREAK; 738 else if (sts & MAX310X_LSR_RXPAR_BIT) 739 flag = TTY_PARITY; 740 else if (sts & MAX310X_LSR_FRERR_BIT) 741 flag = TTY_FRAME; 742 else if (sts & MAX310X_LSR_RXOVR_BIT) 743 flag = TTY_OVERRUN; 744 } 745 746 if (uart_handle_sysrq_char(port, ch)) 747 continue; 748 749 if (sts & port->ignore_status_mask) 750 continue; 751 752 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 753 } 754 } 755 756 tty_flip_buffer_push(&port->state->port); 757} 758 759static void max310x_handle_tx(struct uart_port *port) 760{ 761 struct circ_buf *xmit = &port->state->xmit; 762 unsigned int txlen, to_send, until_end; 763 764 if (unlikely(port->x_char)) { 765 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 766 port->icount.tx++; 767 port->x_char = 0; 768 return; 769 } 770 771 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 772 return; 773 774 /* Get length of data pending in circular buffer */ 775 to_send = uart_circ_chars_pending(xmit); 776 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 777 if (likely(to_send)) { 778 /* Limit to size of TX FIFO */ 779 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 780 txlen = port->fifosize - txlen; 781 to_send = (to_send > txlen) ? txlen : to_send; 782 783 if (until_end < to_send) { 784 /* It's a circ buffer -- wrap around. 785 * We could do that in one SPI transaction, but meh. */ 786 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 787 max310x_batch_write(port, xmit->buf, to_send - until_end); 788 } else { 789 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 790 } 791 792 /* Add data to send */ 793 port->icount.tx += to_send; 794 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); 795 } 796 797 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 798 uart_write_wakeup(port); 799} 800 801static void max310x_start_tx(struct uart_port *port) 802{ 803 struct max310x_one *one = to_max310x_port(port); 804 805 schedule_work(&one->tx_work); 806} 807 808static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 809{ 810 struct uart_port *port = &s->p[portno].port; 811 irqreturn_t res = IRQ_NONE; 812 813 do { 814 unsigned int ists, lsr, rxlen; 815 816 /* Read IRQ status & RX FIFO level */ 817 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 818 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 819 if (!ists && !rxlen) 820 break; 821 822 res = IRQ_HANDLED; 823 824 if (ists & MAX310X_IRQ_CTS_BIT) { 825 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 826 uart_handle_cts_change(port, 827 !!(lsr & MAX310X_LSR_CTS_BIT)); 828 } 829 if (rxlen) 830 max310x_handle_rx(port, rxlen); 831 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 832 max310x_start_tx(port); 833 } while (1); 834 return res; 835} 836 837static irqreturn_t max310x_ist(int irq, void *dev_id) 838{ 839 struct max310x_port *s = (struct max310x_port *)dev_id; 840 bool handled = false; 841 842 if (s->devtype->nr > 1) { 843 do { 844 unsigned int val = ~0; 845 846 WARN_ON_ONCE(regmap_read(s->regmap, 847 MAX310X_GLOBALIRQ_REG, &val)); 848 val = ((1 << s->devtype->nr) - 1) & ~val; 849 if (!val) 850 break; 851 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 852 handled = true; 853 } while (1); 854 } else { 855 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 856 handled = true; 857 } 858 859 return IRQ_RETVAL(handled); 860} 861 862static void max310x_tx_proc(struct work_struct *ws) 863{ 864 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 865 866 max310x_handle_tx(&one->port); 867} 868 869static unsigned int max310x_tx_empty(struct uart_port *port) 870{ 871 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 872 873 return lvl ? 0 : TIOCSER_TEMT; 874} 875 876static unsigned int max310x_get_mctrl(struct uart_port *port) 877{ 878 /* DCD and DSR are not wired and CTS/RTS is handled automatically 879 * so just indicate DSR and CAR asserted 880 */ 881 return TIOCM_DSR | TIOCM_CAR; 882} 883 884static void max310x_md_proc(struct work_struct *ws) 885{ 886 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 887 888 max310x_port_update(&one->port, MAX310X_MODE2_REG, 889 MAX310X_MODE2_LOOPBACK_BIT, 890 (one->port.mctrl & TIOCM_LOOP) ? 891 MAX310X_MODE2_LOOPBACK_BIT : 0); 892} 893 894static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 895{ 896 struct max310x_one *one = to_max310x_port(port); 897 898 schedule_work(&one->md_work); 899} 900 901static void max310x_break_ctl(struct uart_port *port, int break_state) 902{ 903 max310x_port_update(port, MAX310X_LCR_REG, 904 MAX310X_LCR_TXBREAK_BIT, 905 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 906} 907 908static void max310x_set_termios(struct uart_port *port, 909 struct ktermios *termios, 910 struct ktermios *old) 911{ 912 unsigned int lcr = 0, flow = 0; 913 int baud; 914 915 /* Mask termios capabilities we don't support */ 916 termios->c_cflag &= ~CMSPAR; 917 918 /* Word size */ 919 switch (termios->c_cflag & CSIZE) { 920 case CS5: 921 break; 922 case CS6: 923 lcr = MAX310X_LCR_LENGTH0_BIT; 924 break; 925 case CS7: 926 lcr = MAX310X_LCR_LENGTH1_BIT; 927 break; 928 case CS8: 929 default: 930 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 931 break; 932 } 933 934 /* Parity */ 935 if (termios->c_cflag & PARENB) { 936 lcr |= MAX310X_LCR_PARITY_BIT; 937 if (!(termios->c_cflag & PARODD)) 938 lcr |= MAX310X_LCR_EVENPARITY_BIT; 939 } 940 941 /* Stop bits */ 942 if (termios->c_cflag & CSTOPB) 943 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 944 945 /* Update LCR register */ 946 max310x_port_write(port, MAX310X_LCR_REG, lcr); 947 948 /* Set read status mask */ 949 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 950 if (termios->c_iflag & INPCK) 951 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 952 MAX310X_LSR_FRERR_BIT; 953 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 954 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 955 956 /* Set status ignore mask */ 957 port->ignore_status_mask = 0; 958 if (termios->c_iflag & IGNBRK) 959 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 960 if (!(termios->c_cflag & CREAD)) 961 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 962 MAX310X_LSR_RXOVR_BIT | 963 MAX310X_LSR_FRERR_BIT | 964 MAX310X_LSR_RXBRK_BIT; 965 966 /* Configure flow control */ 967 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 968 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 969 970 /* Disable transmitter before enabling AutoCTS or auto transmitter 971 * flow control 972 */ 973 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 974 max310x_port_update(port, MAX310X_MODE1_REG, 975 MAX310X_MODE1_TXDIS_BIT, 976 MAX310X_MODE1_TXDIS_BIT); 977 } 978 979 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 980 981 if (termios->c_cflag & CRTSCTS) { 982 /* Enable AUTORTS and AUTOCTS */ 983 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 984 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 985 MAX310X_FLOWCTRL_AUTORTS_BIT; 986 } 987 if (termios->c_iflag & IXON) 988 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 989 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 990 if (termios->c_iflag & IXOFF) { 991 port->status |= UPSTAT_AUTOXOFF; 992 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 993 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 994 } 995 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 996 997 /* Enable transmitter after disabling AutoCTS and auto transmitter 998 * flow control 999 */ 1000 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1001 max310x_port_update(port, MAX310X_MODE1_REG, 1002 MAX310X_MODE1_TXDIS_BIT, 1003 0); 1004 } 1005 1006 /* Get baud rate generator configuration */ 1007 baud = uart_get_baud_rate(port, termios, old, 1008 port->uartclk / 16 / 0xffff, 1009 port->uartclk / 4); 1010 1011 /* Setup baudrate generator */ 1012 baud = max310x_set_baud(port, baud); 1013 1014 /* Update timeout according to new baud rate */ 1015 uart_update_timeout(port, termios->c_cflag, baud); 1016} 1017 1018static void max310x_rs_proc(struct work_struct *ws) 1019{ 1020 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1021 unsigned int delay, mode1 = 0, mode2 = 0; 1022 1023 delay = (one->port.rs485.delay_rts_before_send << 4) | 1024 one->port.rs485.delay_rts_after_send; 1025 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1026 1027 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1028 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1029 1030 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1031 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1032 } 1033 1034 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1035 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1036 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1037 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1038} 1039 1040static int max310x_rs485_config(struct uart_port *port, 1041 struct serial_rs485 *rs485) 1042{ 1043 struct max310x_one *one = to_max310x_port(port); 1044 1045 if ((rs485->delay_rts_before_send > 0x0f) || 1046 (rs485->delay_rts_after_send > 0x0f)) 1047 return -ERANGE; 1048 1049 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | 1050 SER_RS485_ENABLED; 1051 memset(rs485->padding, 0, sizeof(rs485->padding)); 1052 port->rs485 = *rs485; 1053 1054 schedule_work(&one->rs_work); 1055 1056 return 0; 1057} 1058 1059static int max310x_startup(struct uart_port *port) 1060{ 1061 struct max310x_port *s = dev_get_drvdata(port->dev); 1062 unsigned int val; 1063 1064 s->devtype->power(port, 1); 1065 1066 /* Configure MODE1 register */ 1067 max310x_port_update(port, MAX310X_MODE1_REG, 1068 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1069 1070 /* Configure MODE2 register & Reset FIFOs*/ 1071 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1072 max310x_port_write(port, MAX310X_MODE2_REG, val); 1073 max310x_port_update(port, MAX310X_MODE2_REG, 1074 MAX310X_MODE2_FIFORST_BIT, 0); 1075 1076 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1077 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1078 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1079 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1080 1081 if (port->rs485.flags & SER_RS485_ENABLED) { 1082 max310x_port_update(port, MAX310X_MODE1_REG, 1083 MAX310X_MODE1_TRNSCVCTRL_BIT, 1084 MAX310X_MODE1_TRNSCVCTRL_BIT); 1085 1086 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1087 max310x_port_update(port, MAX310X_MODE2_REG, 1088 MAX310X_MODE2_ECHOSUPR_BIT, 1089 MAX310X_MODE2_ECHOSUPR_BIT); 1090 } 1091 1092 /* Configure flow control levels */ 1093 /* Flow control halt level 96, resume level 48 */ 1094 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1095 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1096 1097 /* Clear IRQ status register */ 1098 max310x_port_read(port, MAX310X_IRQSTS_REG); 1099 1100 /* Enable RX, TX, CTS change interrupts */ 1101 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1102 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1103 1104 return 0; 1105} 1106 1107static void max310x_shutdown(struct uart_port *port) 1108{ 1109 struct max310x_port *s = dev_get_drvdata(port->dev); 1110 1111 /* Disable all interrupts */ 1112 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1113 1114 s->devtype->power(port, 0); 1115} 1116 1117static const char *max310x_type(struct uart_port *port) 1118{ 1119 struct max310x_port *s = dev_get_drvdata(port->dev); 1120 1121 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1122} 1123 1124static int max310x_request_port(struct uart_port *port) 1125{ 1126 /* Do nothing */ 1127 return 0; 1128} 1129 1130static void max310x_config_port(struct uart_port *port, int flags) 1131{ 1132 if (flags & UART_CONFIG_TYPE) 1133 port->type = PORT_MAX310X; 1134} 1135 1136static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1137{ 1138 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1139 return -EINVAL; 1140 if (s->irq != port->irq) 1141 return -EINVAL; 1142 1143 return 0; 1144} 1145 1146static void max310x_null_void(struct uart_port *port) 1147{ 1148 /* Do nothing */ 1149} 1150 1151static const struct uart_ops max310x_ops = { 1152 .tx_empty = max310x_tx_empty, 1153 .set_mctrl = max310x_set_mctrl, 1154 .get_mctrl = max310x_get_mctrl, 1155 .stop_tx = max310x_null_void, 1156 .start_tx = max310x_start_tx, 1157 .stop_rx = max310x_null_void, 1158 .break_ctl = max310x_break_ctl, 1159 .startup = max310x_startup, 1160 .shutdown = max310x_shutdown, 1161 .set_termios = max310x_set_termios, 1162 .type = max310x_type, 1163 .request_port = max310x_request_port, 1164 .release_port = max310x_null_void, 1165 .config_port = max310x_config_port, 1166 .verify_port = max310x_verify_port, 1167}; 1168 1169static int __maybe_unused max310x_suspend(struct device *dev) 1170{ 1171 struct max310x_port *s = dev_get_drvdata(dev); 1172 int i; 1173 1174 for (i = 0; i < s->devtype->nr; i++) { 1175 uart_suspend_port(&max310x_uart, &s->p[i].port); 1176 s->devtype->power(&s->p[i].port, 0); 1177 } 1178 1179 return 0; 1180} 1181 1182static int __maybe_unused max310x_resume(struct device *dev) 1183{ 1184 struct max310x_port *s = dev_get_drvdata(dev); 1185 int i; 1186 1187 for (i = 0; i < s->devtype->nr; i++) { 1188 s->devtype->power(&s->p[i].port, 1); 1189 uart_resume_port(&max310x_uart, &s->p[i].port); 1190 } 1191 1192 return 0; 1193} 1194 1195static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1196 1197#ifdef CONFIG_GPIOLIB 1198static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1199{ 1200 unsigned int val; 1201 struct max310x_port *s = gpiochip_get_data(chip); 1202 struct uart_port *port = &s->p[offset / 4].port; 1203 1204 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1205 1206 return !!((val >> 4) & (1 << (offset % 4))); 1207} 1208 1209static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1210{ 1211 struct max310x_port *s = gpiochip_get_data(chip); 1212 struct uart_port *port = &s->p[offset / 4].port; 1213 1214 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1215 value ? 1 << (offset % 4) : 0); 1216} 1217 1218static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1219{ 1220 struct max310x_port *s = gpiochip_get_data(chip); 1221 struct uart_port *port = &s->p[offset / 4].port; 1222 1223 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1224 1225 return 0; 1226} 1227 1228static int max310x_gpio_direction_output(struct gpio_chip *chip, 1229 unsigned offset, int value) 1230{ 1231 struct max310x_port *s = gpiochip_get_data(chip); 1232 struct uart_port *port = &s->p[offset / 4].port; 1233 1234 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1235 value ? 1 << (offset % 4) : 0); 1236 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1237 1 << (offset % 4)); 1238 1239 return 0; 1240} 1241 1242static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1243 unsigned long config) 1244{ 1245 struct max310x_port *s = gpiochip_get_data(chip); 1246 struct uart_port *port = &s->p[offset / 4].port; 1247 1248 switch (pinconf_to_config_param(config)) { 1249 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1250 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1251 1 << ((offset % 4) + 4), 1252 1 << ((offset % 4) + 4)); 1253 return 0; 1254 case PIN_CONFIG_DRIVE_PUSH_PULL: 1255 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1256 1 << ((offset % 4) + 4), 0); 1257 return 0; 1258 default: 1259 return -ENOTSUPP; 1260 } 1261} 1262#endif 1263 1264static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, 1265 struct regmap *regmap, int irq) 1266{ 1267 int i, ret, fmin, fmax, freq, uartclk; 1268 struct clk *clk_osc, *clk_xtal; 1269 struct max310x_port *s; 1270 bool xtal = false; 1271 1272 if (IS_ERR(regmap)) 1273 return PTR_ERR(regmap); 1274 1275 /* Alloc port structure */ 1276 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1277 if (!s) { 1278 dev_err(dev, "Error allocating port structure\n"); 1279 return -ENOMEM; 1280 } 1281 1282 clk_osc = devm_clk_get(dev, "osc"); 1283 clk_xtal = devm_clk_get(dev, "xtal"); 1284 if (!IS_ERR(clk_osc)) { 1285 s->clk = clk_osc; 1286 fmin = 500000; 1287 fmax = 35000000; 1288 } else if (!IS_ERR(clk_xtal)) { 1289 s->clk = clk_xtal; 1290 fmin = 1000000; 1291 fmax = 4000000; 1292 xtal = true; 1293 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || 1294 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { 1295 return -EPROBE_DEFER; 1296 } else { 1297 dev_err(dev, "Cannot get clock\n"); 1298 return -EINVAL; 1299 } 1300 1301 ret = clk_prepare_enable(s->clk); 1302 if (ret) 1303 return ret; 1304 1305 freq = clk_get_rate(s->clk); 1306 /* Check frequency limits */ 1307 if (freq < fmin || freq > fmax) { 1308 ret = -ERANGE; 1309 goto out_clk; 1310 } 1311 1312 s->regmap = regmap; 1313 s->devtype = devtype; 1314 dev_set_drvdata(dev, s); 1315 1316 /* Check device to ensure we are talking to what we expect */ 1317 ret = devtype->detect(dev); 1318 if (ret) 1319 goto out_clk; 1320 1321 for (i = 0; i < devtype->nr; i++) { 1322 unsigned int offs = i << 5; 1323 1324 /* Reset port */ 1325 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 1326 MAX310X_MODE2_RST_BIT); 1327 /* Clear port reset */ 1328 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); 1329 1330 /* Wait for port startup */ 1331 do { 1332 regmap_read(s->regmap, 1333 MAX310X_BRGDIVLSB_REG + offs, &ret); 1334 } while (ret != 0x01); 1335 1336 regmap_write(s->regmap, MAX310X_MODE1_REG + offs, 1337 devtype->mode1); 1338 } 1339 1340 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1341 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1342 1343 for (i = 0; i < devtype->nr; i++) { 1344 unsigned int line; 1345 1346 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1347 if (line == MAX310X_UART_NRMAX) { 1348 ret = -ERANGE; 1349 goto out_uart; 1350 } 1351 1352 /* Initialize port data */ 1353 s->p[i].port.line = line; 1354 s->p[i].port.dev = dev; 1355 s->p[i].port.irq = irq; 1356 s->p[i].port.type = PORT_MAX310X; 1357 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1358 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1359 s->p[i].port.iotype = UPIO_PORT; 1360 s->p[i].port.iobase = i * 0x20; 1361 s->p[i].port.membase = (void __iomem *)~0; 1362 s->p[i].port.uartclk = uartclk; 1363 s->p[i].port.rs485_config = max310x_rs485_config; 1364 s->p[i].port.ops = &max310x_ops; 1365 /* Disable all interrupts */ 1366 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1367 /* Clear IRQ status register */ 1368 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1369 /* Initialize queue for start TX */ 1370 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1371 /* Initialize queue for changing LOOPBACK mode */ 1372 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1373 /* Initialize queue for changing RS485 mode */ 1374 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1375 /* Initialize SPI-transfer buffers */ 1376 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) | 1377 MAX310X_WRITE_BIT; 1378 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG); 1379 1380 /* Register port */ 1381 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1382 if (ret) { 1383 s->p[i].port.dev = NULL; 1384 goto out_uart; 1385 } 1386 set_bit(line, max310x_lines); 1387 1388 /* Go to suspend mode */ 1389 devtype->power(&s->p[i].port, 0); 1390 } 1391 1392#ifdef CONFIG_GPIOLIB 1393 /* Setup GPIO cotroller */ 1394 s->gpio.owner = THIS_MODULE; 1395 s->gpio.parent = dev; 1396 s->gpio.label = devtype->name; 1397 s->gpio.direction_input = max310x_gpio_direction_input; 1398 s->gpio.get = max310x_gpio_get; 1399 s->gpio.direction_output= max310x_gpio_direction_output; 1400 s->gpio.set = max310x_gpio_set; 1401 s->gpio.set_config = max310x_gpio_set_config; 1402 s->gpio.base = -1; 1403 s->gpio.ngpio = devtype->nr * 4; 1404 s->gpio.can_sleep = 1; 1405 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1406 if (ret) 1407 goto out_uart; 1408#endif 1409 1410 /* Setup interrupt */ 1411 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1412 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1413 if (!ret) 1414 return 0; 1415 1416 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1417 1418out_uart: 1419 for (i = 0; i < devtype->nr; i++) { 1420 if (s->p[i].port.dev) { 1421 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1422 clear_bit(s->p[i].port.line, max310x_lines); 1423 } 1424 } 1425 1426out_clk: 1427 clk_disable_unprepare(s->clk); 1428 1429 return ret; 1430} 1431 1432static int max310x_remove(struct device *dev) 1433{ 1434 struct max310x_port *s = dev_get_drvdata(dev); 1435 int i; 1436 1437 for (i = 0; i < s->devtype->nr; i++) { 1438 cancel_work_sync(&s->p[i].tx_work); 1439 cancel_work_sync(&s->p[i].md_work); 1440 cancel_work_sync(&s->p[i].rs_work); 1441 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1442 clear_bit(s->p[i].port.line, max310x_lines); 1443 s->devtype->power(&s->p[i].port, 0); 1444 } 1445 1446 clk_disable_unprepare(s->clk); 1447 1448 return 0; 1449} 1450 1451static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1452 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1453 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1454 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1455 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1456 { } 1457}; 1458MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1459 1460static struct regmap_config regcfg = { 1461 .reg_bits = 8, 1462 .val_bits = 8, 1463 .write_flag_mask = MAX310X_WRITE_BIT, 1464 .cache_type = REGCACHE_RBTREE, 1465 .writeable_reg = max310x_reg_writeable, 1466 .volatile_reg = max310x_reg_volatile, 1467 .precious_reg = max310x_reg_precious, 1468}; 1469 1470#ifdef CONFIG_SPI_MASTER 1471static int max310x_spi_probe(struct spi_device *spi) 1472{ 1473 struct max310x_devtype *devtype; 1474 struct regmap *regmap; 1475 int ret; 1476 1477 /* Setup SPI bus */ 1478 spi->bits_per_word = 8; 1479 spi->mode = spi->mode ? : SPI_MODE_0; 1480 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1481 ret = spi_setup(spi); 1482 if (ret) 1483 return ret; 1484 1485 if (spi->dev.of_node) { 1486 const struct of_device_id *of_id = 1487 of_match_device(max310x_dt_ids, &spi->dev); 1488 if (!of_id) 1489 return -ENODEV; 1490 1491 devtype = (struct max310x_devtype *)of_id->data; 1492 } else { 1493 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1494 1495 devtype = (struct max310x_devtype *)id_entry->driver_data; 1496 } 1497 1498 regcfg.max_register = devtype->nr * 0x20 - 1; 1499 regmap = devm_regmap_init_spi(spi, ®cfg); 1500 1501 return max310x_probe(&spi->dev, devtype, regmap, spi->irq); 1502} 1503 1504static int max310x_spi_remove(struct spi_device *spi) 1505{ 1506 return max310x_remove(&spi->dev); 1507} 1508 1509static const struct spi_device_id max310x_id_table[] = { 1510 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1511 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1512 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1513 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1514 { } 1515}; 1516MODULE_DEVICE_TABLE(spi, max310x_id_table); 1517 1518static struct spi_driver max310x_spi_driver = { 1519 .driver = { 1520 .name = MAX310X_NAME, 1521 .of_match_table = of_match_ptr(max310x_dt_ids), 1522 .pm = &max310x_pm_ops, 1523 }, 1524 .probe = max310x_spi_probe, 1525 .remove = max310x_spi_remove, 1526 .id_table = max310x_id_table, 1527}; 1528#endif 1529 1530static int __init max310x_uart_init(void) 1531{ 1532 int ret; 1533 1534 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1535 1536 ret = uart_register_driver(&max310x_uart); 1537 if (ret) 1538 return ret; 1539 1540#ifdef CONFIG_SPI_MASTER 1541 ret = spi_register_driver(&max310x_spi_driver); 1542 if (ret) 1543 uart_unregister_driver(&max310x_uart); 1544#endif 1545 1546 return ret; 1547} 1548module_init(max310x_uart_init); 1549 1550static void __exit max310x_uart_exit(void) 1551{ 1552#ifdef CONFIG_SPI_MASTER 1553 spi_unregister_driver(&max310x_spi_driver); 1554#endif 1555 1556 uart_unregister_driver(&max310x_uart); 1557} 1558module_exit(max310x_uart_exit); 1559 1560MODULE_LICENSE("GPL"); 1561MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1562MODULE_DESCRIPTION("MAX310X serial driver"); 1563