1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 4 * 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE 6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 7 * Copyright (C) 2007 John Crispin <john@phrozen.org> 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 9 */ 10 11#include <linux/clk.h> 12#include <linux/console.h> 13#include <linux/device.h> 14#include <linux/init.h> 15#include <linux/io.h> 16#include <linux/ioport.h> 17#include <linux/lantiq.h> 18#include <linux/module.h> 19#include <linux/of_address.h> 20#include <linux/of_irq.h> 21#include <linux/of_platform.h> 22#include <linux/serial.h> 23#include <linux/serial_core.h> 24#include <linux/slab.h> 25#include <linux/sysrq.h> 26#include <linux/tty.h> 27#include <linux/tty_flip.h> 28 29#define PORT_LTQ_ASC 111 30#define MAXPORTS 2 31#define UART_DUMMY_UER_RX 1 32#define DRVNAME "lantiq,asc" 33#ifdef __BIG_ENDIAN 34#define LTQ_ASC_TBUF (0x0020 + 3) 35#define LTQ_ASC_RBUF (0x0024 + 3) 36#else 37#define LTQ_ASC_TBUF 0x0020 38#define LTQ_ASC_RBUF 0x0024 39#endif 40#define LTQ_ASC_FSTAT 0x0048 41#define LTQ_ASC_WHBSTATE 0x0018 42#define LTQ_ASC_STATE 0x0014 43#define LTQ_ASC_IRNCR 0x00F8 44#define LTQ_ASC_CLC 0x0000 45#define LTQ_ASC_ID 0x0008 46#define LTQ_ASC_PISEL 0x0004 47#define LTQ_ASC_TXFCON 0x0044 48#define LTQ_ASC_RXFCON 0x0040 49#define LTQ_ASC_CON 0x0010 50#define LTQ_ASC_BG 0x0050 51#define LTQ_ASC_IRNREN 0x00F4 52 53#define ASC_IRNREN_TX 0x1 54#define ASC_IRNREN_RX 0x2 55#define ASC_IRNREN_ERR 0x4 56#define ASC_IRNREN_TX_BUF 0x8 57#define ASC_IRNCR_TIR 0x1 58#define ASC_IRNCR_RIR 0x2 59#define ASC_IRNCR_EIR 0x4 60#define ASC_IRNCR_MASK GENMASK(2, 0) 61 62#define ASCOPT_CSIZE 0x3 63#define TXFIFO_FL 1 64#define RXFIFO_FL 1 65#define ASCCLC_DISS 0x2 66#define ASCCLC_RMCMASK 0x0000FF00 67#define ASCCLC_RMCOFFSET 8 68#define ASCCON_M_8ASYNC 0x0 69#define ASCCON_M_7ASYNC 0x2 70#define ASCCON_ODD 0x00000020 71#define ASCCON_STP 0x00000080 72#define ASCCON_BRS 0x00000100 73#define ASCCON_FDE 0x00000200 74#define ASCCON_R 0x00008000 75#define ASCCON_FEN 0x00020000 76#define ASCCON_ROEN 0x00080000 77#define ASCCON_TOEN 0x00100000 78#define ASCSTATE_PE 0x00010000 79#define ASCSTATE_FE 0x00020000 80#define ASCSTATE_ROE 0x00080000 81#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 82#define ASCWHBSTATE_CLRREN 0x00000001 83#define ASCWHBSTATE_SETREN 0x00000002 84#define ASCWHBSTATE_CLRPE 0x00000004 85#define ASCWHBSTATE_CLRFE 0x00000008 86#define ASCWHBSTATE_CLRROE 0x00000020 87#define ASCTXFCON_TXFEN 0x0001 88#define ASCTXFCON_TXFFLU 0x0002 89#define ASCTXFCON_TXFITLMASK 0x3F00 90#define ASCTXFCON_TXFITLOFF 8 91#define ASCRXFCON_RXFEN 0x0001 92#define ASCRXFCON_RXFFLU 0x0002 93#define ASCRXFCON_RXFITLMASK 0x3F00 94#define ASCRXFCON_RXFITLOFF 8 95#define ASCFSTAT_RXFFLMASK 0x003F 96#define ASCFSTAT_TXFFLMASK 0x3F00 97#define ASCFSTAT_TXFREEMASK 0x3F000000 98#define ASCFSTAT_TXFREEOFF 24 99 100static void lqasc_tx_chars(struct uart_port *port); 101static struct ltq_uart_port *lqasc_port[MAXPORTS]; 102static struct uart_driver lqasc_reg; 103 104struct ltq_soc_data { 105 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port); 106 int (*request_irq)(struct uart_port *port); 107 void (*free_irq)(struct uart_port *port); 108}; 109 110struct ltq_uart_port { 111 struct uart_port port; 112 /* clock used to derive divider */ 113 struct clk *freqclk; 114 /* clock gating of the ASC core */ 115 struct clk *clk; 116 unsigned int tx_irq; 117 unsigned int rx_irq; 118 unsigned int err_irq; 119 unsigned int common_irq; 120 spinlock_t lock; /* exclusive access for multi core */ 121 122 const struct ltq_soc_data *soc; 123}; 124 125static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) 126{ 127 u32 tmp = __raw_readl(reg); 128 129 __raw_writel((tmp & ~clear) | set, reg); 130} 131 132static inline struct 133ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 134{ 135 return container_of(port, struct ltq_uart_port, port); 136} 137 138static void 139lqasc_stop_tx(struct uart_port *port) 140{ 141 return; 142} 143 144static void 145lqasc_start_tx(struct uart_port *port) 146{ 147 unsigned long flags; 148 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 149 150 spin_lock_irqsave(<q_port->lock, flags); 151 lqasc_tx_chars(port); 152 spin_unlock_irqrestore(<q_port->lock, flags); 153 return; 154} 155 156static void 157lqasc_stop_rx(struct uart_port *port) 158{ 159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 160} 161 162static int 163lqasc_rx_chars(struct uart_port *port) 164{ 165 struct tty_port *tport = &port->state->port; 166 unsigned int ch = 0, rsr = 0, fifocnt; 167 168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 169 ASCFSTAT_RXFFLMASK; 170 while (fifocnt--) { 171 u8 flag = TTY_NORMAL; 172 ch = readb(port->membase + LTQ_ASC_RBUF); 173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 174 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 175 tty_flip_buffer_push(tport); 176 port->icount.rx++; 177 178 /* 179 * Note that the error handling code is 180 * out of the main execution path 181 */ 182 if (rsr & ASCSTATE_ANY) { 183 if (rsr & ASCSTATE_PE) { 184 port->icount.parity++; 185 asc_update_bits(0, ASCWHBSTATE_CLRPE, 186 port->membase + LTQ_ASC_WHBSTATE); 187 } else if (rsr & ASCSTATE_FE) { 188 port->icount.frame++; 189 asc_update_bits(0, ASCWHBSTATE_CLRFE, 190 port->membase + LTQ_ASC_WHBSTATE); 191 } 192 if (rsr & ASCSTATE_ROE) { 193 port->icount.overrun++; 194 asc_update_bits(0, ASCWHBSTATE_CLRROE, 195 port->membase + LTQ_ASC_WHBSTATE); 196 } 197 198 rsr &= port->read_status_mask; 199 200 if (rsr & ASCSTATE_PE) 201 flag = TTY_PARITY; 202 else if (rsr & ASCSTATE_FE) 203 flag = TTY_FRAME; 204 } 205 206 if ((rsr & port->ignore_status_mask) == 0) 207 tty_insert_flip_char(tport, ch, flag); 208 209 if (rsr & ASCSTATE_ROE) 210 /* 211 * Overrun is special, since it's reported 212 * immediately, and doesn't affect the current 213 * character 214 */ 215 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 216 } 217 218 if (ch != 0) 219 tty_flip_buffer_push(tport); 220 221 return 0; 222} 223 224static void 225lqasc_tx_chars(struct uart_port *port) 226{ 227 struct circ_buf *xmit = &port->state->xmit; 228 if (uart_tx_stopped(port)) { 229 lqasc_stop_tx(port); 230 return; 231 } 232 233 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & 234 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { 235 if (port->x_char) { 236 writeb(port->x_char, port->membase + LTQ_ASC_TBUF); 237 port->icount.tx++; 238 port->x_char = 0; 239 continue; 240 } 241 242 if (uart_circ_empty(xmit)) 243 break; 244 245 writeb(port->state->xmit.buf[port->state->xmit.tail], 246 port->membase + LTQ_ASC_TBUF); 247 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 248 port->icount.tx++; 249 } 250 251 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 252 uart_write_wakeup(port); 253} 254 255static irqreturn_t 256lqasc_tx_int(int irq, void *_port) 257{ 258 unsigned long flags; 259 struct uart_port *port = (struct uart_port *)_port; 260 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 261 262 spin_lock_irqsave(<q_port->lock, flags); 263 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 264 spin_unlock_irqrestore(<q_port->lock, flags); 265 lqasc_start_tx(port); 266 return IRQ_HANDLED; 267} 268 269static irqreturn_t 270lqasc_err_int(int irq, void *_port) 271{ 272 unsigned long flags; 273 struct uart_port *port = (struct uart_port *)_port; 274 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 275 276 spin_lock_irqsave(<q_port->lock, flags); 277 __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR); 278 /* clear any pending interrupts */ 279 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 280 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 281 spin_unlock_irqrestore(<q_port->lock, flags); 282 return IRQ_HANDLED; 283} 284 285static irqreturn_t 286lqasc_rx_int(int irq, void *_port) 287{ 288 unsigned long flags; 289 struct uart_port *port = (struct uart_port *)_port; 290 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 291 292 spin_lock_irqsave(<q_port->lock, flags); 293 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 294 lqasc_rx_chars(port); 295 spin_unlock_irqrestore(<q_port->lock, flags); 296 return IRQ_HANDLED; 297} 298 299static irqreturn_t lqasc_irq(int irq, void *p) 300{ 301 unsigned long flags; 302 u32 stat; 303 struct uart_port *port = p; 304 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 305 306 spin_lock_irqsave(<q_port->lock, flags); 307 stat = readl(port->membase + LTQ_ASC_IRNCR); 308 spin_unlock_irqrestore(<q_port->lock, flags); 309 if (!(stat & ASC_IRNCR_MASK)) 310 return IRQ_NONE; 311 312 if (stat & ASC_IRNCR_TIR) 313 lqasc_tx_int(irq, p); 314 315 if (stat & ASC_IRNCR_RIR) 316 lqasc_rx_int(irq, p); 317 318 if (stat & ASC_IRNCR_EIR) 319 lqasc_err_int(irq, p); 320 321 return IRQ_HANDLED; 322} 323 324static unsigned int 325lqasc_tx_empty(struct uart_port *port) 326{ 327 int status; 328 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 329 ASCFSTAT_TXFFLMASK; 330 return status ? 0 : TIOCSER_TEMT; 331} 332 333static unsigned int 334lqasc_get_mctrl(struct uart_port *port) 335{ 336 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 337} 338 339static void 340lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 341{ 342} 343 344static void 345lqasc_break_ctl(struct uart_port *port, int break_state) 346{ 347} 348 349static int 350lqasc_startup(struct uart_port *port) 351{ 352 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 353 int retval; 354 unsigned long flags; 355 356 if (!IS_ERR(ltq_port->clk)) 357 clk_prepare_enable(ltq_port->clk); 358 port->uartclk = clk_get_rate(ltq_port->freqclk); 359 360 spin_lock_irqsave(<q_port->lock, flags); 361 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 362 port->membase + LTQ_ASC_CLC); 363 364 __raw_writel(0, port->membase + LTQ_ASC_PISEL); 365 __raw_writel( 366 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 367 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 368 port->membase + LTQ_ASC_TXFCON); 369 __raw_writel( 370 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 371 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 372 port->membase + LTQ_ASC_RXFCON); 373 /* make sure other settings are written to hardware before 374 * setting enable bits 375 */ 376 wmb(); 377 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 378 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 379 380 spin_unlock_irqrestore(<q_port->lock, flags); 381 382 retval = ltq_port->soc->request_irq(port); 383 if (retval) 384 return retval; 385 386 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 387 port->membase + LTQ_ASC_IRNREN); 388 return retval; 389} 390 391static void 392lqasc_shutdown(struct uart_port *port) 393{ 394 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 395 unsigned long flags; 396 397 ltq_port->soc->free_irq(port); 398 399 spin_lock_irqsave(<q_port->lock, flags); 400 __raw_writel(0, port->membase + LTQ_ASC_CON); 401 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 402 port->membase + LTQ_ASC_RXFCON); 403 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 404 port->membase + LTQ_ASC_TXFCON); 405 spin_unlock_irqrestore(<q_port->lock, flags); 406 if (!IS_ERR(ltq_port->clk)) 407 clk_disable_unprepare(ltq_port->clk); 408} 409 410static void 411lqasc_set_termios(struct uart_port *port, 412 struct ktermios *new, struct ktermios *old) 413{ 414 unsigned int cflag; 415 unsigned int iflag; 416 unsigned int divisor; 417 unsigned int baud; 418 unsigned int con = 0; 419 unsigned long flags; 420 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 421 422 cflag = new->c_cflag; 423 iflag = new->c_iflag; 424 425 switch (cflag & CSIZE) { 426 case CS7: 427 con = ASCCON_M_7ASYNC; 428 break; 429 430 case CS5: 431 case CS6: 432 default: 433 new->c_cflag &= ~ CSIZE; 434 new->c_cflag |= CS8; 435 con = ASCCON_M_8ASYNC; 436 break; 437 } 438 439 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 440 441 if (cflag & CSTOPB) 442 con |= ASCCON_STP; 443 444 if (cflag & PARENB) { 445 if (!(cflag & PARODD)) 446 con &= ~ASCCON_ODD; 447 else 448 con |= ASCCON_ODD; 449 } 450 451 port->read_status_mask = ASCSTATE_ROE; 452 if (iflag & INPCK) 453 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 454 455 port->ignore_status_mask = 0; 456 if (iflag & IGNPAR) 457 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 458 459 if (iflag & IGNBRK) { 460 /* 461 * If we're ignoring parity and break indicators, 462 * ignore overruns too (for real raw support). 463 */ 464 if (iflag & IGNPAR) 465 port->ignore_status_mask |= ASCSTATE_ROE; 466 } 467 468 if ((cflag & CREAD) == 0) 469 port->ignore_status_mask |= UART_DUMMY_UER_RX; 470 471 /* set error signals - framing, parity and overrun, enable receiver */ 472 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 473 474 spin_lock_irqsave(<q_port->lock, flags); 475 476 /* set up CON */ 477 asc_update_bits(0, con, port->membase + LTQ_ASC_CON); 478 479 /* Set baud rate - take a divider of 2 into account */ 480 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 481 divisor = uart_get_divisor(port, baud); 482 divisor = divisor / 2 - 1; 483 484 /* disable the baudrate generator */ 485 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 486 487 /* make sure the fractional divider is off */ 488 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 489 490 /* set up to use divisor of 2 */ 491 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 492 493 /* now we can write the new baudrate into the register */ 494 __raw_writel(divisor, port->membase + LTQ_ASC_BG); 495 496 /* turn the baudrate generator back on */ 497 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); 498 499 /* enable rx */ 500 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 501 502 spin_unlock_irqrestore(<q_port->lock, flags); 503 504 /* Don't rewrite B0 */ 505 if (tty_termios_baud_rate(new)) 506 tty_termios_encode_baud_rate(new, baud, baud); 507 508 uart_update_timeout(port, cflag, baud); 509} 510 511static const char* 512lqasc_type(struct uart_port *port) 513{ 514 if (port->type == PORT_LTQ_ASC) 515 return DRVNAME; 516 else 517 return NULL; 518} 519 520static void 521lqasc_release_port(struct uart_port *port) 522{ 523 struct platform_device *pdev = to_platform_device(port->dev); 524 525 if (port->flags & UPF_IOREMAP) { 526 devm_iounmap(&pdev->dev, port->membase); 527 port->membase = NULL; 528 } 529} 530 531static int 532lqasc_request_port(struct uart_port *port) 533{ 534 struct platform_device *pdev = to_platform_device(port->dev); 535 struct resource *res; 536 int size; 537 538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 539 if (!res) { 540 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 541 return -ENODEV; 542 } 543 size = resource_size(res); 544 545 res = devm_request_mem_region(&pdev->dev, res->start, 546 size, dev_name(&pdev->dev)); 547 if (!res) { 548 dev_err(&pdev->dev, "cannot request I/O memory region"); 549 return -EBUSY; 550 } 551 552 if (port->flags & UPF_IOREMAP) { 553 port->membase = devm_ioremap(&pdev->dev, 554 port->mapbase, size); 555 if (port->membase == NULL) 556 return -ENOMEM; 557 } 558 return 0; 559} 560 561static void 562lqasc_config_port(struct uart_port *port, int flags) 563{ 564 if (flags & UART_CONFIG_TYPE) { 565 port->type = PORT_LTQ_ASC; 566 lqasc_request_port(port); 567 } 568} 569 570static int 571lqasc_verify_port(struct uart_port *port, 572 struct serial_struct *ser) 573{ 574 int ret = 0; 575 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 576 ret = -EINVAL; 577 if (ser->irq < 0 || ser->irq >= NR_IRQS) 578 ret = -EINVAL; 579 if (ser->baud_base < 9600) 580 ret = -EINVAL; 581 return ret; 582} 583 584static const struct uart_ops lqasc_pops = { 585 .tx_empty = lqasc_tx_empty, 586 .set_mctrl = lqasc_set_mctrl, 587 .get_mctrl = lqasc_get_mctrl, 588 .stop_tx = lqasc_stop_tx, 589 .start_tx = lqasc_start_tx, 590 .stop_rx = lqasc_stop_rx, 591 .break_ctl = lqasc_break_ctl, 592 .startup = lqasc_startup, 593 .shutdown = lqasc_shutdown, 594 .set_termios = lqasc_set_termios, 595 .type = lqasc_type, 596 .release_port = lqasc_release_port, 597 .request_port = lqasc_request_port, 598 .config_port = lqasc_config_port, 599 .verify_port = lqasc_verify_port, 600}; 601 602#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE 603static void 604lqasc_console_putchar(struct uart_port *port, int ch) 605{ 606 int fifofree; 607 608 if (!port->membase) 609 return; 610 611 do { 612 fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) 613 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; 614 } while (fifofree == 0); 615 writeb(ch, port->membase + LTQ_ASC_TBUF); 616} 617 618static void lqasc_serial_port_write(struct uart_port *port, const char *s, 619 u_int count) 620{ 621 uart_console_write(port, s, count, lqasc_console_putchar); 622} 623 624static void 625lqasc_console_write(struct console *co, const char *s, u_int count) 626{ 627 struct ltq_uart_port *ltq_port; 628 unsigned long flags; 629 630 if (co->index >= MAXPORTS) 631 return; 632 633 ltq_port = lqasc_port[co->index]; 634 if (!ltq_port) 635 return; 636 637 spin_lock_irqsave(<q_port->lock, flags); 638 lqasc_serial_port_write(<q_port->port, s, count); 639 spin_unlock_irqrestore(<q_port->lock, flags); 640} 641 642static int __init 643lqasc_console_setup(struct console *co, char *options) 644{ 645 struct ltq_uart_port *ltq_port; 646 struct uart_port *port; 647 int baud = 115200; 648 int bits = 8; 649 int parity = 'n'; 650 int flow = 'n'; 651 652 if (co->index >= MAXPORTS) 653 return -ENODEV; 654 655 ltq_port = lqasc_port[co->index]; 656 if (!ltq_port) 657 return -ENODEV; 658 659 port = <q_port->port; 660 661 if (!IS_ERR(ltq_port->clk)) 662 clk_prepare_enable(ltq_port->clk); 663 664 port->uartclk = clk_get_rate(ltq_port->freqclk); 665 666 if (options) 667 uart_parse_options(options, &baud, &parity, &bits, &flow); 668 return uart_set_options(port, co, baud, parity, bits, flow); 669} 670 671static struct console lqasc_console = { 672 .name = "ttyLTQ", 673 .write = lqasc_console_write, 674 .device = uart_console_device, 675 .setup = lqasc_console_setup, 676 .flags = CON_PRINTBUFFER, 677 .index = -1, 678 .data = &lqasc_reg, 679}; 680 681static int __init 682lqasc_console_init(void) 683{ 684 register_console(&lqasc_console); 685 return 0; 686} 687console_initcall(lqasc_console_init); 688 689static void lqasc_serial_early_console_write(struct console *co, 690 const char *s, 691 u_int count) 692{ 693 struct earlycon_device *dev = co->data; 694 695 lqasc_serial_port_write(&dev->port, s, count); 696} 697 698static int __init 699lqasc_serial_early_console_setup(struct earlycon_device *device, 700 const char *opt) 701{ 702 if (!device->port.membase) 703 return -ENODEV; 704 705 device->con->write = lqasc_serial_early_console_write; 706 return 0; 707} 708OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup); 709OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup); 710 711#define LANTIQ_SERIAL_CONSOLE (&lqasc_console) 712 713#else 714 715#define LANTIQ_SERIAL_CONSOLE NULL 716 717#endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ 718 719static struct uart_driver lqasc_reg = { 720 .owner = THIS_MODULE, 721 .driver_name = DRVNAME, 722 .dev_name = "ttyLTQ", 723 .major = 0, 724 .minor = 0, 725 .nr = MAXPORTS, 726 .cons = LANTIQ_SERIAL_CONSOLE, 727}; 728 729static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) 730{ 731 struct uart_port *port = <q_port->port; 732 struct resource irqres[3]; 733 int ret; 734 735 ret = of_irq_to_resource_table(dev->of_node, irqres, 3); 736 if (ret != 3) { 737 dev_err(dev, 738 "failed to get IRQs for serial port\n"); 739 return -ENODEV; 740 } 741 ltq_port->tx_irq = irqres[0].start; 742 ltq_port->rx_irq = irqres[1].start; 743 ltq_port->err_irq = irqres[2].start; 744 port->irq = irqres[0].start; 745 746 return 0; 747} 748 749static int request_irq_lantiq(struct uart_port *port) 750{ 751 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 752 int retval; 753 754 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 755 0, "asc_tx", port); 756 if (retval) { 757 dev_err(port->dev, "failed to request asc_tx\n"); 758 return retval; 759 } 760 761 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 762 0, "asc_rx", port); 763 if (retval) { 764 dev_err(port->dev, "failed to request asc_rx\n"); 765 goto err1; 766 } 767 768 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 769 0, "asc_err", port); 770 if (retval) { 771 dev_err(port->dev, "failed to request asc_err\n"); 772 goto err2; 773 } 774 return 0; 775 776err2: 777 free_irq(ltq_port->rx_irq, port); 778err1: 779 free_irq(ltq_port->tx_irq, port); 780 return retval; 781} 782 783static void free_irq_lantiq(struct uart_port *port) 784{ 785 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 786 787 free_irq(ltq_port->tx_irq, port); 788 free_irq(ltq_port->rx_irq, port); 789 free_irq(ltq_port->err_irq, port); 790} 791 792static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port) 793{ 794 struct uart_port *port = <q_port->port; 795 int ret; 796 797 ret = of_irq_get(dev->of_node, 0); 798 if (ret < 0) { 799 dev_err(dev, "failed to fetch IRQ for serial port\n"); 800 return ret; 801 } 802 ltq_port->common_irq = ret; 803 port->irq = ret; 804 805 return 0; 806} 807 808static int request_irq_intel(struct uart_port *port) 809{ 810 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 811 int retval; 812 813 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0, 814 "asc_irq", port); 815 if (retval) 816 dev_err(port->dev, "failed to request asc_irq\n"); 817 818 return retval; 819} 820 821static void free_irq_intel(struct uart_port *port) 822{ 823 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 824 825 free_irq(ltq_port->common_irq, port); 826} 827 828static int lqasc_probe(struct platform_device *pdev) 829{ 830 struct device_node *node = pdev->dev.of_node; 831 struct ltq_uart_port *ltq_port; 832 struct uart_port *port; 833 struct resource *mmres; 834 int line; 835 int ret; 836 837 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 838 if (!mmres) { 839 dev_err(&pdev->dev, 840 "failed to get memory for serial port\n"); 841 return -ENODEV; 842 } 843 844 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 845 GFP_KERNEL); 846 if (!ltq_port) 847 return -ENOMEM; 848 849 port = <q_port->port; 850 851 ltq_port->soc = of_device_get_match_data(&pdev->dev); 852 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port); 853 if (ret) 854 return ret; 855 856 /* get serial id */ 857 line = of_alias_get_id(node, "serial"); 858 if (line < 0) { 859 if (IS_ENABLED(CONFIG_LANTIQ)) { 860 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) 861 line = 0; 862 else 863 line = 1; 864 } else { 865 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 866 line); 867 return line; 868 } 869 } 870 871 if (lqasc_port[line]) { 872 dev_err(&pdev->dev, "port %d already allocated\n", line); 873 return -EBUSY; 874 } 875 876 port->iotype = SERIAL_IO_MEM; 877 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 878 port->ops = &lqasc_pops; 879 port->fifosize = 16; 880 port->type = PORT_LTQ_ASC, 881 port->line = line; 882 port->dev = &pdev->dev; 883 /* unused, just to be backward-compatible */ 884 port->mapbase = mmres->start; 885 886 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 887 ltq_port->freqclk = clk_get_fpi(); 888 else 889 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq"); 890 891 892 if (IS_ERR(ltq_port->freqclk)) { 893 pr_err("failed to get fpi clk\n"); 894 return -ENOENT; 895 } 896 897 /* not all asc ports have clock gates, lets ignore the return code */ 898 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 899 ltq_port->clk = clk_get(&pdev->dev, NULL); 900 else 901 ltq_port->clk = devm_clk_get(&pdev->dev, "asc"); 902 903 spin_lock_init(<q_port->lock); 904 lqasc_port[line] = ltq_port; 905 platform_set_drvdata(pdev, ltq_port); 906 907 ret = uart_add_one_port(&lqasc_reg, port); 908 909 return ret; 910} 911 912static int lqasc_remove(struct platform_device *pdev) 913{ 914 struct uart_port *port = platform_get_drvdata(pdev); 915 916 return uart_remove_one_port(&lqasc_reg, port); 917} 918 919static const struct ltq_soc_data soc_data_lantiq = { 920 .fetch_irq = fetch_irq_lantiq, 921 .request_irq = request_irq_lantiq, 922 .free_irq = free_irq_lantiq, 923}; 924 925static const struct ltq_soc_data soc_data_intel = { 926 .fetch_irq = fetch_irq_intel, 927 .request_irq = request_irq_intel, 928 .free_irq = free_irq_intel, 929}; 930 931static const struct of_device_id ltq_asc_match[] = { 932 { .compatible = "lantiq,asc", .data = &soc_data_lantiq }, 933 { .compatible = "intel,lgm-asc", .data = &soc_data_intel }, 934 {}, 935}; 936MODULE_DEVICE_TABLE(of, ltq_asc_match); 937 938static struct platform_driver lqasc_driver = { 939 .probe = lqasc_probe, 940 .remove = lqasc_remove, 941 .driver = { 942 .name = DRVNAME, 943 .of_match_table = ltq_asc_match, 944 }, 945}; 946 947static int __init 948init_lqasc(void) 949{ 950 int ret; 951 952 ret = uart_register_driver(&lqasc_reg); 953 if (ret != 0) 954 return ret; 955 956 ret = platform_driver_register(&lqasc_driver); 957 if (ret != 0) 958 uart_unregister_driver(&lqasc_reg); 959 960 return ret; 961} 962 963static void __exit exit_lqasc(void) 964{ 965 platform_driver_unregister(&lqasc_driver); 966 uart_unregister_driver(&lqasc_reg); 967} 968 969module_init(init_lqasc); 970module_exit(exit_lqasc); 971 972MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs"); 973MODULE_LICENSE("GPL v2"); 974