1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Zilog serial chips found on SGI workstations and 4 * servers. This driver could actually be made more generic. 5 * 6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the 7 * old drivers/sgi/char/sgiserial.c code which itself is based of the original 8 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over 9 * directly from there but much has been rewritten. Credits therefore go out 10 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell 11 * for their work there. 12 * 13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) 14 * Copyright (C) 2002 David S. Miller (davem@redhat.com) 15 */ 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/errno.h> 19#include <linux/delay.h> 20#include <linux/tty.h> 21#include <linux/tty_flip.h> 22#include <linux/major.h> 23#include <linux/string.h> 24#include <linux/ptrace.h> 25#include <linux/ioport.h> 26#include <linux/slab.h> 27#include <linux/circ_buf.h> 28#include <linux/serial.h> 29#include <linux/sysrq.h> 30#include <linux/console.h> 31#include <linux/spinlock.h> 32#include <linux/init.h> 33 34#include <asm/io.h> 35#include <asm/irq.h> 36#include <asm/sgialib.h> 37#include <asm/sgi/ioc.h> 38#include <asm/sgi/hpc3.h> 39#include <asm/sgi/ip22.h> 40 41#include <linux/serial_core.h> 42 43#include "ip22zilog.h" 44 45/* 46 * On IP22 we need to delay after register accesses but we do not need to 47 * flush writes. 48 */ 49#define ZSDELAY() udelay(5) 50#define ZSDELAY_LONG() udelay(20) 51#define ZS_WSYNC(channel) do { } while (0) 52 53#define NUM_IP22ZILOG 1 54#define NUM_CHANNELS (NUM_IP22ZILOG * 2) 55 56#define ZS_CLOCK 3672000 /* Zilog input clock rate. */ 57#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ 58 59/* 60 * We wrap our port structure around the generic uart_port. 61 */ 62struct uart_ip22zilog_port { 63 struct uart_port port; 64 65 /* IRQ servicing chain. */ 66 struct uart_ip22zilog_port *next; 67 68 /* Current values of Zilog write registers. */ 69 unsigned char curregs[NUM_ZSREGS]; 70 71 unsigned int flags; 72#define IP22ZILOG_FLAG_IS_CONS 0x00000004 73#define IP22ZILOG_FLAG_IS_KGDB 0x00000008 74#define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 75#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 76#define IP22ZILOG_FLAG_REGS_HELD 0x00000040 77#define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 78#define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 79#define IP22ZILOG_FLAG_RESET_DONE 0x00000200 80 81 unsigned int tty_break; 82 83 unsigned char parity_mask; 84 unsigned char prev_status; 85}; 86 87#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) 88#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) 89#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ 90 (UART_ZILOG(PORT)->curregs[REGNUM]) 91#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ 92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) 93#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) 94#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) 95#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) 96#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) 97#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) 98#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) 99#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) 100 101/* Reading and writing Zilog8530 registers. The delays are to make this 102 * driver work on the IP22 which needs a settling delay after each chip 103 * register access, other machines handle this in hardware via auxiliary 104 * flip-flops which implement the settle time we do in software. 105 * 106 * The port lock must be held and local IRQs must be disabled 107 * when {read,write}_zsreg is invoked. 108 */ 109static unsigned char read_zsreg(struct zilog_channel *channel, 110 unsigned char reg) 111{ 112 unsigned char retval; 113 114 writeb(reg, &channel->control); 115 ZSDELAY(); 116 retval = readb(&channel->control); 117 ZSDELAY(); 118 119 return retval; 120} 121 122static void write_zsreg(struct zilog_channel *channel, 123 unsigned char reg, unsigned char value) 124{ 125 writeb(reg, &channel->control); 126 ZSDELAY(); 127 writeb(value, &channel->control); 128 ZSDELAY(); 129} 130 131static void ip22zilog_clear_fifo(struct zilog_channel *channel) 132{ 133 int i; 134 135 for (i = 0; i < 32; i++) { 136 unsigned char regval; 137 138 regval = readb(&channel->control); 139 ZSDELAY(); 140 if (regval & Rx_CH_AV) 141 break; 142 143 regval = read_zsreg(channel, R1); 144 readb(&channel->data); 145 ZSDELAY(); 146 147 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { 148 writeb(ERR_RES, &channel->control); 149 ZSDELAY(); 150 ZS_WSYNC(channel); 151 } 152 } 153} 154 155/* This function must only be called when the TX is not busy. The UART 156 * port lock must be held and local interrupts disabled. 157 */ 158static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) 159{ 160 int i; 161 162 /* Let pending transmits finish. */ 163 for (i = 0; i < 1000; i++) { 164 unsigned char stat = read_zsreg(channel, R1); 165 if (stat & ALL_SNT) 166 break; 167 udelay(100); 168 } 169 170 writeb(ERR_RES, &channel->control); 171 ZSDELAY(); 172 ZS_WSYNC(channel); 173 174 ip22zilog_clear_fifo(channel); 175 176 /* Disable all interrupts. */ 177 write_zsreg(channel, R1, 178 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 179 180 /* Set parity, sync config, stop bits, and clock divisor. */ 181 write_zsreg(channel, R4, regs[R4]); 182 183 /* Set misc. TX/RX control bits. */ 184 write_zsreg(channel, R10, regs[R10]); 185 186 /* Set TX/RX controls sans the enable bits. */ 187 write_zsreg(channel, R3, regs[R3] & ~RxENAB); 188 write_zsreg(channel, R5, regs[R5] & ~TxENAB); 189 190 /* Synchronous mode config. */ 191 write_zsreg(channel, R6, regs[R6]); 192 write_zsreg(channel, R7, regs[R7]); 193 194 /* Don't mess with the interrupt vector (R2, unused by us) and 195 * master interrupt control (R9). We make sure this is setup 196 * properly at probe time then never touch it again. 197 */ 198 199 /* Disable baud generator. */ 200 write_zsreg(channel, R14, regs[R14] & ~BRENAB); 201 202 /* Clock mode control. */ 203 write_zsreg(channel, R11, regs[R11]); 204 205 /* Lower and upper byte of baud rate generator divisor. */ 206 write_zsreg(channel, R12, regs[R12]); 207 write_zsreg(channel, R13, regs[R13]); 208 209 /* Now rewrite R14, with BRENAB (if set). */ 210 write_zsreg(channel, R14, regs[R14]); 211 212 /* External status interrupt control. */ 213 write_zsreg(channel, R15, regs[R15]); 214 215 /* Reset external status interrupts. */ 216 write_zsreg(channel, R0, RES_EXT_INT); 217 write_zsreg(channel, R0, RES_EXT_INT); 218 219 /* Rewrite R3/R5, this time without enables masked. */ 220 write_zsreg(channel, R3, regs[R3]); 221 write_zsreg(channel, R5, regs[R5]); 222 223 /* Rewrite R1, this time without IRQ enabled masked. */ 224 write_zsreg(channel, R1, regs[R1]); 225} 226 227/* Reprogram the Zilog channel HW registers with the copies found in the 228 * software state struct. If the transmitter is busy, we defer this update 229 * until the next TX complete interrupt. Else, we do it right now. 230 * 231 * The UART port lock must be held and local interrupts disabled. 232 */ 233static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, 234 struct zilog_channel *channel) 235{ 236 if (!ZS_REGS_HELD(up)) { 237 if (ZS_TX_ACTIVE(up)) { 238 up->flags |= IP22ZILOG_FLAG_REGS_HELD; 239 } else { 240 __load_zsregs(channel, up->curregs); 241 } 242 } 243} 244 245#define Rx_BRK 0x0100 /* BREAK event software flag. */ 246#define Rx_SYS 0x0200 /* SysRq event software flag. */ 247 248static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up, 249 struct zilog_channel *channel) 250{ 251 unsigned char ch, flag; 252 unsigned int r1; 253 bool push = up->port.state != NULL; 254 255 for (;;) { 256 ch = readb(&channel->control); 257 ZSDELAY(); 258 if (!(ch & Rx_CH_AV)) 259 break; 260 261 r1 = read_zsreg(channel, R1); 262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 263 writeb(ERR_RES, &channel->control); 264 ZSDELAY(); 265 ZS_WSYNC(channel); 266 } 267 268 ch = readb(&channel->data); 269 ZSDELAY(); 270 271 ch &= up->parity_mask; 272 273 /* Handle the null char got when BREAK is removed. */ 274 if (!ch) 275 r1 |= up->tty_break; 276 277 /* A real serial line, record the character and status. */ 278 flag = TTY_NORMAL; 279 up->port.icount.rx++; 280 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) { 281 up->tty_break = 0; 282 283 if (r1 & (Rx_SYS | Rx_BRK)) { 284 up->port.icount.brk++; 285 if (r1 & Rx_SYS) 286 continue; 287 r1 &= ~(PAR_ERR | CRC_ERR); 288 } 289 else if (r1 & PAR_ERR) 290 up->port.icount.parity++; 291 else if (r1 & CRC_ERR) 292 up->port.icount.frame++; 293 if (r1 & Rx_OVR) 294 up->port.icount.overrun++; 295 r1 &= up->port.read_status_mask; 296 if (r1 & Rx_BRK) 297 flag = TTY_BREAK; 298 else if (r1 & PAR_ERR) 299 flag = TTY_PARITY; 300 else if (r1 & CRC_ERR) 301 flag = TTY_FRAME; 302 } 303 304 if (uart_handle_sysrq_char(&up->port, ch)) 305 continue; 306 307 if (push) 308 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag); 309 } 310 return push; 311} 312 313static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, 314 struct zilog_channel *channel) 315{ 316 unsigned char status; 317 318 status = readb(&channel->control); 319 ZSDELAY(); 320 321 writeb(RES_EXT_INT, &channel->control); 322 ZSDELAY(); 323 ZS_WSYNC(channel); 324 325 if (up->curregs[R15] & BRKIE) { 326 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) { 327 if (uart_handle_break(&up->port)) 328 up->tty_break = Rx_SYS; 329 else 330 up->tty_break = Rx_BRK; 331 } 332 } 333 334 if (ZS_WANTS_MODEM_STATUS(up)) { 335 if (status & SYNC) 336 up->port.icount.dsr++; 337 338 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 339 * But it does not tell us which bit has changed, we have to keep 340 * track of this ourselves. 341 */ 342 if ((status ^ up->prev_status) ^ DCD) 343 uart_handle_dcd_change(&up->port, 344 (status & DCD)); 345 if ((status ^ up->prev_status) ^ CTS) 346 uart_handle_cts_change(&up->port, 347 (status & CTS)); 348 349 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 350 } 351 352 up->prev_status = status; 353} 354 355static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, 356 struct zilog_channel *channel) 357{ 358 struct circ_buf *xmit; 359 360 if (ZS_IS_CONS(up)) { 361 unsigned char status = readb(&channel->control); 362 ZSDELAY(); 363 364 /* TX still busy? Just wait for the next TX done interrupt. 365 * 366 * It can occur because of how we do serial console writes. It would 367 * be nice to transmit console writes just like we normally would for 368 * a TTY line. (ie. buffered and TX interrupt driven). That is not 369 * easy because console writes cannot sleep. One solution might be 370 * to poll on enough port->xmit space becoming free. -DaveM 371 */ 372 if (!(status & Tx_BUF_EMP)) 373 return; 374 } 375 376 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; 377 378 if (ZS_REGS_HELD(up)) { 379 __load_zsregs(channel, up->curregs); 380 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; 381 } 382 383 if (ZS_TX_STOPPED(up)) { 384 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; 385 goto ack_tx_int; 386 } 387 388 if (up->port.x_char) { 389 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 390 writeb(up->port.x_char, &channel->data); 391 ZSDELAY(); 392 ZS_WSYNC(channel); 393 394 up->port.icount.tx++; 395 up->port.x_char = 0; 396 return; 397 } 398 399 if (up->port.state == NULL) 400 goto ack_tx_int; 401 xmit = &up->port.state->xmit; 402 if (uart_circ_empty(xmit)) 403 goto ack_tx_int; 404 if (uart_tx_stopped(&up->port)) 405 goto ack_tx_int; 406 407 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 408 writeb(xmit->buf[xmit->tail], &channel->data); 409 ZSDELAY(); 410 ZS_WSYNC(channel); 411 412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 413 up->port.icount.tx++; 414 415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 416 uart_write_wakeup(&up->port); 417 418 return; 419 420ack_tx_int: 421 writeb(RES_Tx_P, &channel->control); 422 ZSDELAY(); 423 ZS_WSYNC(channel); 424} 425 426static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) 427{ 428 struct uart_ip22zilog_port *up = dev_id; 429 430 while (up) { 431 struct zilog_channel *channel 432 = ZILOG_CHANNEL_FROM_PORT(&up->port); 433 unsigned char r3; 434 bool push = false; 435 436 spin_lock(&up->port.lock); 437 r3 = read_zsreg(channel, R3); 438 439 /* Channel A */ 440 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 441 writeb(RES_H_IUS, &channel->control); 442 ZSDELAY(); 443 ZS_WSYNC(channel); 444 445 if (r3 & CHARxIP) 446 push = ip22zilog_receive_chars(up, channel); 447 if (r3 & CHAEXT) 448 ip22zilog_status_handle(up, channel); 449 if (r3 & CHATxIP) 450 ip22zilog_transmit_chars(up, channel); 451 } 452 spin_unlock(&up->port.lock); 453 454 if (push) 455 tty_flip_buffer_push(&up->port.state->port); 456 457 /* Channel B */ 458 up = up->next; 459 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 460 push = false; 461 462 spin_lock(&up->port.lock); 463 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 464 writeb(RES_H_IUS, &channel->control); 465 ZSDELAY(); 466 ZS_WSYNC(channel); 467 468 if (r3 & CHBRxIP) 469 push = ip22zilog_receive_chars(up, channel); 470 if (r3 & CHBEXT) 471 ip22zilog_status_handle(up, channel); 472 if (r3 & CHBTxIP) 473 ip22zilog_transmit_chars(up, channel); 474 } 475 spin_unlock(&up->port.lock); 476 477 if (push) 478 tty_flip_buffer_push(&up->port.state->port); 479 480 up = up->next; 481 } 482 483 return IRQ_HANDLED; 484} 485 486/* A convenient way to quickly get R0 status. The caller must _not_ hold the 487 * port lock, it is acquired here. 488 */ 489static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) 490{ 491 struct zilog_channel *channel; 492 unsigned char status; 493 494 channel = ZILOG_CHANNEL_FROM_PORT(port); 495 status = readb(&channel->control); 496 ZSDELAY(); 497 498 return status; 499} 500 501/* The port lock is not held. */ 502static unsigned int ip22zilog_tx_empty(struct uart_port *port) 503{ 504 unsigned long flags; 505 unsigned char status; 506 unsigned int ret; 507 508 spin_lock_irqsave(&port->lock, flags); 509 510 status = ip22zilog_read_channel_status(port); 511 512 spin_unlock_irqrestore(&port->lock, flags); 513 514 if (status & Tx_BUF_EMP) 515 ret = TIOCSER_TEMT; 516 else 517 ret = 0; 518 519 return ret; 520} 521 522/* The port lock is held and interrupts are disabled. */ 523static unsigned int ip22zilog_get_mctrl(struct uart_port *port) 524{ 525 unsigned char status; 526 unsigned int ret; 527 528 status = ip22zilog_read_channel_status(port); 529 530 ret = 0; 531 if (status & DCD) 532 ret |= TIOCM_CAR; 533 if (status & SYNC) 534 ret |= TIOCM_DSR; 535 if (status & CTS) 536 ret |= TIOCM_CTS; 537 538 return ret; 539} 540 541/* The port lock is held and interrupts are disabled. */ 542static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) 543{ 544 struct uart_ip22zilog_port *up = 545 container_of(port, struct uart_ip22zilog_port, port); 546 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 547 unsigned char set_bits, clear_bits; 548 549 set_bits = clear_bits = 0; 550 551 if (mctrl & TIOCM_RTS) 552 set_bits |= RTS; 553 else 554 clear_bits |= RTS; 555 if (mctrl & TIOCM_DTR) 556 set_bits |= DTR; 557 else 558 clear_bits |= DTR; 559 560 /* NOTE: Not subject to 'transmitter active' rule. */ 561 up->curregs[R5] |= set_bits; 562 up->curregs[R5] &= ~clear_bits; 563 write_zsreg(channel, R5, up->curregs[R5]); 564} 565 566/* The port lock is held and interrupts are disabled. */ 567static void ip22zilog_stop_tx(struct uart_port *port) 568{ 569 struct uart_ip22zilog_port *up = 570 container_of(port, struct uart_ip22zilog_port, port); 571 572 up->flags |= IP22ZILOG_FLAG_TX_STOPPED; 573} 574 575/* The port lock is held and interrupts are disabled. */ 576static void ip22zilog_start_tx(struct uart_port *port) 577{ 578 struct uart_ip22zilog_port *up = 579 container_of(port, struct uart_ip22zilog_port, port); 580 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 581 unsigned char status; 582 583 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 584 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; 585 586 status = readb(&channel->control); 587 ZSDELAY(); 588 589 /* TX busy? Just wait for the TX done interrupt. */ 590 if (!(status & Tx_BUF_EMP)) 591 return; 592 593 /* Send the first character to jump-start the TX done 594 * IRQ sending engine. 595 */ 596 if (port->x_char) { 597 writeb(port->x_char, &channel->data); 598 ZSDELAY(); 599 ZS_WSYNC(channel); 600 601 port->icount.tx++; 602 port->x_char = 0; 603 } else { 604 struct circ_buf *xmit = &port->state->xmit; 605 606 if (uart_circ_empty(xmit)) 607 return; 608 writeb(xmit->buf[xmit->tail], &channel->data); 609 ZSDELAY(); 610 ZS_WSYNC(channel); 611 612 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 613 port->icount.tx++; 614 615 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 616 uart_write_wakeup(&up->port); 617 } 618} 619 620/* The port lock is held and interrupts are disabled. */ 621static void ip22zilog_stop_rx(struct uart_port *port) 622{ 623 struct uart_ip22zilog_port *up = UART_ZILOG(port); 624 struct zilog_channel *channel; 625 626 if (ZS_IS_CONS(up)) 627 return; 628 629 channel = ZILOG_CHANNEL_FROM_PORT(port); 630 631 /* Disable all RX interrupts. */ 632 up->curregs[R1] &= ~RxINT_MASK; 633 ip22zilog_maybe_update_regs(up, channel); 634} 635 636/* The port lock is held. */ 637static void ip22zilog_enable_ms(struct uart_port *port) 638{ 639 struct uart_ip22zilog_port *up = 640 container_of(port, struct uart_ip22zilog_port, port); 641 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 642 unsigned char new_reg; 643 644 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 645 if (new_reg != up->curregs[R15]) { 646 up->curregs[R15] = new_reg; 647 648 /* NOTE: Not subject to 'transmitter active' rule. */ 649 write_zsreg(channel, R15, up->curregs[R15]); 650 } 651} 652 653/* The port lock is not held. */ 654static void ip22zilog_break_ctl(struct uart_port *port, int break_state) 655{ 656 struct uart_ip22zilog_port *up = 657 container_of(port, struct uart_ip22zilog_port, port); 658 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 659 unsigned char set_bits, clear_bits, new_reg; 660 unsigned long flags; 661 662 set_bits = clear_bits = 0; 663 664 if (break_state) 665 set_bits |= SND_BRK; 666 else 667 clear_bits |= SND_BRK; 668 669 spin_lock_irqsave(&port->lock, flags); 670 671 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; 672 if (new_reg != up->curregs[R5]) { 673 up->curregs[R5] = new_reg; 674 675 /* NOTE: Not subject to 'transmitter active' rule. */ 676 write_zsreg(channel, R5, up->curregs[R5]); 677 } 678 679 spin_unlock_irqrestore(&port->lock, flags); 680} 681 682static void __ip22zilog_reset(struct uart_ip22zilog_port *up) 683{ 684 struct zilog_channel *channel; 685 int i; 686 687 if (up->flags & IP22ZILOG_FLAG_RESET_DONE) 688 return; 689 690 /* Let pending transmits finish. */ 691 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 692 for (i = 0; i < 1000; i++) { 693 unsigned char stat = read_zsreg(channel, R1); 694 if (stat & ALL_SNT) 695 break; 696 udelay(100); 697 } 698 699 if (!ZS_IS_CHANNEL_A(up)) { 700 up++; 701 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 702 } 703 write_zsreg(channel, R9, FHWRES); 704 ZSDELAY_LONG(); 705 (void) read_zsreg(channel, R0); 706 707 up->flags |= IP22ZILOG_FLAG_RESET_DONE; 708 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE; 709} 710 711static void __ip22zilog_startup(struct uart_ip22zilog_port *up) 712{ 713 struct zilog_channel *channel; 714 715 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 716 717 __ip22zilog_reset(up); 718 719 __load_zsregs(channel, up->curregs); 720 /* set master interrupt enable */ 721 write_zsreg(channel, R9, up->curregs[R9]); 722 up->prev_status = readb(&channel->control); 723 724 /* Enable receiver and transmitter. */ 725 up->curregs[R3] |= RxENAB; 726 up->curregs[R5] |= TxENAB; 727 728 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 729 ip22zilog_maybe_update_regs(up, channel); 730} 731 732static int ip22zilog_startup(struct uart_port *port) 733{ 734 struct uart_ip22zilog_port *up = UART_ZILOG(port); 735 unsigned long flags; 736 737 if (ZS_IS_CONS(up)) 738 return 0; 739 740 spin_lock_irqsave(&port->lock, flags); 741 __ip22zilog_startup(up); 742 spin_unlock_irqrestore(&port->lock, flags); 743 return 0; 744} 745 746/* 747 * The test for ZS_IS_CONS is explained by the following e-mail: 748 ***** 749 * From: Russell King <rmk@arm.linux.org.uk> 750 * Date: Sun, 8 Dec 2002 10:18:38 +0000 751 * 752 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: 753 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, 754 * > and I noticed that something is not right with reference 755 * > counting in this case. It seems that when the console 756 * > is open by kernel initially, this is not accounted 757 * > as an open, and uart_startup is not called. 758 * 759 * That is correct. We are unable to call uart_startup when the serial 760 * console is initialised because it may need to allocate memory (as 761 * request_irq does) and the memory allocators may not have been 762 * initialised. 763 * 764 * 1. initialise the port into a state where it can send characters in the 765 * console write method. 766 * 767 * 2. don't do the actual hardware shutdown in your shutdown() method (but 768 * do the normal software shutdown - ie, free irqs etc) 769 ***** 770 */ 771static void ip22zilog_shutdown(struct uart_port *port) 772{ 773 struct uart_ip22zilog_port *up = UART_ZILOG(port); 774 struct zilog_channel *channel; 775 unsigned long flags; 776 777 if (ZS_IS_CONS(up)) 778 return; 779 780 spin_lock_irqsave(&port->lock, flags); 781 782 channel = ZILOG_CHANNEL_FROM_PORT(port); 783 784 /* Disable receiver and transmitter. */ 785 up->curregs[R3] &= ~RxENAB; 786 up->curregs[R5] &= ~TxENAB; 787 788 /* Disable all interrupts and BRK assertion. */ 789 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 790 up->curregs[R5] &= ~SND_BRK; 791 ip22zilog_maybe_update_regs(up, channel); 792 793 spin_unlock_irqrestore(&port->lock, flags); 794} 795 796/* Shared by TTY driver and serial console setup. The port lock is held 797 * and local interrupts are disabled. 798 */ 799static void 800ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, 801 unsigned int iflag, int brg) 802{ 803 804 up->curregs[R10] = NRZ; 805 up->curregs[R11] = TCBR | RCBR; 806 807 /* Program BAUD and clock source. */ 808 up->curregs[R4] &= ~XCLK_MASK; 809 up->curregs[R4] |= X16CLK; 810 up->curregs[R12] = brg & 0xff; 811 up->curregs[R13] = (brg >> 8) & 0xff; 812 up->curregs[R14] = BRENAB; 813 814 /* Character size, stop bits, and parity. */ 815 up->curregs[3] &= ~RxN_MASK; 816 up->curregs[5] &= ~TxN_MASK; 817 switch (cflag & CSIZE) { 818 case CS5: 819 up->curregs[3] |= Rx5; 820 up->curregs[5] |= Tx5; 821 up->parity_mask = 0x1f; 822 break; 823 case CS6: 824 up->curregs[3] |= Rx6; 825 up->curregs[5] |= Tx6; 826 up->parity_mask = 0x3f; 827 break; 828 case CS7: 829 up->curregs[3] |= Rx7; 830 up->curregs[5] |= Tx7; 831 up->parity_mask = 0x7f; 832 break; 833 case CS8: 834 default: 835 up->curregs[3] |= Rx8; 836 up->curregs[5] |= Tx8; 837 up->parity_mask = 0xff; 838 break; 839 } 840 up->curregs[4] &= ~0x0c; 841 if (cflag & CSTOPB) 842 up->curregs[4] |= SB2; 843 else 844 up->curregs[4] |= SB1; 845 if (cflag & PARENB) 846 up->curregs[4] |= PAR_ENAB; 847 else 848 up->curregs[4] &= ~PAR_ENAB; 849 if (!(cflag & PARODD)) 850 up->curregs[4] |= PAR_EVEN; 851 else 852 up->curregs[4] &= ~PAR_EVEN; 853 854 up->port.read_status_mask = Rx_OVR; 855 if (iflag & INPCK) 856 up->port.read_status_mask |= CRC_ERR | PAR_ERR; 857 if (iflag & (IGNBRK | BRKINT | PARMRK)) 858 up->port.read_status_mask |= BRK_ABRT; 859 860 up->port.ignore_status_mask = 0; 861 if (iflag & IGNPAR) 862 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 863 if (iflag & IGNBRK) { 864 up->port.ignore_status_mask |= BRK_ABRT; 865 if (iflag & IGNPAR) 866 up->port.ignore_status_mask |= Rx_OVR; 867 } 868 869 if ((cflag & CREAD) == 0) 870 up->port.ignore_status_mask = 0xff; 871} 872 873/* The port lock is not held. */ 874static void 875ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, 876 struct ktermios *old) 877{ 878 struct uart_ip22zilog_port *up = 879 container_of(port, struct uart_ip22zilog_port, port); 880 unsigned long flags; 881 int baud, brg; 882 883 baud = uart_get_baud_rate(port, termios, old, 1200, 76800); 884 885 spin_lock_irqsave(&up->port.lock, flags); 886 887 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 888 889 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); 890 891 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 892 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; 893 else 894 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; 895 896 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); 897 uart_update_timeout(port, termios->c_cflag, baud); 898 899 spin_unlock_irqrestore(&up->port.lock, flags); 900} 901 902static const char *ip22zilog_type(struct uart_port *port) 903{ 904 return "IP22-Zilog"; 905} 906 907/* We do not request/release mappings of the registers here, this 908 * happens at early serial probe time. 909 */ 910static void ip22zilog_release_port(struct uart_port *port) 911{ 912} 913 914static int ip22zilog_request_port(struct uart_port *port) 915{ 916 return 0; 917} 918 919/* These do not need to do anything interesting either. */ 920static void ip22zilog_config_port(struct uart_port *port, int flags) 921{ 922} 923 924/* We do not support letting the user mess with the divisor, IRQ, etc. */ 925static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) 926{ 927 return -EINVAL; 928} 929 930static const struct uart_ops ip22zilog_pops = { 931 .tx_empty = ip22zilog_tx_empty, 932 .set_mctrl = ip22zilog_set_mctrl, 933 .get_mctrl = ip22zilog_get_mctrl, 934 .stop_tx = ip22zilog_stop_tx, 935 .start_tx = ip22zilog_start_tx, 936 .stop_rx = ip22zilog_stop_rx, 937 .enable_ms = ip22zilog_enable_ms, 938 .break_ctl = ip22zilog_break_ctl, 939 .startup = ip22zilog_startup, 940 .shutdown = ip22zilog_shutdown, 941 .set_termios = ip22zilog_set_termios, 942 .type = ip22zilog_type, 943 .release_port = ip22zilog_release_port, 944 .request_port = ip22zilog_request_port, 945 .config_port = ip22zilog_config_port, 946 .verify_port = ip22zilog_verify_port, 947}; 948 949static struct uart_ip22zilog_port *ip22zilog_port_table; 950static struct zilog_layout **ip22zilog_chip_regs; 951 952static struct uart_ip22zilog_port *ip22zilog_irq_chain; 953static int zilog_irq = -1; 954 955static void * __init alloc_one_table(unsigned long size) 956{ 957 return kzalloc(size, GFP_KERNEL); 958} 959 960static void __init ip22zilog_alloc_tables(void) 961{ 962 ip22zilog_port_table = (struct uart_ip22zilog_port *) 963 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); 964 ip22zilog_chip_regs = (struct zilog_layout **) 965 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); 966 967 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { 968 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); 969 } 970} 971 972/* Get the address of the registers for IP22-Zilog instance CHIP. */ 973static struct zilog_layout * __init get_zs(int chip) 974{ 975 unsigned long base; 976 977 if (chip < 0 || chip >= NUM_IP22ZILOG) { 978 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); 979 } 980 981 /* Not probe-able, hard code it. */ 982 base = (unsigned long) &sgioc->uart; 983 984 zilog_irq = SGI_SERIAL_IRQ; 985 request_mem_region(base, 8, "IP22-Zilog"); 986 987 return (struct zilog_layout *) base; 988} 989 990#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ 991 992#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE 993static void ip22zilog_put_char(struct uart_port *port, int ch) 994{ 995 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 996 int loops = ZS_PUT_CHAR_MAX_DELAY; 997 998 /* This is a timed polling loop so do not switch the explicit 999 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM 1000 */ 1001 do { 1002 unsigned char val = readb(&channel->control); 1003 if (val & Tx_BUF_EMP) { 1004 ZSDELAY(); 1005 break; 1006 } 1007 udelay(5); 1008 } while (--loops); 1009 1010 writeb(ch, &channel->data); 1011 ZSDELAY(); 1012 ZS_WSYNC(channel); 1013} 1014 1015static void 1016ip22zilog_console_write(struct console *con, const char *s, unsigned int count) 1017{ 1018 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; 1019 unsigned long flags; 1020 1021 spin_lock_irqsave(&up->port.lock, flags); 1022 uart_console_write(&up->port, s, count, ip22zilog_put_char); 1023 udelay(2); 1024 spin_unlock_irqrestore(&up->port.lock, flags); 1025} 1026 1027static int __init ip22zilog_console_setup(struct console *con, char *options) 1028{ 1029 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; 1030 unsigned long flags; 1031 int baud = 9600, bits = 8; 1032 int parity = 'n'; 1033 int flow = 'n'; 1034 1035 up->flags |= IP22ZILOG_FLAG_IS_CONS; 1036 1037 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index); 1038 1039 spin_lock_irqsave(&up->port.lock, flags); 1040 1041 up->curregs[R15] |= BRKIE; 1042 1043 __ip22zilog_startup(up); 1044 1045 spin_unlock_irqrestore(&up->port.lock, flags); 1046 1047 if (options) 1048 uart_parse_options(options, &baud, &parity, &bits, &flow); 1049 return uart_set_options(&up->port, con, baud, parity, bits, flow); 1050} 1051 1052static struct uart_driver ip22zilog_reg; 1053 1054static struct console ip22zilog_console = { 1055 .name = "ttyS", 1056 .write = ip22zilog_console_write, 1057 .device = uart_console_device, 1058 .setup = ip22zilog_console_setup, 1059 .flags = CON_PRINTBUFFER, 1060 .index = -1, 1061 .data = &ip22zilog_reg, 1062}; 1063#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ 1064 1065static struct uart_driver ip22zilog_reg = { 1066 .owner = THIS_MODULE, 1067 .driver_name = "serial", 1068 .dev_name = "ttyS", 1069 .major = TTY_MAJOR, 1070 .minor = 64, 1071 .nr = NUM_CHANNELS, 1072#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE 1073 .cons = &ip22zilog_console, 1074#endif 1075}; 1076 1077static void __init ip22zilog_prepare(void) 1078{ 1079 unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE); 1080 struct uart_ip22zilog_port *up; 1081 struct zilog_layout *rp; 1082 int channel, chip; 1083 1084 /* 1085 * Temporary fix. 1086 */ 1087 for (channel = 0; channel < NUM_CHANNELS; channel++) 1088 spin_lock_init(&ip22zilog_port_table[channel].port.lock); 1089 1090 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; 1091 up = &ip22zilog_port_table[0]; 1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) 1093 up[channel].next = &up[channel - 1]; 1094 up[channel].next = NULL; 1095 1096 for (chip = 0; chip < NUM_IP22ZILOG; chip++) { 1097 if (!ip22zilog_chip_regs[chip]) { 1098 ip22zilog_chip_regs[chip] = rp = get_zs(chip); 1099 1100 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; 1101 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; 1102 1103 /* In theory mapbase is the physical address ... */ 1104 up[(chip * 2) + 0].port.mapbase = 1105 (unsigned long) ioremap((unsigned long) &rp->channelB, 8); 1106 up[(chip * 2) + 1].port.mapbase = 1107 (unsigned long) ioremap((unsigned long) &rp->channelA, 8); 1108 } 1109 1110 /* Channel A */ 1111 up[(chip * 2) + 0].port.iotype = UPIO_MEM; 1112 up[(chip * 2) + 0].port.irq = zilog_irq; 1113 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; 1114 up[(chip * 2) + 0].port.fifosize = 1; 1115 up[(chip * 2) + 0].port.has_sysrq = sysrq_on; 1116 up[(chip * 2) + 0].port.ops = &ip22zilog_pops; 1117 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; 1118 up[(chip * 2) + 0].port.flags = 0; 1119 up[(chip * 2) + 0].port.line = (chip * 2) + 0; 1120 up[(chip * 2) + 0].flags = 0; 1121 1122 /* Channel B */ 1123 up[(chip * 2) + 1].port.iotype = UPIO_MEM; 1124 up[(chip * 2) + 1].port.irq = zilog_irq; 1125 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; 1126 up[(chip * 2) + 1].port.fifosize = 1; 1127 up[(chip * 2) + 1].port.has_sysrq = sysrq_on; 1128 up[(chip * 2) + 1].port.ops = &ip22zilog_pops; 1129 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; 1130 up[(chip * 2) + 1].port.line = (chip * 2) + 1; 1131 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; 1132 } 1133 1134 for (channel = 0; channel < NUM_CHANNELS; channel++) { 1135 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; 1136 int brg; 1137 1138 /* Normal serial TTY. */ 1139 up->parity_mask = 0xff; 1140 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 1141 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; 1142 up->curregs[R3] = RxENAB | Rx8; 1143 up->curregs[R5] = TxENAB | Tx8; 1144 up->curregs[R9] = NV | MIE; 1145 up->curregs[R10] = NRZ; 1146 up->curregs[R11] = TCBR | RCBR; 1147 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1148 up->curregs[R12] = (brg & 0xff); 1149 up->curregs[R13] = (brg >> 8) & 0xff; 1150 up->curregs[R14] = BRENAB; 1151 } 1152} 1153 1154static int __init ip22zilog_ports_init(void) 1155{ 1156 int ret; 1157 1158 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); 1159 1160 ip22zilog_prepare(); 1161 1162 if (request_irq(zilog_irq, ip22zilog_interrupt, 0, 1163 "IP22-Zilog", ip22zilog_irq_chain)) { 1164 panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); 1165 } 1166 1167 ret = uart_register_driver(&ip22zilog_reg); 1168 if (ret == 0) { 1169 int i; 1170 1171 for (i = 0; i < NUM_CHANNELS; i++) { 1172 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; 1173 1174 uart_add_one_port(&ip22zilog_reg, &up->port); 1175 } 1176 } 1177 1178 return ret; 1179} 1180 1181static int __init ip22zilog_init(void) 1182{ 1183 /* IP22 Zilog setup is hard coded, no probing to do. */ 1184 ip22zilog_alloc_tables(); 1185 ip22zilog_ports_init(); 1186 1187 return 0; 1188} 1189 1190static void __exit ip22zilog_exit(void) 1191{ 1192 int i; 1193 struct uart_ip22zilog_port *up; 1194 1195 for (i = 0; i < NUM_CHANNELS; i++) { 1196 up = &ip22zilog_port_table[i]; 1197 1198 uart_remove_one_port(&ip22zilog_reg, &up->port); 1199 } 1200 1201 /* Free IO mem */ 1202 up = &ip22zilog_port_table[0]; 1203 for (i = 0; i < NUM_IP22ZILOG; i++) { 1204 if (up[(i * 2) + 0].port.mapbase) { 1205 iounmap((void*)up[(i * 2) + 0].port.mapbase); 1206 up[(i * 2) + 0].port.mapbase = 0; 1207 } 1208 if (up[(i * 2) + 1].port.mapbase) { 1209 iounmap((void*)up[(i * 2) + 1].port.mapbase); 1210 up[(i * 2) + 1].port.mapbase = 0; 1211 } 1212 } 1213 1214 uart_unregister_driver(&ip22zilog_reg); 1215} 1216 1217module_init(ip22zilog_init); 1218module_exit(ip22zilog_exit); 1219 1220/* David wrote it but I'm to blame for the bugs ... */ 1221MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 1222MODULE_DESCRIPTION("SGI Zilog serial port driver"); 1223MODULE_LICENSE("GPL"); 1224