1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9#undef DEBUG 10#include <linux/module.h> 11#include <linux/pci.h> 12#include <linux/string.h> 13#include <linux/kernel.h> 14#include <linux/slab.h> 15#include <linux/delay.h> 16#include <linux/tty.h> 17#include <linux/serial_reg.h> 18#include <linux/serial_core.h> 19#include <linux/8250_pci.h> 20#include <linux/bitops.h> 21 22#include <asm/byteorder.h> 23#include <asm/io.h> 24 25#include "8250.h" 26 27/* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44}; 45 46struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49}; 50 51struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57}; 58 59#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 60 61static const struct pci_device_id pci_use_msi[] = { 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 69 PCI_ANY_ID, PCI_ANY_ID) }, 70 { } 71}; 72 73static int pci_default_setup(struct serial_private*, 74 const struct pciserial_board*, struct uart_8250_port *, int); 75 76static void moan_device(const char *str, struct pci_dev *dev) 77{ 78 pci_err(dev, "%s\n" 79 "Please send the output of lspci -vv, this\n" 80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 81 "manufacturer and name of serial board or\n" 82 "modem board to <linux-serial@vger.kernel.org>.\n", 83 str, dev->vendor, dev->device, 84 dev->subsystem_vendor, dev->subsystem_device); 85} 86 87static int 88setup_port(struct serial_private *priv, struct uart_8250_port *port, 89 u8 bar, unsigned int offset, int regshift) 90{ 91 struct pci_dev *dev = priv->dev; 92 93 if (bar >= PCI_STD_NUM_BARS) 94 return -EINVAL; 95 96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 98 return -ENOMEM; 99 100 port->port.iotype = UPIO_MEM; 101 port->port.iobase = 0; 102 port->port.mapbase = pci_resource_start(dev, bar) + offset; 103 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 104 port->port.regshift = regshift; 105 } else { 106 port->port.iotype = UPIO_PORT; 107 port->port.iobase = pci_resource_start(dev, bar) + offset; 108 port->port.mapbase = 0; 109 port->port.membase = NULL; 110 port->port.regshift = 0; 111 } 112 return 0; 113} 114 115/* 116 * ADDI-DATA GmbH communication cards <info@addi-data.com> 117 */ 118static int addidata_apci7800_setup(struct serial_private *priv, 119 const struct pciserial_board *board, 120 struct uart_8250_port *port, int idx) 121{ 122 unsigned int bar = 0, offset = board->first_offset; 123 bar = FL_GET_BASE(board->flags); 124 125 if (idx < 2) { 126 offset += idx * board->uart_offset; 127 } else if ((idx >= 2) && (idx < 4)) { 128 bar += 1; 129 offset += ((idx - 2) * board->uart_offset); 130 } else if ((idx >= 4) && (idx < 6)) { 131 bar += 2; 132 offset += ((idx - 4) * board->uart_offset); 133 } else if (idx >= 6) { 134 bar += 3; 135 offset += ((idx - 6) * board->uart_offset); 136 } 137 138 return setup_port(priv, port, bar, offset, board->reg_shift); 139} 140 141/* 142 * AFAVLAB uses a different mixture of BARs and offsets 143 * Not that ugly ;) -- HW 144 */ 145static int 146afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 147 struct uart_8250_port *port, int idx) 148{ 149 unsigned int bar, offset = board->first_offset; 150 151 bar = FL_GET_BASE(board->flags); 152 if (idx < 4) 153 bar += idx; 154 else { 155 bar = 4; 156 offset += (idx - 4) * board->uart_offset; 157 } 158 159 return setup_port(priv, port, bar, offset, board->reg_shift); 160} 161 162/* 163 * HP's Remote Management Console. The Diva chip came in several 164 * different versions. N-class, L2000 and A500 have two Diva chips, each 165 * with 3 UARTs (the third UART on the second chip is unused). Superdome 166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 167 * one Diva chip, but it has been expanded to 5 UARTs. 168 */ 169static int pci_hp_diva_init(struct pci_dev *dev) 170{ 171 int rc = 0; 172 173 switch (dev->subsystem_device) { 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 177 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 178 rc = 3; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 181 rc = 2; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 184 rc = 4; 185 break; 186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 188 rc = 1; 189 break; 190 } 191 192 return rc; 193} 194 195/* 196 * HP's Diva chip puts the 4th/5th serial port further out, and 197 * some serial ports are supposed to be hidden on certain models. 198 */ 199static int 200pci_hp_diva_setup(struct serial_private *priv, 201 const struct pciserial_board *board, 202 struct uart_8250_port *port, int idx) 203{ 204 unsigned int offset = board->first_offset; 205 unsigned int bar = FL_GET_BASE(board->flags); 206 207 switch (priv->dev->subsystem_device) { 208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 209 if (idx == 3) 210 idx++; 211 break; 212 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 213 if (idx > 0) 214 idx++; 215 if (idx > 2) 216 idx++; 217 break; 218 } 219 if (idx > 2) 220 offset = 0x18; 221 222 offset += idx * board->uart_offset; 223 224 return setup_port(priv, port, bar, offset, board->reg_shift); 225} 226 227/* 228 * Added for EKF Intel i960 serial boards 229 */ 230static int pci_inteli960ni_init(struct pci_dev *dev) 231{ 232 u32 oldval; 233 234 if (!(dev->subsystem_device & 0x1000)) 235 return -ENODEV; 236 237 /* is firmware started? */ 238 pci_read_config_dword(dev, 0x44, &oldval); 239 if (oldval == 0x00001000L) { /* RESET value */ 240 pci_dbg(dev, "Local i960 firmware missing\n"); 241 return -ENODEV; 242 } 243 return 0; 244} 245 246/* 247 * Some PCI serial cards using the PLX 9050 PCI interface chip require 248 * that the card interrupt be explicitly enabled or disabled. This 249 * seems to be mainly needed on card using the PLX which also use I/O 250 * mapped memory. 251 */ 252static int pci_plx9050_init(struct pci_dev *dev) 253{ 254 u8 irq_config; 255 void __iomem *p; 256 257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 258 moan_device("no memory in bar 0", dev); 259 return 0; 260 } 261 262 irq_config = 0x41; 263 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 265 irq_config = 0x43; 266 267 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 269 /* 270 * As the megawolf cards have the int pins active 271 * high, and have 2 UART chips, both ints must be 272 * enabled on the 9050. Also, the UARTS are set in 273 * 16450 mode by default, so we have to enable the 274 * 16C950 'enhanced' mode so that we can use the 275 * deep FIFOs 276 */ 277 irq_config = 0x5b; 278 /* 279 * enable/disable interrupts 280 */ 281 p = ioremap(pci_resource_start(dev, 0), 0x80); 282 if (p == NULL) 283 return -ENOMEM; 284 writel(irq_config, p + 0x4c); 285 286 /* 287 * Read the register back to ensure that it took effect. 288 */ 289 readl(p + 0x4c); 290 iounmap(p); 291 292 return 0; 293} 294 295static void pci_plx9050_exit(struct pci_dev *dev) 296{ 297 u8 __iomem *p; 298 299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 300 return; 301 302 /* 303 * disable interrupts 304 */ 305 p = ioremap(pci_resource_start(dev, 0), 0x80); 306 if (p != NULL) { 307 writel(0, p + 0x4c); 308 309 /* 310 * Read the register back to ensure that it took effect. 311 */ 312 readl(p + 0x4c); 313 iounmap(p); 314 } 315} 316 317#define NI8420_INT_ENABLE_REG 0x38 318#define NI8420_INT_ENABLE_BIT 0x2000 319 320static void pci_ni8420_exit(struct pci_dev *dev) 321{ 322 void __iomem *p; 323 unsigned int bar = 0; 324 325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 326 moan_device("no memory in bar", dev); 327 return; 328 } 329 330 p = pci_ioremap_bar(dev, bar); 331 if (p == NULL) 332 return; 333 334 /* Disable the CPU Interrupt */ 335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 336 p + NI8420_INT_ENABLE_REG); 337 iounmap(p); 338} 339 340 341/* MITE registers */ 342#define MITE_IOWBSR1 0xc4 343#define MITE_IOWCR1 0xf4 344#define MITE_LCIMR1 0x08 345#define MITE_LCIMR2 0x10 346 347#define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 348 349static void pci_ni8430_exit(struct pci_dev *dev) 350{ 351 void __iomem *p; 352 unsigned int bar = 0; 353 354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 355 moan_device("no memory in bar", dev); 356 return; 357 } 358 359 p = pci_ioremap_bar(dev, bar); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366} 367 368/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369static int 370sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372{ 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387} 388 389/* 390* This does initialization for PMC OCTALPRO cards: 391* maps the device memory, resets the UARTs (needed, bc 392* if the module is removed and inserted again, the card 393* is in the sleep mode) and enables global interrupt. 394*/ 395 396/* global control register offset for SBS PMC-OctalPro */ 397#define OCT_REG_CR_OFF 0x500 398 399static int sbs_init(struct pci_dev *dev) 400{ 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417} 418 419/* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423static void sbs_exit(struct pci_dev *dev) 424{ 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432} 433 434/* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464static int pci_siig10x_init(struct pci_dev *dev) 465{ 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489} 490 491#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494static int pci_siig20x_init(struct pci_dev *dev) 495{ 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509} 510 511static int pci_siig_init(struct pci_dev *dev) 512{ 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 else if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522} 523 524static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527{ 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536} 537 538/* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545}; 546 547static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553}; 554 555static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560}; 561 562static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565}; 566 567static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570} timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575}; 576 577/* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583static int pci_timedia_probe(struct pci_dev *dev) 584{ 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 591 dev->subsystem_device); 592 return -ENODEV; 593 } 594 595 return 0; 596} 597 598static int pci_timedia_init(struct pci_dev *dev) 599{ 600 const unsigned short *ids; 601 int i, j; 602 603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 604 ids = timedia_data[i].ids; 605 for (j = 0; ids[j]; j++) 606 if (dev->subsystem_device == ids[j]) 607 return timedia_data[i].num; 608 } 609 return 0; 610} 611 612/* 613 * Timedia/SUNIX uses a mixture of BARs and offsets 614 * Ugh, this is ugly as all hell --- TYT 615 */ 616static int 617pci_timedia_setup(struct serial_private *priv, 618 const struct pciserial_board *board, 619 struct uart_8250_port *port, int idx) 620{ 621 unsigned int bar = 0, offset = board->first_offset; 622 623 switch (idx) { 624 case 0: 625 bar = 0; 626 break; 627 case 1: 628 offset = board->uart_offset; 629 bar = 0; 630 break; 631 case 2: 632 bar = 1; 633 break; 634 case 3: 635 offset = board->uart_offset; 636 fallthrough; 637 case 4: /* BAR 2 */ 638 case 5: /* BAR 3 */ 639 case 6: /* BAR 4 */ 640 case 7: /* BAR 5 */ 641 bar = idx - 2; 642 } 643 644 return setup_port(priv, port, bar, offset, board->reg_shift); 645} 646 647/* 648 * Some Titan cards are also a little weird 649 */ 650static int 651titan_400l_800l_setup(struct serial_private *priv, 652 const struct pciserial_board *board, 653 struct uart_8250_port *port, int idx) 654{ 655 unsigned int bar, offset = board->first_offset; 656 657 switch (idx) { 658 case 0: 659 bar = 1; 660 break; 661 case 1: 662 bar = 2; 663 break; 664 default: 665 bar = 4; 666 offset = (idx - 2) * board->uart_offset; 667 } 668 669 return setup_port(priv, port, bar, offset, board->reg_shift); 670} 671 672static int pci_xircom_init(struct pci_dev *dev) 673{ 674 msleep(100); 675 return 0; 676} 677 678static int pci_ni8420_init(struct pci_dev *dev) 679{ 680 void __iomem *p; 681 unsigned int bar = 0; 682 683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 684 moan_device("no memory in bar", dev); 685 return 0; 686 } 687 688 p = pci_ioremap_bar(dev, bar); 689 if (p == NULL) 690 return -ENOMEM; 691 692 /* Enable CPU Interrupt */ 693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 694 p + NI8420_INT_ENABLE_REG); 695 696 iounmap(p); 697 return 0; 698} 699 700#define MITE_IOWBSR1_WSIZE 0xa 701#define MITE_IOWBSR1_WIN_OFFSET 0x800 702#define MITE_IOWBSR1_WENAB (1 << 7) 703#define MITE_LCIMR1_IO_IE_0 (1 << 24) 704#define MITE_LCIMR2_SET_CPU_IE (1 << 31) 705#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 706 707static int pci_ni8430_init(struct pci_dev *dev) 708{ 709 void __iomem *p; 710 struct pci_bus_region region; 711 u32 device_window; 712 unsigned int bar = 0; 713 714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 715 moan_device("no memory in bar", dev); 716 return 0; 717 } 718 719 p = pci_ioremap_bar(dev, bar); 720 if (p == NULL) 721 return -ENOMEM; 722 723 /* 724 * Set device window address and size in BAR0, while acknowledging that 725 * the resource structure may contain a translated address that differs 726 * from the address the device responds to. 727 */ 728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 731 writel(device_window, p + MITE_IOWBSR1); 732 733 /* Set window access to go to RAMSEL IO address space */ 734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 735 p + MITE_IOWCR1); 736 737 /* Enable IO Bus Interrupt 0 */ 738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 739 740 /* Enable CPU Interrupt */ 741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 742 743 iounmap(p); 744 return 0; 745} 746 747/* UART Port Control Register */ 748#define NI8430_PORTCON 0x0f 749#define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 750 751static int 752pci_ni8430_setup(struct serial_private *priv, 753 const struct pciserial_board *board, 754 struct uart_8250_port *port, int idx) 755{ 756 struct pci_dev *dev = priv->dev; 757 void __iomem *p; 758 unsigned int bar, offset = board->first_offset; 759 760 if (idx >= board->num_ports) 761 return 1; 762 763 bar = FL_GET_BASE(board->flags); 764 offset += idx * board->uart_offset; 765 766 p = pci_ioremap_bar(dev, bar); 767 if (!p) 768 return -ENOMEM; 769 770 /* enable the transceiver */ 771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 772 p + offset + NI8430_PORTCON); 773 774 iounmap(p); 775 776 return setup_port(priv, port, bar, offset, board->reg_shift); 777} 778 779static int pci_netmos_9900_setup(struct serial_private *priv, 780 const struct pciserial_board *board, 781 struct uart_8250_port *port, int idx) 782{ 783 unsigned int bar; 784 785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 786 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 787 /* netmos apparently orders BARs by datasheet layout, so serial 788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 789 */ 790 bar = 3 * idx; 791 792 return setup_port(priv, port, bar, 0, board->reg_shift); 793 } else { 794 return pci_default_setup(priv, board, port, idx); 795 } 796} 797 798/* the 99xx series comes with a range of device IDs and a variety 799 * of capabilities: 800 * 801 * 9900 has varying capabilities and can cascade to sub-controllers 802 * (cascading should be purely internal) 803 * 9904 is hardwired with 4 serial ports 804 * 9912 and 9922 are hardwired with 2 serial ports 805 */ 806static int pci_netmos_9900_numports(struct pci_dev *dev) 807{ 808 unsigned int c = dev->class; 809 unsigned int pi; 810 unsigned short sub_serports; 811 812 pi = c & 0xff; 813 814 if (pi == 2) 815 return 1; 816 817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 818 /* two possibilities: 0x30ps encodes number of parallel and 819 * serial ports, or 0x1000 indicates *something*. This is not 820 * immediately obvious, since the 2s1p+4s configuration seems 821 * to offer all functionality on functions 0..2, while still 822 * advertising the same function 3 as the 4s+2s1p config. 823 */ 824 sub_serports = dev->subsystem_device & 0xf; 825 if (sub_serports > 0) 826 return sub_serports; 827 828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 829 return 0; 830 } 831 832 moan_device("unknown NetMos/Mostech program interface", dev); 833 return 0; 834} 835 836static int pci_netmos_init(struct pci_dev *dev) 837{ 838 /* subdevice 0x00PS means <P> parallel, <S> serial */ 839 unsigned int num_serial = dev->subsystem_device & 0xf; 840 841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 842 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 843 return 0; 844 845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 846 dev->subsystem_device == 0x0299) 847 return 0; 848 849 switch (dev->device) { /* FALLTHROUGH on all */ 850 case PCI_DEVICE_ID_NETMOS_9904: 851 case PCI_DEVICE_ID_NETMOS_9912: 852 case PCI_DEVICE_ID_NETMOS_9922: 853 case PCI_DEVICE_ID_NETMOS_9900: 854 num_serial = pci_netmos_9900_numports(dev); 855 break; 856 857 default: 858 break; 859 } 860 861 if (num_serial == 0) { 862 moan_device("unknown NetMos/Mostech device", dev); 863 return -ENODEV; 864 } 865 866 return num_serial; 867} 868 869/* 870 * These chips are available with optionally one parallel port and up to 871 * two serial ports. Unfortunately they all have the same product id. 872 * 873 * Basic configuration is done over a region of 32 I/O ports. The base 874 * ioport is called INTA or INTC, depending on docs/other drivers. 875 * 876 * The region of the 32 I/O ports is configured in POSIO0R... 877 */ 878 879/* registers */ 880#define ITE_887x_MISCR 0x9c 881#define ITE_887x_INTCBAR 0x78 882#define ITE_887x_UARTBAR 0x7c 883#define ITE_887x_PS0BAR 0x10 884#define ITE_887x_POSIO0 0x60 885 886/* I/O space size */ 887#define ITE_887x_IOSIZE 32 888/* I/O space size (bits 26-24; 8 bytes = 011b) */ 889#define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 890/* I/O space size (bits 26-24; 32 bytes = 101b) */ 891#define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 892/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 893#define ITE_887x_POSIO_SPEED (3 << 29) 894/* enable IO_Space bit */ 895#define ITE_887x_POSIO_ENABLE (1 << 31) 896 897/* inta_addr are the configuration addresses of the ITE */ 898static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 899static int pci_ite887x_init(struct pci_dev *dev) 900{ 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 908 "ite887x"); 909 if (iobase != NULL) { 910 /* write POSIO0R - speed | size | ioport */ 911 pci_write_config_dword(dev, ITE_887x_POSIO0, 912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 914 /* write INTCBAR - ioport */ 915 pci_write_config_dword(dev, ITE_887x_INTCBAR, 916 inta_addr[i]); 917 ret = inb(inta_addr[i]); 918 if (ret != 0xff) { 919 /* ioport connected */ 920 break; 921 } 922 release_region(iobase->start, ITE_887x_IOSIZE); 923 } 924 } 925 926 if (i == ARRAY_SIZE(inta_addr)) { 927 pci_err(dev, "could not find iobase\n"); 928 return -ENODEV; 929 } 930 931 /* start of undocumented type checking (see parport_pc.c) */ 932 type = inb(iobase->start + 0x18) & 0x0f; 933 934 switch (type) { 935 case 0x2: /* ITE8871 (1P) */ 936 case 0xa: /* ITE8875 (1P) */ 937 ret = 0; 938 break; 939 case 0xe: /* ITE8872 (2S1P) */ 940 ret = 2; 941 break; 942 case 0x6: /* ITE8873 (1S) */ 943 ret = 1; 944 break; 945 case 0x8: /* ITE8874 (2S) */ 946 ret = 2; 947 break; 948 default: 949 moan_device("Unknown ITE887x", dev); 950 ret = -ENODEV; 951 } 952 953 /* configure all serial ports */ 954 for (i = 0; i < ret; i++) { 955 /* read the I/O port from the device */ 956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 957 &ioport); 958 ioport &= 0x0000FF00; /* the actual base address */ 959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 961 ITE_887x_POSIO_IOSIZE_8 | ioport); 962 963 /* write the ioport to the UARTBAR */ 964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 966 uartbar |= (ioport << (16 * i)); /* set the ioport */ 967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 968 969 /* get current config */ 970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 971 /* disable interrupts (UARTx_Routing[3:0]) */ 972 miscr &= ~(0xf << (12 - 4 * i)); 973 /* activate the UART (UARTx_En) */ 974 miscr |= 1 << (23 - i); 975 /* write new config with activated UART */ 976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 977 } 978 979 if (ret <= 0) { 980 /* the device has no UARTs if we get here */ 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 984 return ret; 985} 986 987static void pci_ite887x_exit(struct pci_dev *dev) 988{ 989 u32 ioport; 990 /* the ioport is bit 0-15 in POSIO0R */ 991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 992 ioport &= 0xffff; 993 release_region(ioport, ITE_887x_IOSIZE); 994} 995 996/* 997 * Oxford Semiconductor Inc. 998 * Check if an OxSemi device is part of the Tornado range of devices. 999 */ 1000#define PCI_VENDOR_ID_ENDRUN 0x7401 1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1002 1003static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1004{ 1005 /* OxSemi Tornado devices are all 0xCxxx */ 1006 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1007 (dev->device & 0xf000) != 0xc000) 1008 return false; 1009 1010 /* EndRun devices are all 0xExxx */ 1011 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1012 (dev->device & 0xf000) != 0xe000) 1013 return false; 1014 1015 return true; 1016} 1017 1018/* 1019 * Determine the number of ports available on a Tornado device. 1020 */ 1021static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1022{ 1023 u8 __iomem *p; 1024 unsigned long deviceID; 1025 unsigned int number_uarts = 0; 1026 1027 if (!pci_oxsemi_tornado_p(dev)) 1028 return 0; 1029 1030 p = pci_iomap(dev, 0, 5); 1031 if (p == NULL) 1032 return -ENOMEM; 1033 1034 deviceID = ioread32(p); 1035 /* Tornado device */ 1036 if (deviceID == 0x07000200) { 1037 number_uarts = ioread8(p + 4); 1038 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1039 number_uarts, 1040 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1041 "EndRun" : "Oxford"); 1042 } 1043 pci_iounmap(dev, p); 1044 return number_uarts; 1045} 1046 1047/* Quatech devices have their own extra interface features */ 1048 1049struct quatech_feature { 1050 u16 devid; 1051 bool amcc; 1052}; 1053 1054#define QPCR_TEST_FOR1 0x3F 1055#define QPCR_TEST_GET1 0x00 1056#define QPCR_TEST_FOR2 0x40 1057#define QPCR_TEST_GET2 0x40 1058#define QPCR_TEST_FOR3 0x80 1059#define QPCR_TEST_GET3 0x40 1060#define QPCR_TEST_FOR4 0xC0 1061#define QPCR_TEST_GET4 0x80 1062 1063#define QOPR_CLOCK_X1 0x0000 1064#define QOPR_CLOCK_X2 0x0001 1065#define QOPR_CLOCK_X4 0x0002 1066#define QOPR_CLOCK_X8 0x0003 1067#define QOPR_CLOCK_RATE_MASK 0x0003 1068 1069 1070static struct quatech_feature quatech_cards[] = { 1071 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1072 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1073 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1074 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1075 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1076 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1077 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1078 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1079 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1080 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1081 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1082 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1083 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1084 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1085 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1086 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1087 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1088 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1089 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1090 { 0, } 1091}; 1092 1093static int pci_quatech_amcc(struct pci_dev *dev) 1094{ 1095 struct quatech_feature *qf = &quatech_cards[0]; 1096 while (qf->devid) { 1097 if (qf->devid == dev->device) 1098 return qf->amcc; 1099 qf++; 1100 } 1101 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1102 return 0; 1103}; 1104 1105static int pci_quatech_rqopr(struct uart_8250_port *port) 1106{ 1107 unsigned long base = port->port.iobase; 1108 u8 LCR, val; 1109 1110 LCR = inb(base + UART_LCR); 1111 outb(0xBF, base + UART_LCR); 1112 val = inb(base + UART_SCR); 1113 outb(LCR, base + UART_LCR); 1114 return val; 1115} 1116 1117static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1118{ 1119 unsigned long base = port->port.iobase; 1120 u8 LCR; 1121 1122 LCR = inb(base + UART_LCR); 1123 outb(0xBF, base + UART_LCR); 1124 inb(base + UART_SCR); 1125 outb(qopr, base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127} 1128 1129static int pci_quatech_rqmcr(struct uart_8250_port *port) 1130{ 1131 unsigned long base = port->port.iobase; 1132 u8 LCR, val, qmcr; 1133 1134 LCR = inb(base + UART_LCR); 1135 outb(0xBF, base + UART_LCR); 1136 val = inb(base + UART_SCR); 1137 outb(val | 0x10, base + UART_SCR); 1138 qmcr = inb(base + UART_MCR); 1139 outb(val, base + UART_SCR); 1140 outb(LCR, base + UART_LCR); 1141 1142 return qmcr; 1143} 1144 1145static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1146{ 1147 unsigned long base = port->port.iobase; 1148 u8 LCR, val; 1149 1150 LCR = inb(base + UART_LCR); 1151 outb(0xBF, base + UART_LCR); 1152 val = inb(base + UART_SCR); 1153 outb(val | 0x10, base + UART_SCR); 1154 outb(qmcr, base + UART_MCR); 1155 outb(val, base + UART_SCR); 1156 outb(LCR, base + UART_LCR); 1157} 1158 1159static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1160{ 1161 unsigned long base = port->port.iobase; 1162 u8 LCR, val; 1163 1164 LCR = inb(base + UART_LCR); 1165 outb(0xBF, base + UART_LCR); 1166 val = inb(base + UART_SCR); 1167 if (val & 0x20) { 1168 outb(0x80, UART_LCR); 1169 if (!(inb(UART_SCR) & 0x20)) { 1170 outb(LCR, base + UART_LCR); 1171 return 1; 1172 } 1173 } 1174 return 0; 1175} 1176 1177static int pci_quatech_test(struct uart_8250_port *port) 1178{ 1179 u8 reg, qopr; 1180 1181 qopr = pci_quatech_rqopr(port); 1182 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1183 reg = pci_quatech_rqopr(port) & 0xC0; 1184 if (reg != QPCR_TEST_GET1) 1185 return -EINVAL; 1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1187 reg = pci_quatech_rqopr(port) & 0xC0; 1188 if (reg != QPCR_TEST_GET2) 1189 return -EINVAL; 1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1191 reg = pci_quatech_rqopr(port) & 0xC0; 1192 if (reg != QPCR_TEST_GET3) 1193 return -EINVAL; 1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1195 reg = pci_quatech_rqopr(port) & 0xC0; 1196 if (reg != QPCR_TEST_GET4) 1197 return -EINVAL; 1198 1199 pci_quatech_wqopr(port, qopr); 1200 return 0; 1201} 1202 1203static int pci_quatech_clock(struct uart_8250_port *port) 1204{ 1205 u8 qopr, reg, set; 1206 unsigned long clock; 1207 1208 if (pci_quatech_test(port) < 0) 1209 return 1843200; 1210 1211 qopr = pci_quatech_rqopr(port); 1212 1213 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (reg & QOPR_CLOCK_X8) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1220 reg = pci_quatech_rqopr(port); 1221 if (!(reg & QOPR_CLOCK_X8)) { 1222 clock = 1843200; 1223 goto out; 1224 } 1225 reg &= QOPR_CLOCK_X8; 1226 if (reg == QOPR_CLOCK_X2) { 1227 clock = 3685400; 1228 set = QOPR_CLOCK_X2; 1229 } else if (reg == QOPR_CLOCK_X4) { 1230 clock = 7372800; 1231 set = QOPR_CLOCK_X4; 1232 } else if (reg == QOPR_CLOCK_X8) { 1233 clock = 14745600; 1234 set = QOPR_CLOCK_X8; 1235 } else { 1236 clock = 1843200; 1237 set = QOPR_CLOCK_X1; 1238 } 1239 qopr &= ~QOPR_CLOCK_RATE_MASK; 1240 qopr |= set; 1241 1242out: 1243 pci_quatech_wqopr(port, qopr); 1244 return clock; 1245} 1246 1247static int pci_quatech_rs422(struct uart_8250_port *port) 1248{ 1249 u8 qmcr; 1250 int rs422 = 0; 1251 1252 if (!pci_quatech_has_qmcr(port)) 1253 return 0; 1254 qmcr = pci_quatech_rqmcr(port); 1255 pci_quatech_wqmcr(port, 0xFF); 1256 if (pci_quatech_rqmcr(port)) 1257 rs422 = 1; 1258 pci_quatech_wqmcr(port, qmcr); 1259 return rs422; 1260} 1261 1262static int pci_quatech_init(struct pci_dev *dev) 1263{ 1264 if (pci_quatech_amcc(dev)) { 1265 unsigned long base = pci_resource_start(dev, 0); 1266 if (base) { 1267 u32 tmp; 1268 1269 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1270 tmp = inl(base + 0x3c); 1271 outl(tmp | 0x01000000, base + 0x3c); 1272 outl(tmp &= ~0x01000000, base + 0x3c); 1273 } 1274 } 1275 return 0; 1276} 1277 1278static int pci_quatech_setup(struct serial_private *priv, 1279 const struct pciserial_board *board, 1280 struct uart_8250_port *port, int idx) 1281{ 1282 /* Needed by pci_quatech calls below */ 1283 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1284 /* Set up the clocking */ 1285 port->port.uartclk = pci_quatech_clock(port); 1286 /* For now just warn about RS422 */ 1287 if (pci_quatech_rs422(port)) 1288 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1289 return pci_default_setup(priv, board, port, idx); 1290} 1291 1292static void pci_quatech_exit(struct pci_dev *dev) 1293{ 1294} 1295 1296static int pci_default_setup(struct serial_private *priv, 1297 const struct pciserial_board *board, 1298 struct uart_8250_port *port, int idx) 1299{ 1300 unsigned int bar, offset = board->first_offset, maxnr; 1301 1302 bar = FL_GET_BASE(board->flags); 1303 if (board->flags & FL_BASE_BARS) 1304 bar += idx; 1305 else 1306 offset += idx * board->uart_offset; 1307 1308 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1309 (board->reg_shift + 3); 1310 1311 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1312 return 1; 1313 1314 return setup_port(priv, port, bar, offset, board->reg_shift); 1315} 1316static void 1317pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1318 unsigned int quot, unsigned int quot_frac) 1319{ 1320 int scr; 1321 int lcr; 1322 1323 for (scr = 16; scr > 4; scr--) { 1324 unsigned int maxrate = port->uartclk / scr; 1325 unsigned int divisor = max(maxrate / baud, 1U); 1326 int delta = maxrate / divisor - baud; 1327 1328 if (baud > maxrate + baud / 50) 1329 continue; 1330 1331 if (delta > baud / 50) 1332 divisor++; 1333 1334 if (divisor > 0xffff) 1335 continue; 1336 1337 /* Update delta due to possible divisor change */ 1338 delta = maxrate / divisor - baud; 1339 if (abs(delta) < baud / 50) { 1340 lcr = serial_port_in(port, UART_LCR); 1341 serial_port_out(port, UART_LCR, lcr | 0x80); 1342 serial_port_out(port, UART_DLL, divisor & 0xff); 1343 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff); 1344 serial_port_out(port, 2, 16 - scr); 1345 serial_port_out(port, UART_LCR, lcr); 1346 return; 1347 } 1348 } 1349} 1350static int pci_pericom_setup(struct serial_private *priv, 1351 const struct pciserial_board *board, 1352 struct uart_8250_port *port, int idx) 1353{ 1354 unsigned int bar, offset = board->first_offset, maxnr; 1355 1356 bar = FL_GET_BASE(board->flags); 1357 if (board->flags & FL_BASE_BARS) 1358 bar += idx; 1359 else 1360 offset += idx * board->uart_offset; 1361 1362 1363 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1364 (board->reg_shift + 3); 1365 1366 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1367 return 1; 1368 1369 port->port.set_divisor = pericom_do_set_divisor; 1370 1371 return setup_port(priv, port, bar, offset, board->reg_shift); 1372} 1373 1374static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1375 const struct pciserial_board *board, 1376 struct uart_8250_port *port, int idx) 1377{ 1378 unsigned int bar, offset = board->first_offset, maxnr; 1379 1380 bar = FL_GET_BASE(board->flags); 1381 if (board->flags & FL_BASE_BARS) 1382 bar += idx; 1383 else 1384 offset += idx * board->uart_offset; 1385 1386 if (idx==3) 1387 offset = 0x38; 1388 1389 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1390 (board->reg_shift + 3); 1391 1392 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1393 return 1; 1394 1395 port->port.set_divisor = pericom_do_set_divisor; 1396 1397 return setup_port(priv, port, bar, offset, board->reg_shift); 1398} 1399 1400static int 1401ce4100_serial_setup(struct serial_private *priv, 1402 const struct pciserial_board *board, 1403 struct uart_8250_port *port, int idx) 1404{ 1405 int ret; 1406 1407 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1408 port->port.iotype = UPIO_MEM32; 1409 port->port.type = PORT_XSCALE; 1410 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1411 port->port.regshift = 2; 1412 1413 return ret; 1414} 1415 1416static int 1417pci_omegapci_setup(struct serial_private *priv, 1418 const struct pciserial_board *board, 1419 struct uart_8250_port *port, int idx) 1420{ 1421 return setup_port(priv, port, 2, idx * 8, 0); 1422} 1423 1424static int 1425pci_brcm_trumanage_setup(struct serial_private *priv, 1426 const struct pciserial_board *board, 1427 struct uart_8250_port *port, int idx) 1428{ 1429 int ret = pci_default_setup(priv, board, port, idx); 1430 1431 port->port.type = PORT_BRCM_TRUMANAGE; 1432 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1433 return ret; 1434} 1435 1436/* RTS will control by MCR if this bit is 0 */ 1437#define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1438/* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1439#define FINTEK_RTS_INVERT BIT(5) 1440 1441/* We should do proper H/W transceiver setting before change to RS485 mode */ 1442static int pci_fintek_rs485_config(struct uart_port *port, 1443 struct serial_rs485 *rs485) 1444{ 1445 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1446 u8 setting; 1447 u8 *index = (u8 *) port->private_data; 1448 1449 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1450 1451 if (!rs485) 1452 rs485 = &port->rs485; 1453 else if (rs485->flags & SER_RS485_ENABLED) 1454 memset(rs485->padding, 0, sizeof(rs485->padding)); 1455 else 1456 memset(rs485, 0, sizeof(*rs485)); 1457 1458 /* F81504/508/512 not support RTS delay before or after send */ 1459 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1460 1461 if (rs485->flags & SER_RS485_ENABLED) { 1462 /* Enable RTS H/W control mode */ 1463 setting |= FINTEK_RTS_CONTROL_BY_HW; 1464 1465 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1466 /* RTS driving high on TX */ 1467 setting &= ~FINTEK_RTS_INVERT; 1468 } else { 1469 /* RTS driving low on TX */ 1470 setting |= FINTEK_RTS_INVERT; 1471 } 1472 1473 rs485->delay_rts_after_send = 0; 1474 rs485->delay_rts_before_send = 0; 1475 } else { 1476 /* Disable RTS H/W control mode */ 1477 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1478 } 1479 1480 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1481 1482 if (rs485 != &port->rs485) 1483 port->rs485 = *rs485; 1484 1485 return 0; 1486} 1487 1488static int pci_fintek_setup(struct serial_private *priv, 1489 const struct pciserial_board *board, 1490 struct uart_8250_port *port, int idx) 1491{ 1492 struct pci_dev *pdev = priv->dev; 1493 u8 *data; 1494 u8 config_base; 1495 u16 iobase; 1496 1497 config_base = 0x40 + 0x08 * idx; 1498 1499 /* Get the io address from configuration space */ 1500 pci_read_config_word(pdev, config_base + 4, &iobase); 1501 1502 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1503 1504 port->port.iotype = UPIO_PORT; 1505 port->port.iobase = iobase; 1506 port->port.rs485_config = pci_fintek_rs485_config; 1507 1508 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1509 if (!data) 1510 return -ENOMEM; 1511 1512 /* preserve index in PCI configuration space */ 1513 *data = idx; 1514 port->port.private_data = data; 1515 1516 return 0; 1517} 1518 1519static int pci_fintek_init(struct pci_dev *dev) 1520{ 1521 unsigned long iobase; 1522 u32 max_port, i; 1523 resource_size_t bar_data[3]; 1524 u8 config_base; 1525 struct serial_private *priv = pci_get_drvdata(dev); 1526 1527 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1528 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1529 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1530 return -ENODEV; 1531 1532 switch (dev->device) { 1533 case 0x1104: /* 4 ports */ 1534 case 0x1108: /* 8 ports */ 1535 max_port = dev->device & 0xff; 1536 break; 1537 case 0x1112: /* 12 ports */ 1538 max_port = 12; 1539 break; 1540 default: 1541 return -EINVAL; 1542 } 1543 1544 /* Get the io address dispatch from the BIOS */ 1545 bar_data[0] = pci_resource_start(dev, 5); 1546 bar_data[1] = pci_resource_start(dev, 4); 1547 bar_data[2] = pci_resource_start(dev, 3); 1548 1549 for (i = 0; i < max_port; ++i) { 1550 /* UART0 configuration offset start from 0x40 */ 1551 config_base = 0x40 + 0x08 * i; 1552 1553 /* Calculate Real IO Port */ 1554 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1555 1556 /* Enable UART I/O port */ 1557 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1558 1559 /* Select 128-byte FIFO and 8x FIFO threshold */ 1560 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1561 1562 /* LSB UART */ 1563 pci_write_config_byte(dev, config_base + 0x04, 1564 (u8)(iobase & 0xff)); 1565 1566 /* MSB UART */ 1567 pci_write_config_byte(dev, config_base + 0x05, 1568 (u8)((iobase & 0xff00) >> 8)); 1569 1570 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1571 1572 if (!priv) { 1573 /* First init without port data 1574 * force init to RS232 Mode 1575 */ 1576 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1577 } 1578 } 1579 1580 return max_port; 1581} 1582 1583static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1584{ 1585 struct f815xxa_data *data = p->private_data; 1586 unsigned long flags; 1587 1588 spin_lock_irqsave(&data->lock, flags); 1589 writeb(value, p->membase + offset); 1590 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1591 spin_unlock_irqrestore(&data->lock, flags); 1592} 1593 1594static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1595 const struct pciserial_board *board, 1596 struct uart_8250_port *port, int idx) 1597{ 1598 struct pci_dev *pdev = priv->dev; 1599 struct f815xxa_data *data; 1600 1601 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1602 if (!data) 1603 return -ENOMEM; 1604 1605 data->idx = idx; 1606 spin_lock_init(&data->lock); 1607 1608 port->port.private_data = data; 1609 port->port.iotype = UPIO_MEM; 1610 port->port.flags |= UPF_IOREMAP; 1611 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1612 port->port.serial_out = f815xxa_mem_serial_out; 1613 1614 return 0; 1615} 1616 1617static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1618{ 1619 u32 max_port, i; 1620 int config_base; 1621 1622 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1623 return -ENODEV; 1624 1625 switch (dev->device) { 1626 case 0x1204: /* 4 ports */ 1627 case 0x1208: /* 8 ports */ 1628 max_port = dev->device & 0xff; 1629 break; 1630 case 0x1212: /* 12 ports */ 1631 max_port = 12; 1632 break; 1633 default: 1634 return -EINVAL; 1635 } 1636 1637 /* Set to mmio decode */ 1638 pci_write_config_byte(dev, 0x209, 0x40); 1639 1640 for (i = 0; i < max_port; ++i) { 1641 /* UART0 configuration offset start from 0x2A0 */ 1642 config_base = 0x2A0 + 0x08 * i; 1643 1644 /* Select 128-byte FIFO and 8x FIFO threshold */ 1645 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1646 1647 /* Enable UART I/O port */ 1648 pci_write_config_byte(dev, config_base + 0, 0x01); 1649 } 1650 1651 return max_port; 1652} 1653 1654static int skip_tx_en_setup(struct serial_private *priv, 1655 const struct pciserial_board *board, 1656 struct uart_8250_port *port, int idx) 1657{ 1658 port->port.quirks |= UPQ_NO_TXEN_TEST; 1659 pci_dbg(priv->dev, 1660 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1661 priv->dev->vendor, priv->dev->device, 1662 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1663 1664 return pci_default_setup(priv, board, port, idx); 1665} 1666 1667static void kt_handle_break(struct uart_port *p) 1668{ 1669 struct uart_8250_port *up = up_to_u8250p(p); 1670 /* 1671 * On receipt of a BI, serial device in Intel ME (Intel 1672 * management engine) needs to have its fifos cleared for sane 1673 * SOL (Serial Over Lan) output. 1674 */ 1675 serial8250_clear_and_reinit_fifos(up); 1676} 1677 1678static unsigned int kt_serial_in(struct uart_port *p, int offset) 1679{ 1680 struct uart_8250_port *up = up_to_u8250p(p); 1681 unsigned int val; 1682 1683 /* 1684 * When the Intel ME (management engine) gets reset its serial 1685 * port registers could return 0 momentarily. Functions like 1686 * serial8250_console_write, read and save the IER, perform 1687 * some operation and then restore it. In order to avoid 1688 * setting IER register inadvertently to 0, if the value read 1689 * is 0, double check with ier value in uart_8250_port and use 1690 * that instead. up->ier should be the same value as what is 1691 * currently configured. 1692 */ 1693 val = inb(p->iobase + offset); 1694 if (offset == UART_IER) { 1695 if (val == 0) 1696 val = up->ier; 1697 } 1698 return val; 1699} 1700 1701static int kt_serial_setup(struct serial_private *priv, 1702 const struct pciserial_board *board, 1703 struct uart_8250_port *port, int idx) 1704{ 1705 port->port.flags |= UPF_BUG_THRE; 1706 port->port.serial_in = kt_serial_in; 1707 port->port.handle_break = kt_handle_break; 1708 return skip_tx_en_setup(priv, board, port, idx); 1709} 1710 1711static int pci_eg20t_init(struct pci_dev *dev) 1712{ 1713#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1714 return -ENODEV; 1715#else 1716 return 0; 1717#endif 1718} 1719 1720static int 1721pci_wch_ch353_setup(struct serial_private *priv, 1722 const struct pciserial_board *board, 1723 struct uart_8250_port *port, int idx) 1724{ 1725 port->port.flags |= UPF_FIXED_TYPE; 1726 port->port.type = PORT_16550A; 1727 return pci_default_setup(priv, board, port, idx); 1728} 1729 1730static int 1731pci_wch_ch355_setup(struct serial_private *priv, 1732 const struct pciserial_board *board, 1733 struct uart_8250_port *port, int idx) 1734{ 1735 port->port.flags |= UPF_FIXED_TYPE; 1736 port->port.type = PORT_16550A; 1737 return pci_default_setup(priv, board, port, idx); 1738} 1739 1740static int 1741pci_wch_ch38x_setup(struct serial_private *priv, 1742 const struct pciserial_board *board, 1743 struct uart_8250_port *port, int idx) 1744{ 1745 port->port.flags |= UPF_FIXED_TYPE; 1746 port->port.type = PORT_16850; 1747 return pci_default_setup(priv, board, port, idx); 1748} 1749 1750 1751#define CH384_XINT_ENABLE_REG 0xEB 1752#define CH384_XINT_ENABLE_BIT 0x02 1753 1754static int pci_wch_ch38x_init(struct pci_dev *dev) 1755{ 1756 int max_port; 1757 unsigned long iobase; 1758 1759 1760 switch (dev->device) { 1761 case 0x3853: /* 8 ports */ 1762 max_port = 8; 1763 break; 1764 default: 1765 return -EINVAL; 1766 } 1767 1768 iobase = pci_resource_start(dev, 0); 1769 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1770 1771 return max_port; 1772} 1773 1774static void pci_wch_ch38x_exit(struct pci_dev *dev) 1775{ 1776 unsigned long iobase; 1777 1778 iobase = pci_resource_start(dev, 0); 1779 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1780} 1781 1782 1783static int 1784pci_sunix_setup(struct serial_private *priv, 1785 const struct pciserial_board *board, 1786 struct uart_8250_port *port, int idx) 1787{ 1788 int bar; 1789 int offset; 1790 1791 port->port.flags |= UPF_FIXED_TYPE; 1792 port->port.type = PORT_SUNIX; 1793 1794 if (idx < 4) { 1795 bar = 0; 1796 offset = idx * board->uart_offset; 1797 } else { 1798 bar = 1; 1799 idx -= 4; 1800 idx = div_s64_rem(idx, 4, &offset); 1801 offset = idx * 64 + offset * board->uart_offset; 1802 } 1803 1804 return setup_port(priv, port, bar, offset, 0); 1805} 1806 1807static int 1808pci_moxa_setup(struct serial_private *priv, 1809 const struct pciserial_board *board, 1810 struct uart_8250_port *port, int idx) 1811{ 1812 unsigned int bar = FL_GET_BASE(board->flags); 1813 int offset; 1814 1815 if (board->num_ports == 4 && idx == 3) 1816 offset = 7 * board->uart_offset; 1817 else 1818 offset = idx * board->uart_offset; 1819 1820 return setup_port(priv, port, bar, offset, 0); 1821} 1822 1823#define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1824#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1825#define PCI_DEVICE_ID_OCTPRO 0x0001 1826#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1827#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1828#define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1829#define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1830#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1831#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1832#define PCI_VENDOR_ID_ADVANTECH 0x13fe 1833#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1834#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 1835#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 1836#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1837#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1838#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1839#define PCI_DEVICE_ID_TITAN_200I 0x8028 1840#define PCI_DEVICE_ID_TITAN_400I 0x8048 1841#define PCI_DEVICE_ID_TITAN_800I 0x8088 1842#define PCI_DEVICE_ID_TITAN_800EH 0xA007 1843#define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1844#define PCI_DEVICE_ID_TITAN_400EH 0xA009 1845#define PCI_DEVICE_ID_TITAN_100E 0xA010 1846#define PCI_DEVICE_ID_TITAN_200E 0xA012 1847#define PCI_DEVICE_ID_TITAN_400E 0xA013 1848#define PCI_DEVICE_ID_TITAN_800E 0xA014 1849#define PCI_DEVICE_ID_TITAN_200EI 0xA016 1850#define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1851#define PCI_DEVICE_ID_TITAN_200V3 0xA306 1852#define PCI_DEVICE_ID_TITAN_400V3 0xA310 1853#define PCI_DEVICE_ID_TITAN_410V3 0xA312 1854#define PCI_DEVICE_ID_TITAN_800V3 0xA314 1855#define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1856#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1857#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1858#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1859#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1860#define PCI_VENDOR_ID_WCH 0x4348 1861#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1862#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1863#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1864#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1865#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1866#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1867#define PCI_VENDOR_ID_AGESTAR 0x5372 1868#define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1869#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1870#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1871 1872#define PCIE_VENDOR_ID_WCH 0x1c00 1873#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1874#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1875#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1876#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1877 1878#define PCI_VENDOR_ID_ACCESIO 0x494f 1879#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1880#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1881#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1882#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1883#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1884#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1885#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1886#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1887#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1888#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1889#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1890#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1891#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1892#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1893#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1894#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1895#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1896#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1897#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1898#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1899#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1900#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1901#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1902#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1903#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1904#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1905#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1906#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1907#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1908#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1909#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1910#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1911#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1912 1913 1914#define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1915#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1916#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1917#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1918#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1919#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1920#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1921#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1922#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1923#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1924#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1925#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1926 1927/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1928#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1929#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1930 1931/* 1932 * Master list of serial port init/setup/exit quirks. 1933 * This does not describe the general nature of the port. 1934 * (ie, baud base, number and location of ports, etc) 1935 * 1936 * This list is ordered alphabetically by vendor then device. 1937 * Specific entries must come before more generic entries. 1938 */ 1939static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1940 /* 1941 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1942 */ 1943 { 1944 .vendor = PCI_VENDOR_ID_AMCC, 1945 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1946 .subvendor = PCI_ANY_ID, 1947 .subdevice = PCI_ANY_ID, 1948 .setup = addidata_apci7800_setup, 1949 }, 1950 /* 1951 * AFAVLAB cards - these may be called via parport_serial 1952 * It is not clear whether this applies to all products. 1953 */ 1954 { 1955 .vendor = PCI_VENDOR_ID_AFAVLAB, 1956 .device = PCI_ANY_ID, 1957 .subvendor = PCI_ANY_ID, 1958 .subdevice = PCI_ANY_ID, 1959 .setup = afavlab_setup, 1960 }, 1961 /* 1962 * HP Diva 1963 */ 1964 { 1965 .vendor = PCI_VENDOR_ID_HP, 1966 .device = PCI_DEVICE_ID_HP_DIVA, 1967 .subvendor = PCI_ANY_ID, 1968 .subdevice = PCI_ANY_ID, 1969 .init = pci_hp_diva_init, 1970 .setup = pci_hp_diva_setup, 1971 }, 1972 /* 1973 * HPE PCI serial device 1974 */ 1975 { 1976 .vendor = PCI_VENDOR_ID_HP_3PAR, 1977 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 1978 .subvendor = PCI_ANY_ID, 1979 .subdevice = PCI_ANY_ID, 1980 .setup = pci_hp_diva_setup, 1981 }, 1982 /* 1983 * Intel 1984 */ 1985 { 1986 .vendor = PCI_VENDOR_ID_INTEL, 1987 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1988 .subvendor = 0xe4bf, 1989 .subdevice = PCI_ANY_ID, 1990 .init = pci_inteli960ni_init, 1991 .setup = pci_default_setup, 1992 }, 1993 { 1994 .vendor = PCI_VENDOR_ID_INTEL, 1995 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1996 .subvendor = PCI_ANY_ID, 1997 .subdevice = PCI_ANY_ID, 1998 .setup = skip_tx_en_setup, 1999 }, 2000 { 2001 .vendor = PCI_VENDOR_ID_INTEL, 2002 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2003 .subvendor = PCI_ANY_ID, 2004 .subdevice = PCI_ANY_ID, 2005 .setup = skip_tx_en_setup, 2006 }, 2007 { 2008 .vendor = PCI_VENDOR_ID_INTEL, 2009 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2010 .subvendor = PCI_ANY_ID, 2011 .subdevice = PCI_ANY_ID, 2012 .setup = skip_tx_en_setup, 2013 }, 2014 { 2015 .vendor = PCI_VENDOR_ID_INTEL, 2016 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2017 .subvendor = PCI_ANY_ID, 2018 .subdevice = PCI_ANY_ID, 2019 .setup = ce4100_serial_setup, 2020 }, 2021 { 2022 .vendor = PCI_VENDOR_ID_INTEL, 2023 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2024 .subvendor = PCI_ANY_ID, 2025 .subdevice = PCI_ANY_ID, 2026 .setup = kt_serial_setup, 2027 }, 2028 /* 2029 * ITE 2030 */ 2031 { 2032 .vendor = PCI_VENDOR_ID_ITE, 2033 .device = PCI_DEVICE_ID_ITE_8872, 2034 .subvendor = PCI_ANY_ID, 2035 .subdevice = PCI_ANY_ID, 2036 .init = pci_ite887x_init, 2037 .setup = pci_default_setup, 2038 .exit = pci_ite887x_exit, 2039 }, 2040 /* 2041 * National Instruments 2042 */ 2043 { 2044 .vendor = PCI_VENDOR_ID_NI, 2045 .device = PCI_DEVICE_ID_NI_PCI23216, 2046 .subvendor = PCI_ANY_ID, 2047 .subdevice = PCI_ANY_ID, 2048 .init = pci_ni8420_init, 2049 .setup = pci_default_setup, 2050 .exit = pci_ni8420_exit, 2051 }, 2052 { 2053 .vendor = PCI_VENDOR_ID_NI, 2054 .device = PCI_DEVICE_ID_NI_PCI2328, 2055 .subvendor = PCI_ANY_ID, 2056 .subdevice = PCI_ANY_ID, 2057 .init = pci_ni8420_init, 2058 .setup = pci_default_setup, 2059 .exit = pci_ni8420_exit, 2060 }, 2061 { 2062 .vendor = PCI_VENDOR_ID_NI, 2063 .device = PCI_DEVICE_ID_NI_PCI2324, 2064 .subvendor = PCI_ANY_ID, 2065 .subdevice = PCI_ANY_ID, 2066 .init = pci_ni8420_init, 2067 .setup = pci_default_setup, 2068 .exit = pci_ni8420_exit, 2069 }, 2070 { 2071 .vendor = PCI_VENDOR_ID_NI, 2072 .device = PCI_DEVICE_ID_NI_PCI2322, 2073 .subvendor = PCI_ANY_ID, 2074 .subdevice = PCI_ANY_ID, 2075 .init = pci_ni8420_init, 2076 .setup = pci_default_setup, 2077 .exit = pci_ni8420_exit, 2078 }, 2079 { 2080 .vendor = PCI_VENDOR_ID_NI, 2081 .device = PCI_DEVICE_ID_NI_PCI2324I, 2082 .subvendor = PCI_ANY_ID, 2083 .subdevice = PCI_ANY_ID, 2084 .init = pci_ni8420_init, 2085 .setup = pci_default_setup, 2086 .exit = pci_ni8420_exit, 2087 }, 2088 { 2089 .vendor = PCI_VENDOR_ID_NI, 2090 .device = PCI_DEVICE_ID_NI_PCI2322I, 2091 .subvendor = PCI_ANY_ID, 2092 .subdevice = PCI_ANY_ID, 2093 .init = pci_ni8420_init, 2094 .setup = pci_default_setup, 2095 .exit = pci_ni8420_exit, 2096 }, 2097 { 2098 .vendor = PCI_VENDOR_ID_NI, 2099 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2100 .subvendor = PCI_ANY_ID, 2101 .subdevice = PCI_ANY_ID, 2102 .init = pci_ni8420_init, 2103 .setup = pci_default_setup, 2104 .exit = pci_ni8420_exit, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_NI, 2108 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .init = pci_ni8420_init, 2112 .setup = pci_default_setup, 2113 .exit = pci_ni8420_exit, 2114 }, 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8420_init, 2139 .setup = pci_default_setup, 2140 .exit = pci_ni8420_exit, 2141 }, 2142 { 2143 .vendor = PCI_VENDOR_ID_NI, 2144 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2145 .subvendor = PCI_ANY_ID, 2146 .subdevice = PCI_ANY_ID, 2147 .init = pci_ni8420_init, 2148 .setup = pci_default_setup, 2149 .exit = pci_ni8420_exit, 2150 }, 2151 { 2152 .vendor = PCI_VENDOR_ID_NI, 2153 .device = PCI_ANY_ID, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_ni8430_init, 2157 .setup = pci_ni8430_setup, 2158 .exit = pci_ni8430_exit, 2159 }, 2160 /* Quatech */ 2161 { 2162 .vendor = PCI_VENDOR_ID_QUATECH, 2163 .device = PCI_ANY_ID, 2164 .subvendor = PCI_ANY_ID, 2165 .subdevice = PCI_ANY_ID, 2166 .init = pci_quatech_init, 2167 .setup = pci_quatech_setup, 2168 .exit = pci_quatech_exit, 2169 }, 2170 /* 2171 * Panacom 2172 */ 2173 { 2174 .vendor = PCI_VENDOR_ID_PANACOM, 2175 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2176 .subvendor = PCI_ANY_ID, 2177 .subdevice = PCI_ANY_ID, 2178 .init = pci_plx9050_init, 2179 .setup = pci_default_setup, 2180 .exit = pci_plx9050_exit, 2181 }, 2182 { 2183 .vendor = PCI_VENDOR_ID_PANACOM, 2184 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2185 .subvendor = PCI_ANY_ID, 2186 .subdevice = PCI_ANY_ID, 2187 .init = pci_plx9050_init, 2188 .setup = pci_default_setup, 2189 .exit = pci_plx9050_exit, 2190 }, 2191 /* 2192 * Pericom (Only 7954 - It have a offset jump for port 4) 2193 */ 2194 { 2195 .vendor = PCI_VENDOR_ID_PERICOM, 2196 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2197 .subvendor = PCI_ANY_ID, 2198 .subdevice = PCI_ANY_ID, 2199 .setup = pci_pericom_setup_four_at_eight, 2200 }, 2201 /* 2202 * PLX 2203 */ 2204 { 2205 .vendor = PCI_VENDOR_ID_PLX, 2206 .device = PCI_DEVICE_ID_PLX_9050, 2207 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2208 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2209 .init = pci_plx9050_init, 2210 .setup = pci_default_setup, 2211 .exit = pci_plx9050_exit, 2212 }, 2213 { 2214 .vendor = PCI_VENDOR_ID_PLX, 2215 .device = PCI_DEVICE_ID_PLX_9050, 2216 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2217 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2218 .init = pci_plx9050_init, 2219 .setup = pci_default_setup, 2220 .exit = pci_plx9050_exit, 2221 }, 2222 { 2223 .vendor = PCI_VENDOR_ID_PLX, 2224 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2225 .subvendor = PCI_VENDOR_ID_PLX, 2226 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2227 .init = pci_plx9050_init, 2228 .setup = pci_default_setup, 2229 .exit = pci_plx9050_exit, 2230 }, 2231 { 2232 .vendor = PCI_VENDOR_ID_ACCESIO, 2233 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2234 .subvendor = PCI_ANY_ID, 2235 .subdevice = PCI_ANY_ID, 2236 .setup = pci_pericom_setup_four_at_eight, 2237 }, 2238 { 2239 .vendor = PCI_VENDOR_ID_ACCESIO, 2240 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2241 .subvendor = PCI_ANY_ID, 2242 .subdevice = PCI_ANY_ID, 2243 .setup = pci_pericom_setup_four_at_eight, 2244 }, 2245 { 2246 .vendor = PCI_VENDOR_ID_ACCESIO, 2247 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2248 .subvendor = PCI_ANY_ID, 2249 .subdevice = PCI_ANY_ID, 2250 .setup = pci_pericom_setup_four_at_eight, 2251 }, 2252 { 2253 .vendor = PCI_VENDOR_ID_ACCESIO, 2254 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2255 .subvendor = PCI_ANY_ID, 2256 .subdevice = PCI_ANY_ID, 2257 .setup = pci_pericom_setup_four_at_eight, 2258 }, 2259 { 2260 .vendor = PCI_VENDOR_ID_ACCESIO, 2261 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2262 .subvendor = PCI_ANY_ID, 2263 .subdevice = PCI_ANY_ID, 2264 .setup = pci_pericom_setup_four_at_eight, 2265 }, 2266 { 2267 .vendor = PCI_VENDOR_ID_ACCESIO, 2268 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2269 .subvendor = PCI_ANY_ID, 2270 .subdevice = PCI_ANY_ID, 2271 .setup = pci_pericom_setup_four_at_eight, 2272 }, 2273 { 2274 .vendor = PCI_VENDOR_ID_ACCESIO, 2275 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2276 .subvendor = PCI_ANY_ID, 2277 .subdevice = PCI_ANY_ID, 2278 .setup = pci_pericom_setup_four_at_eight, 2279 }, 2280 { 2281 .vendor = PCI_VENDOR_ID_ACCESIO, 2282 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2283 .subvendor = PCI_ANY_ID, 2284 .subdevice = PCI_ANY_ID, 2285 .setup = pci_pericom_setup_four_at_eight, 2286 }, 2287 { 2288 .vendor = PCI_VENDOR_ID_ACCESIO, 2289 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2290 .subvendor = PCI_ANY_ID, 2291 .subdevice = PCI_ANY_ID, 2292 .setup = pci_pericom_setup_four_at_eight, 2293 }, 2294 { 2295 .vendor = PCI_VENDOR_ID_ACCESIO, 2296 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2297 .subvendor = PCI_ANY_ID, 2298 .subdevice = PCI_ANY_ID, 2299 .setup = pci_pericom_setup_four_at_eight, 2300 }, 2301 { 2302 .vendor = PCI_VENDOR_ID_ACCESIO, 2303 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2304 .subvendor = PCI_ANY_ID, 2305 .subdevice = PCI_ANY_ID, 2306 .setup = pci_pericom_setup_four_at_eight, 2307 }, 2308 { 2309 .vendor = PCI_VENDOR_ID_ACCESIO, 2310 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2311 .subvendor = PCI_ANY_ID, 2312 .subdevice = PCI_ANY_ID, 2313 .setup = pci_pericom_setup_four_at_eight, 2314 }, 2315 { 2316 .vendor = PCI_VENDOR_ID_ACCESIO, 2317 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2318 .subvendor = PCI_ANY_ID, 2319 .subdevice = PCI_ANY_ID, 2320 .setup = pci_pericom_setup_four_at_eight, 2321 }, 2322 { 2323 .vendor = PCI_VENDOR_ID_ACCESIO, 2324 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2325 .subvendor = PCI_ANY_ID, 2326 .subdevice = PCI_ANY_ID, 2327 .setup = pci_pericom_setup_four_at_eight, 2328 }, 2329 { 2330 .vendor = PCI_VENDOR_ID_ACCESIO, 2331 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2332 .subvendor = PCI_ANY_ID, 2333 .subdevice = PCI_ANY_ID, 2334 .setup = pci_pericom_setup_four_at_eight, 2335 }, 2336 { 2337 .vendor = PCI_VENDOR_ID_ACCESIO, 2338 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2339 .subvendor = PCI_ANY_ID, 2340 .subdevice = PCI_ANY_ID, 2341 .setup = pci_pericom_setup_four_at_eight, 2342 }, 2343 { 2344 .vendor = PCI_VENDOR_ID_ACCESIO, 2345 .device = PCI_ANY_ID, 2346 .subvendor = PCI_ANY_ID, 2347 .subdevice = PCI_ANY_ID, 2348 .setup = pci_pericom_setup, 2349 }, /* 2350 * SBS Technologies, Inc., PMC-OCTALPRO 232 2351 */ 2352 { 2353 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2354 .device = PCI_DEVICE_ID_OCTPRO, 2355 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2356 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2357 .init = sbs_init, 2358 .setup = sbs_setup, 2359 .exit = sbs_exit, 2360 }, 2361 /* 2362 * SBS Technologies, Inc., PMC-OCTALPRO 422 2363 */ 2364 { 2365 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2366 .device = PCI_DEVICE_ID_OCTPRO, 2367 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2368 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2369 .init = sbs_init, 2370 .setup = sbs_setup, 2371 .exit = sbs_exit, 2372 }, 2373 /* 2374 * SBS Technologies, Inc., P-Octal 232 2375 */ 2376 { 2377 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2378 .device = PCI_DEVICE_ID_OCTPRO, 2379 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2380 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2381 .init = sbs_init, 2382 .setup = sbs_setup, 2383 .exit = sbs_exit, 2384 }, 2385 /* 2386 * SBS Technologies, Inc., P-Octal 422 2387 */ 2388 { 2389 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2390 .device = PCI_DEVICE_ID_OCTPRO, 2391 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2392 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2393 .init = sbs_init, 2394 .setup = sbs_setup, 2395 .exit = sbs_exit, 2396 }, 2397 /* 2398 * SIIG cards - these may be called via parport_serial 2399 */ 2400 { 2401 .vendor = PCI_VENDOR_ID_SIIG, 2402 .device = PCI_ANY_ID, 2403 .subvendor = PCI_ANY_ID, 2404 .subdevice = PCI_ANY_ID, 2405 .init = pci_siig_init, 2406 .setup = pci_siig_setup, 2407 }, 2408 /* 2409 * Titan cards 2410 */ 2411 { 2412 .vendor = PCI_VENDOR_ID_TITAN, 2413 .device = PCI_DEVICE_ID_TITAN_400L, 2414 .subvendor = PCI_ANY_ID, 2415 .subdevice = PCI_ANY_ID, 2416 .setup = titan_400l_800l_setup, 2417 }, 2418 { 2419 .vendor = PCI_VENDOR_ID_TITAN, 2420 .device = PCI_DEVICE_ID_TITAN_800L, 2421 .subvendor = PCI_ANY_ID, 2422 .subdevice = PCI_ANY_ID, 2423 .setup = titan_400l_800l_setup, 2424 }, 2425 /* 2426 * Timedia cards 2427 */ 2428 { 2429 .vendor = PCI_VENDOR_ID_TIMEDIA, 2430 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2431 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2432 .subdevice = PCI_ANY_ID, 2433 .probe = pci_timedia_probe, 2434 .init = pci_timedia_init, 2435 .setup = pci_timedia_setup, 2436 }, 2437 { 2438 .vendor = PCI_VENDOR_ID_TIMEDIA, 2439 .device = PCI_ANY_ID, 2440 .subvendor = PCI_ANY_ID, 2441 .subdevice = PCI_ANY_ID, 2442 .setup = pci_timedia_setup, 2443 }, 2444 /* 2445 * Sunix PCI serial boards 2446 */ 2447 { 2448 .vendor = PCI_VENDOR_ID_SUNIX, 2449 .device = PCI_DEVICE_ID_SUNIX_1999, 2450 .subvendor = PCI_VENDOR_ID_SUNIX, 2451 .subdevice = PCI_ANY_ID, 2452 .setup = pci_sunix_setup, 2453 }, 2454 /* 2455 * Xircom cards 2456 */ 2457 { 2458 .vendor = PCI_VENDOR_ID_XIRCOM, 2459 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2460 .subvendor = PCI_ANY_ID, 2461 .subdevice = PCI_ANY_ID, 2462 .init = pci_xircom_init, 2463 .setup = pci_default_setup, 2464 }, 2465 /* 2466 * Netmos cards - these may be called via parport_serial 2467 */ 2468 { 2469 .vendor = PCI_VENDOR_ID_NETMOS, 2470 .device = PCI_ANY_ID, 2471 .subvendor = PCI_ANY_ID, 2472 .subdevice = PCI_ANY_ID, 2473 .init = pci_netmos_init, 2474 .setup = pci_netmos_9900_setup, 2475 }, 2476 /* 2477 * EndRun Technologies 2478 */ 2479 { 2480 .vendor = PCI_VENDOR_ID_ENDRUN, 2481 .device = PCI_ANY_ID, 2482 .subvendor = PCI_ANY_ID, 2483 .subdevice = PCI_ANY_ID, 2484 .init = pci_oxsemi_tornado_init, 2485 .setup = pci_default_setup, 2486 }, 2487 /* 2488 * For Oxford Semiconductor Tornado based devices 2489 */ 2490 { 2491 .vendor = PCI_VENDOR_ID_OXSEMI, 2492 .device = PCI_ANY_ID, 2493 .subvendor = PCI_ANY_ID, 2494 .subdevice = PCI_ANY_ID, 2495 .init = pci_oxsemi_tornado_init, 2496 .setup = pci_default_setup, 2497 }, 2498 { 2499 .vendor = PCI_VENDOR_ID_MAINPINE, 2500 .device = PCI_ANY_ID, 2501 .subvendor = PCI_ANY_ID, 2502 .subdevice = PCI_ANY_ID, 2503 .init = pci_oxsemi_tornado_init, 2504 .setup = pci_default_setup, 2505 }, 2506 { 2507 .vendor = PCI_VENDOR_ID_DIGI, 2508 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2509 .subvendor = PCI_SUBVENDOR_ID_IBM, 2510 .subdevice = PCI_ANY_ID, 2511 .init = pci_oxsemi_tornado_init, 2512 .setup = pci_default_setup, 2513 }, 2514 { 2515 .vendor = PCI_VENDOR_ID_INTEL, 2516 .device = 0x8811, 2517 .subvendor = PCI_ANY_ID, 2518 .subdevice = PCI_ANY_ID, 2519 .init = pci_eg20t_init, 2520 .setup = pci_default_setup, 2521 }, 2522 { 2523 .vendor = PCI_VENDOR_ID_INTEL, 2524 .device = 0x8812, 2525 .subvendor = PCI_ANY_ID, 2526 .subdevice = PCI_ANY_ID, 2527 .init = pci_eg20t_init, 2528 .setup = pci_default_setup, 2529 }, 2530 { 2531 .vendor = PCI_VENDOR_ID_INTEL, 2532 .device = 0x8813, 2533 .subvendor = PCI_ANY_ID, 2534 .subdevice = PCI_ANY_ID, 2535 .init = pci_eg20t_init, 2536 .setup = pci_default_setup, 2537 }, 2538 { 2539 .vendor = PCI_VENDOR_ID_INTEL, 2540 .device = 0x8814, 2541 .subvendor = PCI_ANY_ID, 2542 .subdevice = PCI_ANY_ID, 2543 .init = pci_eg20t_init, 2544 .setup = pci_default_setup, 2545 }, 2546 { 2547 .vendor = 0x10DB, 2548 .device = 0x8027, 2549 .subvendor = PCI_ANY_ID, 2550 .subdevice = PCI_ANY_ID, 2551 .init = pci_eg20t_init, 2552 .setup = pci_default_setup, 2553 }, 2554 { 2555 .vendor = 0x10DB, 2556 .device = 0x8028, 2557 .subvendor = PCI_ANY_ID, 2558 .subdevice = PCI_ANY_ID, 2559 .init = pci_eg20t_init, 2560 .setup = pci_default_setup, 2561 }, 2562 { 2563 .vendor = 0x10DB, 2564 .device = 0x8029, 2565 .subvendor = PCI_ANY_ID, 2566 .subdevice = PCI_ANY_ID, 2567 .init = pci_eg20t_init, 2568 .setup = pci_default_setup, 2569 }, 2570 { 2571 .vendor = 0x10DB, 2572 .device = 0x800C, 2573 .subvendor = PCI_ANY_ID, 2574 .subdevice = PCI_ANY_ID, 2575 .init = pci_eg20t_init, 2576 .setup = pci_default_setup, 2577 }, 2578 { 2579 .vendor = 0x10DB, 2580 .device = 0x800D, 2581 .subvendor = PCI_ANY_ID, 2582 .subdevice = PCI_ANY_ID, 2583 .init = pci_eg20t_init, 2584 .setup = pci_default_setup, 2585 }, 2586 /* 2587 * Cronyx Omega PCI (PLX-chip based) 2588 */ 2589 { 2590 .vendor = PCI_VENDOR_ID_PLX, 2591 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2592 .subvendor = PCI_ANY_ID, 2593 .subdevice = PCI_ANY_ID, 2594 .setup = pci_omegapci_setup, 2595 }, 2596 /* WCH CH353 1S1P card (16550 clone) */ 2597 { 2598 .vendor = PCI_VENDOR_ID_WCH, 2599 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2600 .subvendor = PCI_ANY_ID, 2601 .subdevice = PCI_ANY_ID, 2602 .setup = pci_wch_ch353_setup, 2603 }, 2604 /* WCH CH353 2S1P card (16550 clone) */ 2605 { 2606 .vendor = PCI_VENDOR_ID_WCH, 2607 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2608 .subvendor = PCI_ANY_ID, 2609 .subdevice = PCI_ANY_ID, 2610 .setup = pci_wch_ch353_setup, 2611 }, 2612 /* WCH CH353 4S card (16550 clone) */ 2613 { 2614 .vendor = PCI_VENDOR_ID_WCH, 2615 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2616 .subvendor = PCI_ANY_ID, 2617 .subdevice = PCI_ANY_ID, 2618 .setup = pci_wch_ch353_setup, 2619 }, 2620 /* WCH CH353 2S1PF card (16550 clone) */ 2621 { 2622 .vendor = PCI_VENDOR_ID_WCH, 2623 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2624 .subvendor = PCI_ANY_ID, 2625 .subdevice = PCI_ANY_ID, 2626 .setup = pci_wch_ch353_setup, 2627 }, 2628 /* WCH CH352 2S card (16550 clone) */ 2629 { 2630 .vendor = PCI_VENDOR_ID_WCH, 2631 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2632 .subvendor = PCI_ANY_ID, 2633 .subdevice = PCI_ANY_ID, 2634 .setup = pci_wch_ch353_setup, 2635 }, 2636 /* WCH CH355 4S card (16550 clone) */ 2637 { 2638 .vendor = PCI_VENDOR_ID_WCH, 2639 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2640 .subvendor = PCI_ANY_ID, 2641 .subdevice = PCI_ANY_ID, 2642 .setup = pci_wch_ch355_setup, 2643 }, 2644 /* WCH CH382 2S card (16850 clone) */ 2645 { 2646 .vendor = PCIE_VENDOR_ID_WCH, 2647 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2648 .subvendor = PCI_ANY_ID, 2649 .subdevice = PCI_ANY_ID, 2650 .setup = pci_wch_ch38x_setup, 2651 }, 2652 /* WCH CH382 2S1P card (16850 clone) */ 2653 { 2654 .vendor = PCIE_VENDOR_ID_WCH, 2655 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2656 .subvendor = PCI_ANY_ID, 2657 .subdevice = PCI_ANY_ID, 2658 .setup = pci_wch_ch38x_setup, 2659 }, 2660 /* WCH CH384 4S card (16850 clone) */ 2661 { 2662 .vendor = PCIE_VENDOR_ID_WCH, 2663 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2664 .subvendor = PCI_ANY_ID, 2665 .subdevice = PCI_ANY_ID, 2666 .setup = pci_wch_ch38x_setup, 2667 }, 2668 /* WCH CH384 8S card (16850 clone) */ 2669 { 2670 .vendor = PCIE_VENDOR_ID_WCH, 2671 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .init = pci_wch_ch38x_init, 2675 .exit = pci_wch_ch38x_exit, 2676 .setup = pci_wch_ch38x_setup, 2677 }, 2678 /* 2679 * Broadcom TruManage (NetXtreme) 2680 */ 2681 { 2682 .vendor = PCI_VENDOR_ID_BROADCOM, 2683 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2684 .subvendor = PCI_ANY_ID, 2685 .subdevice = PCI_ANY_ID, 2686 .setup = pci_brcm_trumanage_setup, 2687 }, 2688 { 2689 .vendor = 0x1c29, 2690 .device = 0x1104, 2691 .subvendor = PCI_ANY_ID, 2692 .subdevice = PCI_ANY_ID, 2693 .setup = pci_fintek_setup, 2694 .init = pci_fintek_init, 2695 }, 2696 { 2697 .vendor = 0x1c29, 2698 .device = 0x1108, 2699 .subvendor = PCI_ANY_ID, 2700 .subdevice = PCI_ANY_ID, 2701 .setup = pci_fintek_setup, 2702 .init = pci_fintek_init, 2703 }, 2704 { 2705 .vendor = 0x1c29, 2706 .device = 0x1112, 2707 .subvendor = PCI_ANY_ID, 2708 .subdevice = PCI_ANY_ID, 2709 .setup = pci_fintek_setup, 2710 .init = pci_fintek_init, 2711 }, 2712 /* 2713 * MOXA 2714 */ 2715 { 2716 .vendor = PCI_VENDOR_ID_MOXA, 2717 .device = PCI_ANY_ID, 2718 .subvendor = PCI_ANY_ID, 2719 .subdevice = PCI_ANY_ID, 2720 .setup = pci_moxa_setup, 2721 }, 2722 { 2723 .vendor = 0x1c29, 2724 .device = 0x1204, 2725 .subvendor = PCI_ANY_ID, 2726 .subdevice = PCI_ANY_ID, 2727 .setup = pci_fintek_f815xxa_setup, 2728 .init = pci_fintek_f815xxa_init, 2729 }, 2730 { 2731 .vendor = 0x1c29, 2732 .device = 0x1208, 2733 .subvendor = PCI_ANY_ID, 2734 .subdevice = PCI_ANY_ID, 2735 .setup = pci_fintek_f815xxa_setup, 2736 .init = pci_fintek_f815xxa_init, 2737 }, 2738 { 2739 .vendor = 0x1c29, 2740 .device = 0x1212, 2741 .subvendor = PCI_ANY_ID, 2742 .subdevice = PCI_ANY_ID, 2743 .setup = pci_fintek_f815xxa_setup, 2744 .init = pci_fintek_f815xxa_init, 2745 }, 2746 2747 /* 2748 * Default "match everything" terminator entry 2749 */ 2750 { 2751 .vendor = PCI_ANY_ID, 2752 .device = PCI_ANY_ID, 2753 .subvendor = PCI_ANY_ID, 2754 .subdevice = PCI_ANY_ID, 2755 .setup = pci_default_setup, 2756 } 2757}; 2758 2759static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2760{ 2761 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2762} 2763 2764static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2765{ 2766 struct pci_serial_quirk *quirk; 2767 2768 for (quirk = pci_serial_quirks; ; quirk++) 2769 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2770 quirk_id_matches(quirk->device, dev->device) && 2771 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2772 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2773 break; 2774 return quirk; 2775} 2776 2777/* 2778 * This is the configuration table for all of the PCI serial boards 2779 * which we support. It is directly indexed by the pci_board_num_t enum 2780 * value, which is encoded in the pci_device_id PCI probe table's 2781 * driver_data member. 2782 * 2783 * The makeup of these names are: 2784 * pbn_bn{_bt}_n_baud{_offsetinhex} 2785 * 2786 * bn = PCI BAR number 2787 * bt = Index using PCI BARs 2788 * n = number of serial ports 2789 * baud = baud rate 2790 * offsetinhex = offset for each sequential port (in hex) 2791 * 2792 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2793 * 2794 * Please note: in theory if n = 1, _bt infix should make no difference. 2795 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2796 */ 2797enum pci_board_num_t { 2798 pbn_default = 0, 2799 2800 pbn_b0_1_115200, 2801 pbn_b0_2_115200, 2802 pbn_b0_4_115200, 2803 pbn_b0_5_115200, 2804 pbn_b0_8_115200, 2805 2806 pbn_b0_1_921600, 2807 pbn_b0_2_921600, 2808 pbn_b0_4_921600, 2809 2810 pbn_b0_2_1130000, 2811 2812 pbn_b0_4_1152000, 2813 2814 pbn_b0_4_1250000, 2815 2816 pbn_b0_2_1843200, 2817 pbn_b0_4_1843200, 2818 2819 pbn_b0_1_3906250, 2820 2821 pbn_b0_bt_1_115200, 2822 pbn_b0_bt_2_115200, 2823 pbn_b0_bt_4_115200, 2824 pbn_b0_bt_8_115200, 2825 2826 pbn_b0_bt_1_460800, 2827 pbn_b0_bt_2_460800, 2828 pbn_b0_bt_4_460800, 2829 2830 pbn_b0_bt_1_921600, 2831 pbn_b0_bt_2_921600, 2832 pbn_b0_bt_4_921600, 2833 pbn_b0_bt_8_921600, 2834 2835 pbn_b1_1_115200, 2836 pbn_b1_2_115200, 2837 pbn_b1_4_115200, 2838 pbn_b1_8_115200, 2839 pbn_b1_16_115200, 2840 2841 pbn_b1_1_921600, 2842 pbn_b1_2_921600, 2843 pbn_b1_4_921600, 2844 pbn_b1_8_921600, 2845 2846 pbn_b1_2_1250000, 2847 2848 pbn_b1_bt_1_115200, 2849 pbn_b1_bt_2_115200, 2850 pbn_b1_bt_4_115200, 2851 2852 pbn_b1_bt_2_921600, 2853 2854 pbn_b1_1_1382400, 2855 pbn_b1_2_1382400, 2856 pbn_b1_4_1382400, 2857 pbn_b1_8_1382400, 2858 2859 pbn_b2_1_115200, 2860 pbn_b2_2_115200, 2861 pbn_b2_4_115200, 2862 pbn_b2_8_115200, 2863 2864 pbn_b2_1_460800, 2865 pbn_b2_4_460800, 2866 pbn_b2_8_460800, 2867 pbn_b2_16_460800, 2868 2869 pbn_b2_1_921600, 2870 pbn_b2_4_921600, 2871 pbn_b2_8_921600, 2872 2873 pbn_b2_8_1152000, 2874 2875 pbn_b2_bt_1_115200, 2876 pbn_b2_bt_2_115200, 2877 pbn_b2_bt_4_115200, 2878 2879 pbn_b2_bt_2_921600, 2880 pbn_b2_bt_4_921600, 2881 2882 pbn_b3_2_115200, 2883 pbn_b3_4_115200, 2884 pbn_b3_8_115200, 2885 2886 pbn_b4_bt_2_921600, 2887 pbn_b4_bt_4_921600, 2888 pbn_b4_bt_8_921600, 2889 2890 /* 2891 * Board-specific versions. 2892 */ 2893 pbn_panacom, 2894 pbn_panacom2, 2895 pbn_panacom4, 2896 pbn_plx_romulus, 2897 pbn_oxsemi, 2898 pbn_oxsemi_1_3906250, 2899 pbn_oxsemi_2_3906250, 2900 pbn_oxsemi_4_3906250, 2901 pbn_oxsemi_8_3906250, 2902 pbn_intel_i960, 2903 pbn_sgi_ioc3, 2904 pbn_computone_4, 2905 pbn_computone_6, 2906 pbn_computone_8, 2907 pbn_sbsxrsio, 2908 pbn_pasemi_1682M, 2909 pbn_ni8430_2, 2910 pbn_ni8430_4, 2911 pbn_ni8430_8, 2912 pbn_ni8430_16, 2913 pbn_ADDIDATA_PCIe_1_3906250, 2914 pbn_ADDIDATA_PCIe_2_3906250, 2915 pbn_ADDIDATA_PCIe_4_3906250, 2916 pbn_ADDIDATA_PCIe_8_3906250, 2917 pbn_ce4100_1_115200, 2918 pbn_omegapci, 2919 pbn_NETMOS9900_2s_115200, 2920 pbn_brcm_trumanage, 2921 pbn_fintek_4, 2922 pbn_fintek_8, 2923 pbn_fintek_12, 2924 pbn_fintek_F81504A, 2925 pbn_fintek_F81508A, 2926 pbn_fintek_F81512A, 2927 pbn_wch382_2, 2928 pbn_wch384_4, 2929 pbn_wch384_8, 2930 pbn_pericom_PI7C9X7951, 2931 pbn_pericom_PI7C9X7952, 2932 pbn_pericom_PI7C9X7954, 2933 pbn_pericom_PI7C9X7958, 2934 pbn_sunix_pci_1s, 2935 pbn_sunix_pci_2s, 2936 pbn_sunix_pci_4s, 2937 pbn_sunix_pci_8s, 2938 pbn_sunix_pci_16s, 2939 pbn_titan_1_4000000, 2940 pbn_titan_2_4000000, 2941 pbn_titan_4_4000000, 2942 pbn_titan_8_4000000, 2943 pbn_moxa8250_2p, 2944 pbn_moxa8250_4p, 2945 pbn_moxa8250_8p, 2946}; 2947 2948/* 2949 * uart_offset - the space between channels 2950 * reg_shift - describes how the UART registers are mapped 2951 * to PCI memory by the card. 2952 * For example IER register on SBS, Inc. PMC-OctPro is located at 2953 * offset 0x10 from the UART base, while UART_IER is defined as 1 2954 * in include/linux/serial_reg.h, 2955 * see first lines of serial_in() and serial_out() in 8250.c 2956*/ 2957 2958static struct pciserial_board pci_boards[] = { 2959 [pbn_default] = { 2960 .flags = FL_BASE0, 2961 .num_ports = 1, 2962 .base_baud = 115200, 2963 .uart_offset = 8, 2964 }, 2965 [pbn_b0_1_115200] = { 2966 .flags = FL_BASE0, 2967 .num_ports = 1, 2968 .base_baud = 115200, 2969 .uart_offset = 8, 2970 }, 2971 [pbn_b0_2_115200] = { 2972 .flags = FL_BASE0, 2973 .num_ports = 2, 2974 .base_baud = 115200, 2975 .uart_offset = 8, 2976 }, 2977 [pbn_b0_4_115200] = { 2978 .flags = FL_BASE0, 2979 .num_ports = 4, 2980 .base_baud = 115200, 2981 .uart_offset = 8, 2982 }, 2983 [pbn_b0_5_115200] = { 2984 .flags = FL_BASE0, 2985 .num_ports = 5, 2986 .base_baud = 115200, 2987 .uart_offset = 8, 2988 }, 2989 [pbn_b0_8_115200] = { 2990 .flags = FL_BASE0, 2991 .num_ports = 8, 2992 .base_baud = 115200, 2993 .uart_offset = 8, 2994 }, 2995 [pbn_b0_1_921600] = { 2996 .flags = FL_BASE0, 2997 .num_ports = 1, 2998 .base_baud = 921600, 2999 .uart_offset = 8, 3000 }, 3001 [pbn_b0_2_921600] = { 3002 .flags = FL_BASE0, 3003 .num_ports = 2, 3004 .base_baud = 921600, 3005 .uart_offset = 8, 3006 }, 3007 [pbn_b0_4_921600] = { 3008 .flags = FL_BASE0, 3009 .num_ports = 4, 3010 .base_baud = 921600, 3011 .uart_offset = 8, 3012 }, 3013 3014 [pbn_b0_2_1130000] = { 3015 .flags = FL_BASE0, 3016 .num_ports = 2, 3017 .base_baud = 1130000, 3018 .uart_offset = 8, 3019 }, 3020 3021 [pbn_b0_4_1152000] = { 3022 .flags = FL_BASE0, 3023 .num_ports = 4, 3024 .base_baud = 1152000, 3025 .uart_offset = 8, 3026 }, 3027 3028 [pbn_b0_4_1250000] = { 3029 .flags = FL_BASE0, 3030 .num_ports = 4, 3031 .base_baud = 1250000, 3032 .uart_offset = 8, 3033 }, 3034 3035 [pbn_b0_2_1843200] = { 3036 .flags = FL_BASE0, 3037 .num_ports = 2, 3038 .base_baud = 1843200, 3039 .uart_offset = 8, 3040 }, 3041 [pbn_b0_4_1843200] = { 3042 .flags = FL_BASE0, 3043 .num_ports = 4, 3044 .base_baud = 1843200, 3045 .uart_offset = 8, 3046 }, 3047 3048 [pbn_b0_1_3906250] = { 3049 .flags = FL_BASE0, 3050 .num_ports = 1, 3051 .base_baud = 3906250, 3052 .uart_offset = 8, 3053 }, 3054 3055 [pbn_b0_bt_1_115200] = { 3056 .flags = FL_BASE0|FL_BASE_BARS, 3057 .num_ports = 1, 3058 .base_baud = 115200, 3059 .uart_offset = 8, 3060 }, 3061 [pbn_b0_bt_2_115200] = { 3062 .flags = FL_BASE0|FL_BASE_BARS, 3063 .num_ports = 2, 3064 .base_baud = 115200, 3065 .uart_offset = 8, 3066 }, 3067 [pbn_b0_bt_4_115200] = { 3068 .flags = FL_BASE0|FL_BASE_BARS, 3069 .num_ports = 4, 3070 .base_baud = 115200, 3071 .uart_offset = 8, 3072 }, 3073 [pbn_b0_bt_8_115200] = { 3074 .flags = FL_BASE0|FL_BASE_BARS, 3075 .num_ports = 8, 3076 .base_baud = 115200, 3077 .uart_offset = 8, 3078 }, 3079 3080 [pbn_b0_bt_1_460800] = { 3081 .flags = FL_BASE0|FL_BASE_BARS, 3082 .num_ports = 1, 3083 .base_baud = 460800, 3084 .uart_offset = 8, 3085 }, 3086 [pbn_b0_bt_2_460800] = { 3087 .flags = FL_BASE0|FL_BASE_BARS, 3088 .num_ports = 2, 3089 .base_baud = 460800, 3090 .uart_offset = 8, 3091 }, 3092 [pbn_b0_bt_4_460800] = { 3093 .flags = FL_BASE0|FL_BASE_BARS, 3094 .num_ports = 4, 3095 .base_baud = 460800, 3096 .uart_offset = 8, 3097 }, 3098 3099 [pbn_b0_bt_1_921600] = { 3100 .flags = FL_BASE0|FL_BASE_BARS, 3101 .num_ports = 1, 3102 .base_baud = 921600, 3103 .uart_offset = 8, 3104 }, 3105 [pbn_b0_bt_2_921600] = { 3106 .flags = FL_BASE0|FL_BASE_BARS, 3107 .num_ports = 2, 3108 .base_baud = 921600, 3109 .uart_offset = 8, 3110 }, 3111 [pbn_b0_bt_4_921600] = { 3112 .flags = FL_BASE0|FL_BASE_BARS, 3113 .num_ports = 4, 3114 .base_baud = 921600, 3115 .uart_offset = 8, 3116 }, 3117 [pbn_b0_bt_8_921600] = { 3118 .flags = FL_BASE0|FL_BASE_BARS, 3119 .num_ports = 8, 3120 .base_baud = 921600, 3121 .uart_offset = 8, 3122 }, 3123 3124 [pbn_b1_1_115200] = { 3125 .flags = FL_BASE1, 3126 .num_ports = 1, 3127 .base_baud = 115200, 3128 .uart_offset = 8, 3129 }, 3130 [pbn_b1_2_115200] = { 3131 .flags = FL_BASE1, 3132 .num_ports = 2, 3133 .base_baud = 115200, 3134 .uart_offset = 8, 3135 }, 3136 [pbn_b1_4_115200] = { 3137 .flags = FL_BASE1, 3138 .num_ports = 4, 3139 .base_baud = 115200, 3140 .uart_offset = 8, 3141 }, 3142 [pbn_b1_8_115200] = { 3143 .flags = FL_BASE1, 3144 .num_ports = 8, 3145 .base_baud = 115200, 3146 .uart_offset = 8, 3147 }, 3148 [pbn_b1_16_115200] = { 3149 .flags = FL_BASE1, 3150 .num_ports = 16, 3151 .base_baud = 115200, 3152 .uart_offset = 8, 3153 }, 3154 3155 [pbn_b1_1_921600] = { 3156 .flags = FL_BASE1, 3157 .num_ports = 1, 3158 .base_baud = 921600, 3159 .uart_offset = 8, 3160 }, 3161 [pbn_b1_2_921600] = { 3162 .flags = FL_BASE1, 3163 .num_ports = 2, 3164 .base_baud = 921600, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b1_4_921600] = { 3168 .flags = FL_BASE1, 3169 .num_ports = 4, 3170 .base_baud = 921600, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b1_8_921600] = { 3174 .flags = FL_BASE1, 3175 .num_ports = 8, 3176 .base_baud = 921600, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b1_2_1250000] = { 3180 .flags = FL_BASE1, 3181 .num_ports = 2, 3182 .base_baud = 1250000, 3183 .uart_offset = 8, 3184 }, 3185 3186 [pbn_b1_bt_1_115200] = { 3187 .flags = FL_BASE1|FL_BASE_BARS, 3188 .num_ports = 1, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 [pbn_b1_bt_2_115200] = { 3193 .flags = FL_BASE1|FL_BASE_BARS, 3194 .num_ports = 2, 3195 .base_baud = 115200, 3196 .uart_offset = 8, 3197 }, 3198 [pbn_b1_bt_4_115200] = { 3199 .flags = FL_BASE1|FL_BASE_BARS, 3200 .num_ports = 4, 3201 .base_baud = 115200, 3202 .uart_offset = 8, 3203 }, 3204 3205 [pbn_b1_bt_2_921600] = { 3206 .flags = FL_BASE1|FL_BASE_BARS, 3207 .num_ports = 2, 3208 .base_baud = 921600, 3209 .uart_offset = 8, 3210 }, 3211 3212 [pbn_b1_1_1382400] = { 3213 .flags = FL_BASE1, 3214 .num_ports = 1, 3215 .base_baud = 1382400, 3216 .uart_offset = 8, 3217 }, 3218 [pbn_b1_2_1382400] = { 3219 .flags = FL_BASE1, 3220 .num_ports = 2, 3221 .base_baud = 1382400, 3222 .uart_offset = 8, 3223 }, 3224 [pbn_b1_4_1382400] = { 3225 .flags = FL_BASE1, 3226 .num_ports = 4, 3227 .base_baud = 1382400, 3228 .uart_offset = 8, 3229 }, 3230 [pbn_b1_8_1382400] = { 3231 .flags = FL_BASE1, 3232 .num_ports = 8, 3233 .base_baud = 1382400, 3234 .uart_offset = 8, 3235 }, 3236 3237 [pbn_b2_1_115200] = { 3238 .flags = FL_BASE2, 3239 .num_ports = 1, 3240 .base_baud = 115200, 3241 .uart_offset = 8, 3242 }, 3243 [pbn_b2_2_115200] = { 3244 .flags = FL_BASE2, 3245 .num_ports = 2, 3246 .base_baud = 115200, 3247 .uart_offset = 8, 3248 }, 3249 [pbn_b2_4_115200] = { 3250 .flags = FL_BASE2, 3251 .num_ports = 4, 3252 .base_baud = 115200, 3253 .uart_offset = 8, 3254 }, 3255 [pbn_b2_8_115200] = { 3256 .flags = FL_BASE2, 3257 .num_ports = 8, 3258 .base_baud = 115200, 3259 .uart_offset = 8, 3260 }, 3261 3262 [pbn_b2_1_460800] = { 3263 .flags = FL_BASE2, 3264 .num_ports = 1, 3265 .base_baud = 460800, 3266 .uart_offset = 8, 3267 }, 3268 [pbn_b2_4_460800] = { 3269 .flags = FL_BASE2, 3270 .num_ports = 4, 3271 .base_baud = 460800, 3272 .uart_offset = 8, 3273 }, 3274 [pbn_b2_8_460800] = { 3275 .flags = FL_BASE2, 3276 .num_ports = 8, 3277 .base_baud = 460800, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b2_16_460800] = { 3281 .flags = FL_BASE2, 3282 .num_ports = 16, 3283 .base_baud = 460800, 3284 .uart_offset = 8, 3285 }, 3286 3287 [pbn_b2_1_921600] = { 3288 .flags = FL_BASE2, 3289 .num_ports = 1, 3290 .base_baud = 921600, 3291 .uart_offset = 8, 3292 }, 3293 [pbn_b2_4_921600] = { 3294 .flags = FL_BASE2, 3295 .num_ports = 4, 3296 .base_baud = 921600, 3297 .uart_offset = 8, 3298 }, 3299 [pbn_b2_8_921600] = { 3300 .flags = FL_BASE2, 3301 .num_ports = 8, 3302 .base_baud = 921600, 3303 .uart_offset = 8, 3304 }, 3305 3306 [pbn_b2_8_1152000] = { 3307 .flags = FL_BASE2, 3308 .num_ports = 8, 3309 .base_baud = 1152000, 3310 .uart_offset = 8, 3311 }, 3312 3313 [pbn_b2_bt_1_115200] = { 3314 .flags = FL_BASE2|FL_BASE_BARS, 3315 .num_ports = 1, 3316 .base_baud = 115200, 3317 .uart_offset = 8, 3318 }, 3319 [pbn_b2_bt_2_115200] = { 3320 .flags = FL_BASE2|FL_BASE_BARS, 3321 .num_ports = 2, 3322 .base_baud = 115200, 3323 .uart_offset = 8, 3324 }, 3325 [pbn_b2_bt_4_115200] = { 3326 .flags = FL_BASE2|FL_BASE_BARS, 3327 .num_ports = 4, 3328 .base_baud = 115200, 3329 .uart_offset = 8, 3330 }, 3331 3332 [pbn_b2_bt_2_921600] = { 3333 .flags = FL_BASE2|FL_BASE_BARS, 3334 .num_ports = 2, 3335 .base_baud = 921600, 3336 .uart_offset = 8, 3337 }, 3338 [pbn_b2_bt_4_921600] = { 3339 .flags = FL_BASE2|FL_BASE_BARS, 3340 .num_ports = 4, 3341 .base_baud = 921600, 3342 .uart_offset = 8, 3343 }, 3344 3345 [pbn_b3_2_115200] = { 3346 .flags = FL_BASE3, 3347 .num_ports = 2, 3348 .base_baud = 115200, 3349 .uart_offset = 8, 3350 }, 3351 [pbn_b3_4_115200] = { 3352 .flags = FL_BASE3, 3353 .num_ports = 4, 3354 .base_baud = 115200, 3355 .uart_offset = 8, 3356 }, 3357 [pbn_b3_8_115200] = { 3358 .flags = FL_BASE3, 3359 .num_ports = 8, 3360 .base_baud = 115200, 3361 .uart_offset = 8, 3362 }, 3363 3364 [pbn_b4_bt_2_921600] = { 3365 .flags = FL_BASE4, 3366 .num_ports = 2, 3367 .base_baud = 921600, 3368 .uart_offset = 8, 3369 }, 3370 [pbn_b4_bt_4_921600] = { 3371 .flags = FL_BASE4, 3372 .num_ports = 4, 3373 .base_baud = 921600, 3374 .uart_offset = 8, 3375 }, 3376 [pbn_b4_bt_8_921600] = { 3377 .flags = FL_BASE4, 3378 .num_ports = 8, 3379 .base_baud = 921600, 3380 .uart_offset = 8, 3381 }, 3382 3383 /* 3384 * Entries following this are board-specific. 3385 */ 3386 3387 /* 3388 * Panacom - IOMEM 3389 */ 3390 [pbn_panacom] = { 3391 .flags = FL_BASE2, 3392 .num_ports = 2, 3393 .base_baud = 921600, 3394 .uart_offset = 0x400, 3395 .reg_shift = 7, 3396 }, 3397 [pbn_panacom2] = { 3398 .flags = FL_BASE2|FL_BASE_BARS, 3399 .num_ports = 2, 3400 .base_baud = 921600, 3401 .uart_offset = 0x400, 3402 .reg_shift = 7, 3403 }, 3404 [pbn_panacom4] = { 3405 .flags = FL_BASE2|FL_BASE_BARS, 3406 .num_ports = 4, 3407 .base_baud = 921600, 3408 .uart_offset = 0x400, 3409 .reg_shift = 7, 3410 }, 3411 3412 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3413 [pbn_plx_romulus] = { 3414 .flags = FL_BASE2, 3415 .num_ports = 4, 3416 .base_baud = 921600, 3417 .uart_offset = 8 << 2, 3418 .reg_shift = 2, 3419 .first_offset = 0x03, 3420 }, 3421 3422 /* 3423 * This board uses the size of PCI Base region 0 to 3424 * signal now many ports are available 3425 */ 3426 [pbn_oxsemi] = { 3427 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3428 .num_ports = 32, 3429 .base_baud = 115200, 3430 .uart_offset = 8, 3431 }, 3432 [pbn_oxsemi_1_3906250] = { 3433 .flags = FL_BASE0, 3434 .num_ports = 1, 3435 .base_baud = 3906250, 3436 .uart_offset = 0x200, 3437 .first_offset = 0x1000, 3438 }, 3439 [pbn_oxsemi_2_3906250] = { 3440 .flags = FL_BASE0, 3441 .num_ports = 2, 3442 .base_baud = 3906250, 3443 .uart_offset = 0x200, 3444 .first_offset = 0x1000, 3445 }, 3446 [pbn_oxsemi_4_3906250] = { 3447 .flags = FL_BASE0, 3448 .num_ports = 4, 3449 .base_baud = 3906250, 3450 .uart_offset = 0x200, 3451 .first_offset = 0x1000, 3452 }, 3453 [pbn_oxsemi_8_3906250] = { 3454 .flags = FL_BASE0, 3455 .num_ports = 8, 3456 .base_baud = 3906250, 3457 .uart_offset = 0x200, 3458 .first_offset = 0x1000, 3459 }, 3460 3461 3462 /* 3463 * EKF addition for i960 Boards form EKF with serial port. 3464 * Max 256 ports. 3465 */ 3466 [pbn_intel_i960] = { 3467 .flags = FL_BASE0, 3468 .num_ports = 32, 3469 .base_baud = 921600, 3470 .uart_offset = 8 << 2, 3471 .reg_shift = 2, 3472 .first_offset = 0x10000, 3473 }, 3474 [pbn_sgi_ioc3] = { 3475 .flags = FL_BASE0|FL_NOIRQ, 3476 .num_ports = 1, 3477 .base_baud = 458333, 3478 .uart_offset = 8, 3479 .reg_shift = 0, 3480 .first_offset = 0x20178, 3481 }, 3482 3483 /* 3484 * Computone - uses IOMEM. 3485 */ 3486 [pbn_computone_4] = { 3487 .flags = FL_BASE0, 3488 .num_ports = 4, 3489 .base_baud = 921600, 3490 .uart_offset = 0x40, 3491 .reg_shift = 2, 3492 .first_offset = 0x200, 3493 }, 3494 [pbn_computone_6] = { 3495 .flags = FL_BASE0, 3496 .num_ports = 6, 3497 .base_baud = 921600, 3498 .uart_offset = 0x40, 3499 .reg_shift = 2, 3500 .first_offset = 0x200, 3501 }, 3502 [pbn_computone_8] = { 3503 .flags = FL_BASE0, 3504 .num_ports = 8, 3505 .base_baud = 921600, 3506 .uart_offset = 0x40, 3507 .reg_shift = 2, 3508 .first_offset = 0x200, 3509 }, 3510 [pbn_sbsxrsio] = { 3511 .flags = FL_BASE0, 3512 .num_ports = 8, 3513 .base_baud = 460800, 3514 .uart_offset = 256, 3515 .reg_shift = 4, 3516 }, 3517 /* 3518 * PA Semi PWRficient PA6T-1682M on-chip UART 3519 */ 3520 [pbn_pasemi_1682M] = { 3521 .flags = FL_BASE0, 3522 .num_ports = 1, 3523 .base_baud = 8333333, 3524 }, 3525 /* 3526 * National Instruments 843x 3527 */ 3528 [pbn_ni8430_16] = { 3529 .flags = FL_BASE0, 3530 .num_ports = 16, 3531 .base_baud = 3686400, 3532 .uart_offset = 0x10, 3533 .first_offset = 0x800, 3534 }, 3535 [pbn_ni8430_8] = { 3536 .flags = FL_BASE0, 3537 .num_ports = 8, 3538 .base_baud = 3686400, 3539 .uart_offset = 0x10, 3540 .first_offset = 0x800, 3541 }, 3542 [pbn_ni8430_4] = { 3543 .flags = FL_BASE0, 3544 .num_ports = 4, 3545 .base_baud = 3686400, 3546 .uart_offset = 0x10, 3547 .first_offset = 0x800, 3548 }, 3549 [pbn_ni8430_2] = { 3550 .flags = FL_BASE0, 3551 .num_ports = 2, 3552 .base_baud = 3686400, 3553 .uart_offset = 0x10, 3554 .first_offset = 0x800, 3555 }, 3556 /* 3557 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3558 */ 3559 [pbn_ADDIDATA_PCIe_1_3906250] = { 3560 .flags = FL_BASE0, 3561 .num_ports = 1, 3562 .base_baud = 3906250, 3563 .uart_offset = 0x200, 3564 .first_offset = 0x1000, 3565 }, 3566 [pbn_ADDIDATA_PCIe_2_3906250] = { 3567 .flags = FL_BASE0, 3568 .num_ports = 2, 3569 .base_baud = 3906250, 3570 .uart_offset = 0x200, 3571 .first_offset = 0x1000, 3572 }, 3573 [pbn_ADDIDATA_PCIe_4_3906250] = { 3574 .flags = FL_BASE0, 3575 .num_ports = 4, 3576 .base_baud = 3906250, 3577 .uart_offset = 0x200, 3578 .first_offset = 0x1000, 3579 }, 3580 [pbn_ADDIDATA_PCIe_8_3906250] = { 3581 .flags = FL_BASE0, 3582 .num_ports = 8, 3583 .base_baud = 3906250, 3584 .uart_offset = 0x200, 3585 .first_offset = 0x1000, 3586 }, 3587 [pbn_ce4100_1_115200] = { 3588 .flags = FL_BASE_BARS, 3589 .num_ports = 2, 3590 .base_baud = 921600, 3591 .reg_shift = 2, 3592 }, 3593 [pbn_omegapci] = { 3594 .flags = FL_BASE0, 3595 .num_ports = 8, 3596 .base_baud = 115200, 3597 .uart_offset = 0x200, 3598 }, 3599 [pbn_NETMOS9900_2s_115200] = { 3600 .flags = FL_BASE0, 3601 .num_ports = 2, 3602 .base_baud = 115200, 3603 }, 3604 [pbn_brcm_trumanage] = { 3605 .flags = FL_BASE0, 3606 .num_ports = 1, 3607 .reg_shift = 2, 3608 .base_baud = 115200, 3609 }, 3610 [pbn_fintek_4] = { 3611 .num_ports = 4, 3612 .uart_offset = 8, 3613 .base_baud = 115200, 3614 .first_offset = 0x40, 3615 }, 3616 [pbn_fintek_8] = { 3617 .num_ports = 8, 3618 .uart_offset = 8, 3619 .base_baud = 115200, 3620 .first_offset = 0x40, 3621 }, 3622 [pbn_fintek_12] = { 3623 .num_ports = 12, 3624 .uart_offset = 8, 3625 .base_baud = 115200, 3626 .first_offset = 0x40, 3627 }, 3628 [pbn_fintek_F81504A] = { 3629 .num_ports = 4, 3630 .uart_offset = 8, 3631 .base_baud = 115200, 3632 }, 3633 [pbn_fintek_F81508A] = { 3634 .num_ports = 8, 3635 .uart_offset = 8, 3636 .base_baud = 115200, 3637 }, 3638 [pbn_fintek_F81512A] = { 3639 .num_ports = 12, 3640 .uart_offset = 8, 3641 .base_baud = 115200, 3642 }, 3643 [pbn_wch382_2] = { 3644 .flags = FL_BASE0, 3645 .num_ports = 2, 3646 .base_baud = 115200, 3647 .uart_offset = 8, 3648 .first_offset = 0xC0, 3649 }, 3650 [pbn_wch384_4] = { 3651 .flags = FL_BASE0, 3652 .num_ports = 4, 3653 .base_baud = 115200, 3654 .uart_offset = 8, 3655 .first_offset = 0xC0, 3656 }, 3657 [pbn_wch384_8] = { 3658 .flags = FL_BASE0, 3659 .num_ports = 8, 3660 .base_baud = 115200, 3661 .uart_offset = 8, 3662 .first_offset = 0x00, 3663 }, 3664 /* 3665 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3666 */ 3667 [pbn_pericom_PI7C9X7951] = { 3668 .flags = FL_BASE0, 3669 .num_ports = 1, 3670 .base_baud = 921600, 3671 .uart_offset = 0x8, 3672 }, 3673 [pbn_pericom_PI7C9X7952] = { 3674 .flags = FL_BASE0, 3675 .num_ports = 2, 3676 .base_baud = 921600, 3677 .uart_offset = 0x8, 3678 }, 3679 [pbn_pericom_PI7C9X7954] = { 3680 .flags = FL_BASE0, 3681 .num_ports = 4, 3682 .base_baud = 921600, 3683 .uart_offset = 0x8, 3684 }, 3685 [pbn_pericom_PI7C9X7958] = { 3686 .flags = FL_BASE0, 3687 .num_ports = 8, 3688 .base_baud = 921600, 3689 .uart_offset = 0x8, 3690 }, 3691 [pbn_sunix_pci_1s] = { 3692 .num_ports = 1, 3693 .base_baud = 921600, 3694 .uart_offset = 0x8, 3695 }, 3696 [pbn_sunix_pci_2s] = { 3697 .num_ports = 2, 3698 .base_baud = 921600, 3699 .uart_offset = 0x8, 3700 }, 3701 [pbn_sunix_pci_4s] = { 3702 .num_ports = 4, 3703 .base_baud = 921600, 3704 .uart_offset = 0x8, 3705 }, 3706 [pbn_sunix_pci_8s] = { 3707 .num_ports = 8, 3708 .base_baud = 921600, 3709 .uart_offset = 0x8, 3710 }, 3711 [pbn_sunix_pci_16s] = { 3712 .num_ports = 16, 3713 .base_baud = 921600, 3714 .uart_offset = 0x8, 3715 }, 3716 [pbn_titan_1_4000000] = { 3717 .flags = FL_BASE0, 3718 .num_ports = 1, 3719 .base_baud = 4000000, 3720 .uart_offset = 0x200, 3721 .first_offset = 0x1000, 3722 }, 3723 [pbn_titan_2_4000000] = { 3724 .flags = FL_BASE0, 3725 .num_ports = 2, 3726 .base_baud = 4000000, 3727 .uart_offset = 0x200, 3728 .first_offset = 0x1000, 3729 }, 3730 [pbn_titan_4_4000000] = { 3731 .flags = FL_BASE0, 3732 .num_ports = 4, 3733 .base_baud = 4000000, 3734 .uart_offset = 0x200, 3735 .first_offset = 0x1000, 3736 }, 3737 [pbn_titan_8_4000000] = { 3738 .flags = FL_BASE0, 3739 .num_ports = 8, 3740 .base_baud = 4000000, 3741 .uart_offset = 0x200, 3742 .first_offset = 0x1000, 3743 }, 3744 [pbn_moxa8250_2p] = { 3745 .flags = FL_BASE1, 3746 .num_ports = 2, 3747 .base_baud = 921600, 3748 .uart_offset = 0x200, 3749 }, 3750 [pbn_moxa8250_4p] = { 3751 .flags = FL_BASE1, 3752 .num_ports = 4, 3753 .base_baud = 921600, 3754 .uart_offset = 0x200, 3755 }, 3756 [pbn_moxa8250_8p] = { 3757 .flags = FL_BASE1, 3758 .num_ports = 8, 3759 .base_baud = 921600, 3760 .uart_offset = 0x200, 3761 }, 3762}; 3763 3764static const struct pci_device_id blacklist[] = { 3765 /* softmodems */ 3766 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3767 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3768 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3769 3770 /* multi-io cards handled by parport_serial */ 3771 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3772 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3773 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3774 3775 /* Intel platforms with MID UART */ 3776 { PCI_VDEVICE(INTEL, 0x081b), }, 3777 { PCI_VDEVICE(INTEL, 0x081c), }, 3778 { PCI_VDEVICE(INTEL, 0x081d), }, 3779 { PCI_VDEVICE(INTEL, 0x1191), }, 3780 { PCI_VDEVICE(INTEL, 0x18d8), }, 3781 { PCI_VDEVICE(INTEL, 0x19d8), }, 3782 3783 /* Intel platforms with DesignWare UART */ 3784 { PCI_VDEVICE(INTEL, 0x0936), }, 3785 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3786 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3787 { PCI_VDEVICE(INTEL, 0x228a), }, 3788 { PCI_VDEVICE(INTEL, 0x228c), }, 3789 { PCI_VDEVICE(INTEL, 0x4b96), }, 3790 { PCI_VDEVICE(INTEL, 0x4b97), }, 3791 { PCI_VDEVICE(INTEL, 0x4b98), }, 3792 { PCI_VDEVICE(INTEL, 0x4b99), }, 3793 { PCI_VDEVICE(INTEL, 0x4b9a), }, 3794 { PCI_VDEVICE(INTEL, 0x4b9b), }, 3795 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3796 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3797 3798 /* Exar devices */ 3799 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3800 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3801 3802 /* End of the black list */ 3803 { } 3804}; 3805 3806static int serial_pci_is_class_communication(struct pci_dev *dev) 3807{ 3808 /* 3809 * If it is not a communications device or the programming 3810 * interface is greater than 6, give up. 3811 */ 3812 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3813 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3814 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3815 (dev->class & 0xff) > 6) 3816 return -ENODEV; 3817 3818 return 0; 3819} 3820 3821/* 3822 * Given a complete unknown PCI device, try to use some heuristics to 3823 * guess what the configuration might be, based on the pitiful PCI 3824 * serial specs. Returns 0 on success, -ENODEV on failure. 3825 */ 3826static int 3827serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3828{ 3829 int num_iomem, num_port, first_port = -1, i; 3830 int rc; 3831 3832 rc = serial_pci_is_class_communication(dev); 3833 if (rc) 3834 return rc; 3835 3836 /* 3837 * Should we try to make guesses for multiport serial devices later? 3838 */ 3839 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3840 return -ENODEV; 3841 3842 num_iomem = num_port = 0; 3843 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3844 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3845 num_port++; 3846 if (first_port == -1) 3847 first_port = i; 3848 } 3849 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3850 num_iomem++; 3851 } 3852 3853 /* 3854 * If there is 1 or 0 iomem regions, and exactly one port, 3855 * use it. We guess the number of ports based on the IO 3856 * region size. 3857 */ 3858 if (num_iomem <= 1 && num_port == 1) { 3859 board->flags = first_port; 3860 board->num_ports = pci_resource_len(dev, first_port) / 8; 3861 return 0; 3862 } 3863 3864 /* 3865 * Now guess if we've got a board which indexes by BARs. 3866 * Each IO BAR should be 8 bytes, and they should follow 3867 * consecutively. 3868 */ 3869 first_port = -1; 3870 num_port = 0; 3871 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3872 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3873 pci_resource_len(dev, i) == 8 && 3874 (first_port == -1 || (first_port + num_port) == i)) { 3875 num_port++; 3876 if (first_port == -1) 3877 first_port = i; 3878 } 3879 } 3880 3881 if (num_port > 1) { 3882 board->flags = first_port | FL_BASE_BARS; 3883 board->num_ports = num_port; 3884 return 0; 3885 } 3886 3887 return -ENODEV; 3888} 3889 3890static inline int 3891serial_pci_matches(const struct pciserial_board *board, 3892 const struct pciserial_board *guessed) 3893{ 3894 return 3895 board->num_ports == guessed->num_ports && 3896 board->base_baud == guessed->base_baud && 3897 board->uart_offset == guessed->uart_offset && 3898 board->reg_shift == guessed->reg_shift && 3899 board->first_offset == guessed->first_offset; 3900} 3901 3902struct serial_private * 3903pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3904{ 3905 struct uart_8250_port uart; 3906 struct serial_private *priv; 3907 struct pci_serial_quirk *quirk; 3908 int rc, nr_ports, i; 3909 3910 nr_ports = board->num_ports; 3911 3912 /* 3913 * Find an init and setup quirks. 3914 */ 3915 quirk = find_quirk(dev); 3916 3917 /* 3918 * Run the new-style initialization function. 3919 * The initialization function returns: 3920 * <0 - error 3921 * 0 - use board->num_ports 3922 * >0 - number of ports 3923 */ 3924 if (quirk->init) { 3925 rc = quirk->init(dev); 3926 if (rc < 0) { 3927 priv = ERR_PTR(rc); 3928 goto err_out; 3929 } 3930 if (rc) 3931 nr_ports = rc; 3932 } 3933 3934 priv = kzalloc(sizeof(struct serial_private) + 3935 sizeof(unsigned int) * nr_ports, 3936 GFP_KERNEL); 3937 if (!priv) { 3938 priv = ERR_PTR(-ENOMEM); 3939 goto err_deinit; 3940 } 3941 3942 priv->dev = dev; 3943 priv->quirk = quirk; 3944 3945 memset(&uart, 0, sizeof(uart)); 3946 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3947 uart.port.uartclk = board->base_baud * 16; 3948 3949 if (board->flags & FL_NOIRQ) { 3950 uart.port.irq = 0; 3951 } else { 3952 if (pci_match_id(pci_use_msi, dev)) { 3953 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3954 pci_set_master(dev); 3955 uart.port.flags &= ~UPF_SHARE_IRQ; 3956 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3957 } else { 3958 pci_dbg(dev, "Using legacy interrupts\n"); 3959 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3960 } 3961 if (rc < 0) { 3962 kfree(priv); 3963 priv = ERR_PTR(rc); 3964 goto err_deinit; 3965 } 3966 3967 uart.port.irq = pci_irq_vector(dev, 0); 3968 } 3969 3970 uart.port.dev = &dev->dev; 3971 3972 for (i = 0; i < nr_ports; i++) { 3973 if (quirk->setup(priv, board, &uart, i)) 3974 break; 3975 3976 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3977 uart.port.iobase, uart.port.irq, uart.port.iotype); 3978 3979 priv->line[i] = serial8250_register_8250_port(&uart); 3980 if (priv->line[i] < 0) { 3981 pci_err(dev, 3982 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3983 uart.port.iobase, uart.port.irq, 3984 uart.port.iotype, priv->line[i]); 3985 break; 3986 } 3987 } 3988 priv->nr = i; 3989 priv->board = board; 3990 return priv; 3991 3992err_deinit: 3993 if (quirk->exit) 3994 quirk->exit(dev); 3995err_out: 3996 return priv; 3997} 3998EXPORT_SYMBOL_GPL(pciserial_init_ports); 3999 4000static void pciserial_detach_ports(struct serial_private *priv) 4001{ 4002 struct pci_serial_quirk *quirk; 4003 int i; 4004 4005 for (i = 0; i < priv->nr; i++) 4006 serial8250_unregister_port(priv->line[i]); 4007 4008 /* 4009 * Find the exit quirks. 4010 */ 4011 quirk = find_quirk(priv->dev); 4012 if (quirk->exit) 4013 quirk->exit(priv->dev); 4014} 4015 4016void pciserial_remove_ports(struct serial_private *priv) 4017{ 4018 pciserial_detach_ports(priv); 4019 kfree(priv); 4020} 4021EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4022 4023void pciserial_suspend_ports(struct serial_private *priv) 4024{ 4025 int i; 4026 4027 for (i = 0; i < priv->nr; i++) 4028 if (priv->line[i] >= 0) 4029 serial8250_suspend_port(priv->line[i]); 4030 4031 /* 4032 * Ensure that every init quirk is properly torn down 4033 */ 4034 if (priv->quirk->exit) 4035 priv->quirk->exit(priv->dev); 4036} 4037EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4038 4039void pciserial_resume_ports(struct serial_private *priv) 4040{ 4041 int i; 4042 4043 /* 4044 * Ensure that the board is correctly configured. 4045 */ 4046 if (priv->quirk->init) 4047 priv->quirk->init(priv->dev); 4048 4049 for (i = 0; i < priv->nr; i++) 4050 if (priv->line[i] >= 0) 4051 serial8250_resume_port(priv->line[i]); 4052} 4053EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4054 4055/* 4056 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4057 * to the arrangement of serial ports on a PCI card. 4058 */ 4059static int 4060pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4061{ 4062 struct pci_serial_quirk *quirk; 4063 struct serial_private *priv; 4064 const struct pciserial_board *board; 4065 const struct pci_device_id *exclude; 4066 struct pciserial_board tmp; 4067 int rc; 4068 4069 quirk = find_quirk(dev); 4070 if (quirk->probe) { 4071 rc = quirk->probe(dev); 4072 if (rc) 4073 return rc; 4074 } 4075 4076 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4077 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4078 return -EINVAL; 4079 } 4080 4081 board = &pci_boards[ent->driver_data]; 4082 4083 exclude = pci_match_id(blacklist, dev); 4084 if (exclude) 4085 return -ENODEV; 4086 4087 rc = pcim_enable_device(dev); 4088 pci_save_state(dev); 4089 if (rc) 4090 return rc; 4091 4092 if (ent->driver_data == pbn_default) { 4093 /* 4094 * Use a copy of the pci_board entry for this; 4095 * avoid changing entries in the table. 4096 */ 4097 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4098 board = &tmp; 4099 4100 /* 4101 * We matched one of our class entries. Try to 4102 * determine the parameters of this board. 4103 */ 4104 rc = serial_pci_guess_board(dev, &tmp); 4105 if (rc) 4106 return rc; 4107 } else { 4108 /* 4109 * We matched an explicit entry. If we are able to 4110 * detect this boards settings with our heuristic, 4111 * then we no longer need this entry. 4112 */ 4113 memcpy(&tmp, &pci_boards[pbn_default], 4114 sizeof(struct pciserial_board)); 4115 rc = serial_pci_guess_board(dev, &tmp); 4116 if (rc == 0 && serial_pci_matches(board, &tmp)) 4117 moan_device("Redundant entry in serial pci_table.", 4118 dev); 4119 } 4120 4121 priv = pciserial_init_ports(dev, board); 4122 if (IS_ERR(priv)) 4123 return PTR_ERR(priv); 4124 4125 pci_set_drvdata(dev, priv); 4126 return 0; 4127} 4128 4129static void pciserial_remove_one(struct pci_dev *dev) 4130{ 4131 struct serial_private *priv = pci_get_drvdata(dev); 4132 4133 pciserial_remove_ports(priv); 4134} 4135 4136#ifdef CONFIG_PM_SLEEP 4137static int pciserial_suspend_one(struct device *dev) 4138{ 4139 struct serial_private *priv = dev_get_drvdata(dev); 4140 4141 if (priv) 4142 pciserial_suspend_ports(priv); 4143 4144 return 0; 4145} 4146 4147static int pciserial_resume_one(struct device *dev) 4148{ 4149 struct pci_dev *pdev = to_pci_dev(dev); 4150 struct serial_private *priv = pci_get_drvdata(pdev); 4151 int err; 4152 4153 if (priv) { 4154 /* 4155 * The device may have been disabled. Re-enable it. 4156 */ 4157 err = pci_enable_device(pdev); 4158 /* FIXME: We cannot simply error out here */ 4159 if (err) 4160 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4161 pciserial_resume_ports(priv); 4162 } 4163 return 0; 4164} 4165#endif 4166 4167static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4168 pciserial_resume_one); 4169 4170static const struct pci_device_id serial_pci_tbl[] = { 4171 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4172 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4173 pbn_b0_4_921600 }, 4174 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4175 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4176 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4177 pbn_b2_8_921600 }, 4178 /* Advantech also use 0x3618 and 0xf618 */ 4179 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4180 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4181 pbn_b0_4_921600 }, 4182 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4183 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4184 pbn_b0_4_921600 }, 4185 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4186 PCI_SUBVENDOR_ID_CONNECT_TECH, 4187 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4188 pbn_b1_8_1382400 }, 4189 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4190 PCI_SUBVENDOR_ID_CONNECT_TECH, 4191 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4192 pbn_b1_4_1382400 }, 4193 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4194 PCI_SUBVENDOR_ID_CONNECT_TECH, 4195 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4196 pbn_b1_2_1382400 }, 4197 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4198 PCI_SUBVENDOR_ID_CONNECT_TECH, 4199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4200 pbn_b1_8_1382400 }, 4201 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4202 PCI_SUBVENDOR_ID_CONNECT_TECH, 4203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4204 pbn_b1_4_1382400 }, 4205 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4206 PCI_SUBVENDOR_ID_CONNECT_TECH, 4207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4208 pbn_b1_2_1382400 }, 4209 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4210 PCI_SUBVENDOR_ID_CONNECT_TECH, 4211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4212 pbn_b1_8_921600 }, 4213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4214 PCI_SUBVENDOR_ID_CONNECT_TECH, 4215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4216 pbn_b1_8_921600 }, 4217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4218 PCI_SUBVENDOR_ID_CONNECT_TECH, 4219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4220 pbn_b1_4_921600 }, 4221 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4222 PCI_SUBVENDOR_ID_CONNECT_TECH, 4223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4224 pbn_b1_4_921600 }, 4225 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4226 PCI_SUBVENDOR_ID_CONNECT_TECH, 4227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4228 pbn_b1_2_921600 }, 4229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4230 PCI_SUBVENDOR_ID_CONNECT_TECH, 4231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4232 pbn_b1_8_921600 }, 4233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4234 PCI_SUBVENDOR_ID_CONNECT_TECH, 4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4236 pbn_b1_8_921600 }, 4237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4238 PCI_SUBVENDOR_ID_CONNECT_TECH, 4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4240 pbn_b1_4_921600 }, 4241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4242 PCI_SUBVENDOR_ID_CONNECT_TECH, 4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4244 pbn_b1_2_1250000 }, 4245 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4246 PCI_SUBVENDOR_ID_CONNECT_TECH, 4247 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4248 pbn_b0_2_1843200 }, 4249 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4250 PCI_SUBVENDOR_ID_CONNECT_TECH, 4251 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4252 pbn_b0_4_1843200 }, 4253 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4254 PCI_VENDOR_ID_AFAVLAB, 4255 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4256 pbn_b0_4_1152000 }, 4257 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4259 pbn_b2_bt_1_115200 }, 4260 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4262 pbn_b2_bt_2_115200 }, 4263 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4265 pbn_b2_bt_4_115200 }, 4266 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4268 pbn_b2_bt_2_115200 }, 4269 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4271 pbn_b2_bt_4_115200 }, 4272 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4274 pbn_b2_8_115200 }, 4275 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4277 pbn_b2_8_460800 }, 4278 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4280 pbn_b2_8_115200 }, 4281 4282 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4284 pbn_b2_bt_2_115200 }, 4285 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4287 pbn_b2_bt_2_921600 }, 4288 /* 4289 * VScom SPCOM800, from sl@s.pl 4290 */ 4291 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_b2_8_921600 }, 4294 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_b2_4_921600 }, 4297 /* Unknown card - subdevice 0x1584 */ 4298 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4299 PCI_VENDOR_ID_PLX, 4300 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4301 pbn_b2_4_115200 }, 4302 /* Unknown card - subdevice 0x1588 */ 4303 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4304 PCI_VENDOR_ID_PLX, 4305 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4306 pbn_b2_8_115200 }, 4307 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4308 PCI_SUBVENDOR_ID_KEYSPAN, 4309 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4310 pbn_panacom }, 4311 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_panacom4 }, 4314 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_panacom2 }, 4317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4318 PCI_VENDOR_ID_ESDGMBH, 4319 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4320 pbn_b2_4_115200 }, 4321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4322 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4323 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4324 pbn_b2_4_460800 }, 4325 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4326 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4327 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4328 pbn_b2_8_460800 }, 4329 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4330 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4331 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4332 pbn_b2_16_460800 }, 4333 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4334 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4335 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4336 pbn_b2_16_460800 }, 4337 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4338 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4339 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4340 pbn_b2_4_460800 }, 4341 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4342 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4343 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4344 pbn_b2_8_460800 }, 4345 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4346 PCI_SUBVENDOR_ID_EXSYS, 4347 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4348 pbn_b2_4_115200 }, 4349 /* 4350 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4351 * (Exoray@isys.ca) 4352 */ 4353 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4354 0x10b5, 0x106a, 0, 0, 4355 pbn_plx_romulus }, 4356 /* 4357 * Quatech cards. These actually have configurable clocks but for 4358 * now we just use the default. 4359 * 4360 * 100 series are RS232, 200 series RS422, 4361 */ 4362 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b1_4_115200 }, 4365 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4367 pbn_b1_2_115200 }, 4368 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4370 pbn_b2_2_115200 }, 4371 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4373 pbn_b1_2_115200 }, 4374 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b2_2_115200 }, 4377 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b1_4_115200 }, 4380 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b1_8_115200 }, 4383 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4385 pbn_b1_8_115200 }, 4386 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_b1_4_115200 }, 4389 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b1_2_115200 }, 4392 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b1_4_115200 }, 4395 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4397 pbn_b1_2_115200 }, 4398 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4400 pbn_b2_4_115200 }, 4401 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b2_2_115200 }, 4404 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b2_1_115200 }, 4407 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b2_4_115200 }, 4410 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b2_2_115200 }, 4413 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b2_1_115200 }, 4416 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_b0_8_115200 }, 4419 4420 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4421 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4422 0, 0, 4423 pbn_b0_4_921600 }, 4424 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4425 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4426 0, 0, 4427 pbn_b0_4_1152000 }, 4428 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_b0_bt_2_921600 }, 4431 4432 /* 4433 * The below card is a little controversial since it is the 4434 * subject of a PCI vendor/device ID clash. (See 4435 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4436 * For now just used the hex ID 0x950a. 4437 */ 4438 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4439 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4440 0, 0, pbn_b0_2_115200 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4442 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4443 0, 0, pbn_b0_2_115200 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_b0_2_1130000 }, 4447 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4448 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4449 pbn_b0_1_921600 }, 4450 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b0_4_115200 }, 4453 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_b0_bt_2_921600 }, 4456 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_b2_8_1152000 }, 4459 4460 /* 4461 * Oxford Semiconductor Inc. Tornado PCI express device range. 4462 */ 4463 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_b0_1_3906250 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_b0_1_3906250 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_3906250 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_1_3906250 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_b0_1_3906250 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_b0_1_3906250 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_3906250 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_3906250 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_b0_1_3906250 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_b0_1_3906250 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_b0_1_3906250 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_b0_1_3906250 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_2_3906250 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_2_3906250 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_4_3906250 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_4_3906250 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_8_3906250 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_8_3906250 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_3906250 }, 4520 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_oxsemi_1_3906250 }, 4523 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_oxsemi_1_3906250 }, 4526 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_oxsemi_1_3906250 }, 4529 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_oxsemi_1_3906250 }, 4532 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4534 pbn_oxsemi_1_3906250 }, 4535 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4537 pbn_oxsemi_1_3906250 }, 4538 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4540 pbn_oxsemi_1_3906250 }, 4541 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4543 pbn_oxsemi_1_3906250 }, 4544 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4546 pbn_oxsemi_1_3906250 }, 4547 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4549 pbn_oxsemi_1_3906250 }, 4550 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4552 pbn_oxsemi_1_3906250 }, 4553 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4555 pbn_oxsemi_1_3906250 }, 4556 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4558 pbn_oxsemi_1_3906250 }, 4559 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4561 pbn_oxsemi_1_3906250 }, 4562 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_oxsemi_1_3906250 }, 4565 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4567 pbn_oxsemi_1_3906250 }, 4568 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4570 pbn_oxsemi_1_3906250 }, 4571 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_oxsemi_1_3906250 }, 4574 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_oxsemi_1_3906250 }, 4577 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_oxsemi_1_3906250 }, 4580 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_oxsemi_1_3906250 }, 4583 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_oxsemi_1_3906250 }, 4586 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_oxsemi_1_3906250 }, 4589 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_oxsemi_1_3906250 }, 4592 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_oxsemi_1_3906250 }, 4595 /* 4596 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4597 */ 4598 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4599 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4600 pbn_oxsemi_1_3906250 }, 4601 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4602 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4603 pbn_oxsemi_2_3906250 }, 4604 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4605 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4606 pbn_oxsemi_4_3906250 }, 4607 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4608 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4609 pbn_oxsemi_8_3906250 }, 4610 4611 /* 4612 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4613 */ 4614 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4615 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4616 pbn_oxsemi_2_3906250 }, 4617 /* 4618 * EndRun Technologies. PCI express device range. 4619 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4620 */ 4621 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4623 pbn_oxsemi_2_3906250 }, 4624 4625 /* 4626 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4627 * from skokodyn@yahoo.com 4628 */ 4629 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4630 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4631 pbn_sbsxrsio }, 4632 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4633 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4634 pbn_sbsxrsio }, 4635 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4636 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4637 pbn_sbsxrsio }, 4638 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4639 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4640 pbn_sbsxrsio }, 4641 4642 /* 4643 * Digitan DS560-558, from jimd@esoft.com 4644 */ 4645 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4647 pbn_b1_1_115200 }, 4648 4649 /* 4650 * Titan Electronic cards 4651 * The 400L and 800L have a custom setup quirk. 4652 */ 4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b0_1_921600 }, 4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b0_2_921600 }, 4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_4_921600 }, 4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_4_921600 }, 4665 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b1_1_921600 }, 4668 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b1_bt_2_921600 }, 4671 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_bt_4_921600 }, 4674 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b0_bt_8_921600 }, 4677 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b4_bt_2_921600 }, 4680 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b4_bt_4_921600 }, 4683 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b4_bt_8_921600 }, 4686 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b0_4_921600 }, 4689 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b0_4_921600 }, 4692 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b0_4_921600 }, 4695 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_titan_1_4000000 }, 4698 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_titan_2_4000000 }, 4701 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_titan_4_4000000 }, 4704 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_titan_8_4000000 }, 4707 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_titan_2_4000000 }, 4710 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_titan_2_4000000 }, 4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_b0_bt_2_921600 }, 4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_b0_4_921600 }, 4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_b0_4_921600 }, 4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b0_4_921600 }, 4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b0_4_921600 }, 4728 4729 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4731 pbn_b2_1_460800 }, 4732 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4734 pbn_b2_1_460800 }, 4735 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4737 pbn_b2_1_460800 }, 4738 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4740 pbn_b2_bt_2_921600 }, 4741 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_b2_bt_2_921600 }, 4744 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_b2_bt_2_921600 }, 4747 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4749 pbn_b2_bt_4_921600 }, 4750 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4752 pbn_b2_bt_4_921600 }, 4753 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4755 pbn_b2_bt_4_921600 }, 4756 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4758 pbn_b0_1_921600 }, 4759 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_b0_1_921600 }, 4762 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b0_1_921600 }, 4765 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4767 pbn_b0_bt_2_921600 }, 4768 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b0_bt_2_921600 }, 4771 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4773 pbn_b0_bt_2_921600 }, 4774 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4776 pbn_b0_bt_4_921600 }, 4777 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b0_bt_4_921600 }, 4780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_4_921600 }, 4783 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b0_bt_8_921600 }, 4786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4788 pbn_b0_bt_8_921600 }, 4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4791 pbn_b0_bt_8_921600 }, 4792 4793 /* 4794 * Computone devices submitted by Doug McNash dmcnash@computone.com 4795 */ 4796 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4797 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4798 0, 0, pbn_computone_4 }, 4799 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4800 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4801 0, 0, pbn_computone_8 }, 4802 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4803 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4804 0, 0, pbn_computone_6 }, 4805 4806 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4808 pbn_oxsemi }, 4809 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4810 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4811 pbn_b0_bt_1_921600 }, 4812 4813 /* 4814 * Sunix PCI serial boards 4815 */ 4816 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4817 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4818 pbn_sunix_pci_1s }, 4819 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4820 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4821 pbn_sunix_pci_2s }, 4822 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4823 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4824 pbn_sunix_pci_4s }, 4825 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4826 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4827 pbn_sunix_pci_4s }, 4828 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4829 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4830 pbn_sunix_pci_8s }, 4831 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4832 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4833 pbn_sunix_pci_8s }, 4834 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4835 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4836 pbn_sunix_pci_16s }, 4837 4838 /* 4839 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4840 */ 4841 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4843 pbn_b0_bt_8_115200 }, 4844 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4846 pbn_b0_bt_8_115200 }, 4847 4848 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4850 pbn_b0_bt_2_115200 }, 4851 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4853 pbn_b0_bt_2_115200 }, 4854 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b0_bt_2_115200 }, 4857 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b0_bt_2_115200 }, 4860 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_bt_2_115200 }, 4863 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_bt_4_460800 }, 4866 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_b0_bt_4_460800 }, 4869 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_bt_2_460800 }, 4872 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4874 pbn_b0_bt_2_460800 }, 4875 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4877 pbn_b0_bt_2_460800 }, 4878 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_b0_bt_1_115200 }, 4881 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b0_bt_1_460800 }, 4884 4885 /* 4886 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4887 * Cards are identified by their subsystem vendor IDs, which 4888 * (in hex) match the model number. 4889 * 4890 * Note that JC140x are RS422/485 cards which require ox950 4891 * ACR = 0x10, and as such are not currently fully supported. 4892 */ 4893 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4894 0x1204, 0x0004, 0, 0, 4895 pbn_b0_4_921600 }, 4896 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4897 0x1208, 0x0004, 0, 0, 4898 pbn_b0_4_921600 }, 4899/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4900 0x1402, 0x0002, 0, 0, 4901 pbn_b0_2_921600 }, */ 4902/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4903 0x1404, 0x0004, 0, 0, 4904 pbn_b0_4_921600 }, */ 4905 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4906 0x1208, 0x0004, 0, 0, 4907 pbn_b0_4_921600 }, 4908 4909 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4910 0x1204, 0x0004, 0, 0, 4911 pbn_b0_4_921600 }, 4912 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4913 0x1208, 0x0004, 0, 0, 4914 pbn_b0_4_921600 }, 4915 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4916 0x1208, 0x0004, 0, 0, 4917 pbn_b0_4_921600 }, 4918 /* 4919 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4920 */ 4921 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4923 pbn_b1_1_1382400 }, 4924 4925 /* 4926 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4927 */ 4928 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4930 pbn_b1_1_1382400 }, 4931 4932 /* 4933 * RAStel 2 port modem, gerg@moreton.com.au 4934 */ 4935 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4937 pbn_b2_bt_2_115200 }, 4938 4939 /* 4940 * EKF addition for i960 Boards form EKF with serial port 4941 */ 4942 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4943 0xE4BF, PCI_ANY_ID, 0, 0, 4944 pbn_intel_i960 }, 4945 4946 /* 4947 * Xircom Cardbus/Ethernet combos 4948 */ 4949 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4951 pbn_b0_1_115200 }, 4952 /* 4953 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4954 */ 4955 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4957 pbn_b0_1_115200 }, 4958 4959 /* 4960 * Untested PCI modems, sent in from various folks... 4961 */ 4962 4963 /* 4964 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4965 */ 4966 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4967 0x1048, 0x1500, 0, 0, 4968 pbn_b1_1_115200 }, 4969 4970 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4971 0xFF00, 0, 0, 0, 4972 pbn_sgi_ioc3 }, 4973 4974 /* 4975 * HP Diva card 4976 */ 4977 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4978 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4979 pbn_b1_1_115200 }, 4980 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_b0_5_115200 }, 4983 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_b2_1_115200 }, 4986 /* HPE PCI serial device */ 4987 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4989 pbn_b1_1_115200 }, 4990 4991 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4993 pbn_b3_2_115200 }, 4994 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4996 pbn_b3_4_115200 }, 4997 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4999 pbn_b3_8_115200 }, 5000 /* 5001 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5002 */ 5003 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5004 PCI_ANY_ID, PCI_ANY_ID, 5005 0, 5006 0, pbn_pericom_PI7C9X7951 }, 5007 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5008 PCI_ANY_ID, PCI_ANY_ID, 5009 0, 5010 0, pbn_pericom_PI7C9X7952 }, 5011 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5012 PCI_ANY_ID, PCI_ANY_ID, 5013 0, 5014 0, pbn_pericom_PI7C9X7954 }, 5015 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5016 PCI_ANY_ID, PCI_ANY_ID, 5017 0, 5018 0, pbn_pericom_PI7C9X7958 }, 5019 /* 5020 * ACCES I/O Products quad 5021 */ 5022 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_pericom_PI7C9X7952 }, 5025 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_pericom_PI7C9X7952 }, 5028 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_pericom_PI7C9X7954 }, 5031 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_pericom_PI7C9X7954 }, 5034 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_pericom_PI7C9X7952 }, 5037 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_pericom_PI7C9X7952 }, 5040 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_pericom_PI7C9X7954 }, 5043 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_pericom_PI7C9X7954 }, 5046 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_pericom_PI7C9X7952 }, 5049 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_pericom_PI7C9X7952 }, 5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_pericom_PI7C9X7954 }, 5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_pericom_PI7C9X7954 }, 5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_pericom_PI7C9X7951 }, 5061 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_pericom_PI7C9X7952 }, 5064 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_pericom_PI7C9X7952 }, 5067 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5069 pbn_pericom_PI7C9X7954 }, 5070 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5072 pbn_pericom_PI7C9X7954 }, 5073 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5075 pbn_pericom_PI7C9X7952 }, 5076 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5078 pbn_pericom_PI7C9X7954 }, 5079 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5081 pbn_pericom_PI7C9X7952 }, 5082 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5084 pbn_pericom_PI7C9X7952 }, 5085 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5087 pbn_pericom_PI7C9X7954 }, 5088 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5090 pbn_pericom_PI7C9X7954 }, 5091 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5093 pbn_pericom_PI7C9X7952 }, 5094 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5096 pbn_pericom_PI7C9X7954 }, 5097 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5099 pbn_pericom_PI7C9X7954 }, 5100 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_pericom_PI7C9X7958 }, 5103 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5105 pbn_pericom_PI7C9X7958 }, 5106 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5108 pbn_pericom_PI7C9X7954 }, 5109 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5111 pbn_pericom_PI7C9X7958 }, 5112 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5114 pbn_pericom_PI7C9X7954 }, 5115 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5117 pbn_pericom_PI7C9X7958 }, 5118 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5120 pbn_pericom_PI7C9X7954 }, 5121 /* 5122 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5123 */ 5124 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5126 pbn_b0_1_115200 }, 5127 /* 5128 * ITE 5129 */ 5130 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5131 PCI_ANY_ID, PCI_ANY_ID, 5132 0, 0, 5133 pbn_b1_bt_1_115200 }, 5134 5135 /* 5136 * IntaShield IS-100 5137 */ 5138 { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5140 pbn_b2_1_115200 }, 5141 /* 5142 * IntaShield IS-200 5143 */ 5144 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5146 pbn_b2_2_115200 }, 5147 /* 5148 * IntaShield IS-400 5149 */ 5150 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5152 pbn_b2_4_115200 }, 5153 /* Brainboxes Devices */ 5154 /* 5155 * Brainboxes UC-101 5156 */ 5157 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 5158 PCI_ANY_ID, PCI_ANY_ID, 5159 0, 0, 5160 pbn_b2_2_115200 }, 5161 /* 5162 * Brainboxes UC-235/246 5163 */ 5164 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 5165 PCI_ANY_ID, PCI_ANY_ID, 5166 0, 0, 5167 pbn_b2_1_115200 }, 5168 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 5169 PCI_ANY_ID, PCI_ANY_ID, 5170 0, 0, 5171 pbn_b2_1_115200 }, 5172 /* 5173 * Brainboxes UC-253/UC-734 5174 */ 5175 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5176 PCI_ANY_ID, PCI_ANY_ID, 5177 0, 0, 5178 pbn_b2_2_115200 }, 5179 /* 5180 * Brainboxes UC-260/271/701/756 5181 */ 5182 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5183 PCI_ANY_ID, PCI_ANY_ID, 5184 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5185 pbn_b2_4_115200 }, 5186 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5187 PCI_ANY_ID, PCI_ANY_ID, 5188 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5189 pbn_b2_4_115200 }, 5190 /* 5191 * Brainboxes UP-189 5192 */ 5193 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5194 PCI_ANY_ID, PCI_ANY_ID, 5195 0, 0, 5196 pbn_b2_2_115200 }, 5197 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5198 PCI_ANY_ID, PCI_ANY_ID, 5199 0, 0, 5200 pbn_b2_2_115200 }, 5201 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5202 PCI_ANY_ID, PCI_ANY_ID, 5203 0, 0, 5204 pbn_b2_2_115200 }, 5205 /* 5206 * Brainboxes UP-200 5207 */ 5208 { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5209 PCI_ANY_ID, PCI_ANY_ID, 5210 0, 0, 5211 pbn_b2_2_115200 }, 5212 { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5213 PCI_ANY_ID, PCI_ANY_ID, 5214 0, 0, 5215 pbn_b2_2_115200 }, 5216 { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5217 PCI_ANY_ID, PCI_ANY_ID, 5218 0, 0, 5219 pbn_b2_2_115200 }, 5220 /* 5221 * Brainboxes UP-869 5222 */ 5223 { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5224 PCI_ANY_ID, PCI_ANY_ID, 5225 0, 0, 5226 pbn_b2_2_115200 }, 5227 { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5228 PCI_ANY_ID, PCI_ANY_ID, 5229 0, 0, 5230 pbn_b2_2_115200 }, 5231 { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5232 PCI_ANY_ID, PCI_ANY_ID, 5233 0, 0, 5234 pbn_b2_2_115200 }, 5235 /* 5236 * Brainboxes UP-880 5237 */ 5238 { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5239 PCI_ANY_ID, PCI_ANY_ID, 5240 0, 0, 5241 pbn_b2_2_115200 }, 5242 { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5243 PCI_ANY_ID, PCI_ANY_ID, 5244 0, 0, 5245 pbn_b2_2_115200 }, 5246 { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5247 PCI_ANY_ID, PCI_ANY_ID, 5248 0, 0, 5249 pbn_b2_2_115200 }, 5250 /* 5251 * Brainboxes UC-268 5252 */ 5253 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5254 PCI_ANY_ID, PCI_ANY_ID, 5255 0, 0, 5256 pbn_b2_4_115200 }, 5257 /* 5258 * Brainboxes UC-275/279 5259 */ 5260 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5261 PCI_ANY_ID, PCI_ANY_ID, 5262 0, 0, 5263 pbn_b2_8_115200 }, 5264 /* 5265 * Brainboxes UC-302 5266 */ 5267 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5268 PCI_ANY_ID, PCI_ANY_ID, 5269 0, 0, 5270 pbn_b2_2_115200 }, 5271 { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 5272 PCI_ANY_ID, PCI_ANY_ID, 5273 0, 0, 5274 pbn_b2_2_115200 }, 5275 { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 5276 PCI_ANY_ID, PCI_ANY_ID, 5277 0, 0, 5278 pbn_b2_2_115200 }, 5279 /* 5280 * Brainboxes UC-310 5281 */ 5282 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5283 PCI_ANY_ID, PCI_ANY_ID, 5284 0, 0, 5285 pbn_b2_2_115200 }, 5286 /* 5287 * Brainboxes UC-313 5288 */ 5289 { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 5290 PCI_ANY_ID, PCI_ANY_ID, 5291 0, 0, 5292 pbn_b2_2_115200 }, 5293 { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 5294 PCI_ANY_ID, PCI_ANY_ID, 5295 0, 0, 5296 pbn_b2_2_115200 }, 5297 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5298 PCI_ANY_ID, PCI_ANY_ID, 5299 0, 0, 5300 pbn_b2_2_115200 }, 5301 /* 5302 * Brainboxes UC-320/324 5303 */ 5304 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5305 PCI_ANY_ID, PCI_ANY_ID, 5306 0, 0, 5307 pbn_b2_1_115200 }, 5308 /* 5309 * Brainboxes UC-346 5310 */ 5311 { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5312 PCI_ANY_ID, PCI_ANY_ID, 5313 0, 0, 5314 pbn_b2_4_115200 }, 5315 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5316 PCI_ANY_ID, PCI_ANY_ID, 5317 0, 0, 5318 pbn_b2_4_115200 }, 5319 /* 5320 * Brainboxes UC-357 5321 */ 5322 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5323 PCI_ANY_ID, PCI_ANY_ID, 5324 0, 0, 5325 pbn_b2_2_115200 }, 5326 { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5327 PCI_ANY_ID, PCI_ANY_ID, 5328 0, 0, 5329 pbn_b2_2_115200 }, 5330 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5331 PCI_ANY_ID, PCI_ANY_ID, 5332 0, 0, 5333 pbn_b2_2_115200 }, 5334 /* 5335 * Brainboxes UC-368 5336 */ 5337 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5338 PCI_ANY_ID, PCI_ANY_ID, 5339 0, 0, 5340 pbn_b2_4_115200 }, 5341 /* 5342 * Brainboxes UC-420 5343 */ 5344 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5345 PCI_ANY_ID, PCI_ANY_ID, 5346 0, 0, 5347 pbn_b2_4_115200 }, 5348 /* 5349 * Brainboxes UC-607 5350 */ 5351 { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5352 PCI_ANY_ID, PCI_ANY_ID, 5353 0, 0, 5354 pbn_b2_2_115200 }, 5355 { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5356 PCI_ANY_ID, PCI_ANY_ID, 5357 0, 0, 5358 pbn_b2_2_115200 }, 5359 { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5360 PCI_ANY_ID, PCI_ANY_ID, 5361 0, 0, 5362 pbn_b2_2_115200 }, 5363 /* 5364 * Brainboxes UC-836 5365 */ 5366 { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5367 PCI_ANY_ID, PCI_ANY_ID, 5368 0, 0, 5369 pbn_b2_4_115200 }, 5370 /* 5371 * Perle PCI-RAS cards 5372 */ 5373 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5374 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5375 0, 0, pbn_b2_4_921600 }, 5376 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5377 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5378 0, 0, pbn_b2_8_921600 }, 5379 5380 /* 5381 * Mainpine series cards: Fairly standard layout but fools 5382 * parts of the autodetect in some cases and uses otherwise 5383 * unmatched communications subclasses in the PCI Express case 5384 */ 5385 5386 { /* RockForceDUO */ 5387 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5388 PCI_VENDOR_ID_MAINPINE, 0x0200, 5389 0, 0, pbn_b0_2_115200 }, 5390 { /* RockForceQUATRO */ 5391 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5392 PCI_VENDOR_ID_MAINPINE, 0x0300, 5393 0, 0, pbn_b0_4_115200 }, 5394 { /* RockForceDUO+ */ 5395 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5396 PCI_VENDOR_ID_MAINPINE, 0x0400, 5397 0, 0, pbn_b0_2_115200 }, 5398 { /* RockForceQUATRO+ */ 5399 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5400 PCI_VENDOR_ID_MAINPINE, 0x0500, 5401 0, 0, pbn_b0_4_115200 }, 5402 { /* RockForce+ */ 5403 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5404 PCI_VENDOR_ID_MAINPINE, 0x0600, 5405 0, 0, pbn_b0_2_115200 }, 5406 { /* RockForce+ */ 5407 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5408 PCI_VENDOR_ID_MAINPINE, 0x0700, 5409 0, 0, pbn_b0_4_115200 }, 5410 { /* RockForceOCTO+ */ 5411 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5412 PCI_VENDOR_ID_MAINPINE, 0x0800, 5413 0, 0, pbn_b0_8_115200 }, 5414 { /* RockForceDUO+ */ 5415 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5416 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5417 0, 0, pbn_b0_2_115200 }, 5418 { /* RockForceQUARTRO+ */ 5419 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5420 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5421 0, 0, pbn_b0_4_115200 }, 5422 { /* RockForceOCTO+ */ 5423 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5424 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5425 0, 0, pbn_b0_8_115200 }, 5426 { /* RockForceD1 */ 5427 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5428 PCI_VENDOR_ID_MAINPINE, 0x2000, 5429 0, 0, pbn_b0_1_115200 }, 5430 { /* RockForceF1 */ 5431 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5432 PCI_VENDOR_ID_MAINPINE, 0x2100, 5433 0, 0, pbn_b0_1_115200 }, 5434 { /* RockForceD2 */ 5435 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5436 PCI_VENDOR_ID_MAINPINE, 0x2200, 5437 0, 0, pbn_b0_2_115200 }, 5438 { /* RockForceF2 */ 5439 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5440 PCI_VENDOR_ID_MAINPINE, 0x2300, 5441 0, 0, pbn_b0_2_115200 }, 5442 { /* RockForceD4 */ 5443 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5444 PCI_VENDOR_ID_MAINPINE, 0x2400, 5445 0, 0, pbn_b0_4_115200 }, 5446 { /* RockForceF4 */ 5447 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5448 PCI_VENDOR_ID_MAINPINE, 0x2500, 5449 0, 0, pbn_b0_4_115200 }, 5450 { /* RockForceD8 */ 5451 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5452 PCI_VENDOR_ID_MAINPINE, 0x2600, 5453 0, 0, pbn_b0_8_115200 }, 5454 { /* RockForceF8 */ 5455 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5456 PCI_VENDOR_ID_MAINPINE, 0x2700, 5457 0, 0, pbn_b0_8_115200 }, 5458 { /* IQ Express D1 */ 5459 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5460 PCI_VENDOR_ID_MAINPINE, 0x3000, 5461 0, 0, pbn_b0_1_115200 }, 5462 { /* IQ Express F1 */ 5463 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5464 PCI_VENDOR_ID_MAINPINE, 0x3100, 5465 0, 0, pbn_b0_1_115200 }, 5466 { /* IQ Express D2 */ 5467 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5468 PCI_VENDOR_ID_MAINPINE, 0x3200, 5469 0, 0, pbn_b0_2_115200 }, 5470 { /* IQ Express F2 */ 5471 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5472 PCI_VENDOR_ID_MAINPINE, 0x3300, 5473 0, 0, pbn_b0_2_115200 }, 5474 { /* IQ Express D4 */ 5475 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5476 PCI_VENDOR_ID_MAINPINE, 0x3400, 5477 0, 0, pbn_b0_4_115200 }, 5478 { /* IQ Express F4 */ 5479 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5480 PCI_VENDOR_ID_MAINPINE, 0x3500, 5481 0, 0, pbn_b0_4_115200 }, 5482 { /* IQ Express D8 */ 5483 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5484 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5485 0, 0, pbn_b0_8_115200 }, 5486 { /* IQ Express F8 */ 5487 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5488 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5489 0, 0, pbn_b0_8_115200 }, 5490 5491 5492 /* 5493 * PA Semi PA6T-1682M on-chip UART 5494 */ 5495 { PCI_VENDOR_ID_PASEMI, 0xa004, 5496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5497 pbn_pasemi_1682M }, 5498 5499 /* 5500 * National Instruments 5501 */ 5502 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5504 pbn_b1_16_115200 }, 5505 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5507 pbn_b1_8_115200 }, 5508 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5510 pbn_b1_bt_4_115200 }, 5511 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5513 pbn_b1_bt_2_115200 }, 5514 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5516 pbn_b1_bt_4_115200 }, 5517 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5519 pbn_b1_bt_2_115200 }, 5520 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5522 pbn_b1_16_115200 }, 5523 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5525 pbn_b1_8_115200 }, 5526 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5528 pbn_b1_bt_4_115200 }, 5529 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5531 pbn_b1_bt_2_115200 }, 5532 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5534 pbn_b1_bt_4_115200 }, 5535 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5537 pbn_b1_bt_2_115200 }, 5538 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5539 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5540 pbn_ni8430_2 }, 5541 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5543 pbn_ni8430_2 }, 5544 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5545 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5546 pbn_ni8430_4 }, 5547 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5549 pbn_ni8430_4 }, 5550 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5552 pbn_ni8430_8 }, 5553 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5555 pbn_ni8430_8 }, 5556 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5558 pbn_ni8430_16 }, 5559 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5561 pbn_ni8430_16 }, 5562 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5564 pbn_ni8430_2 }, 5565 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5567 pbn_ni8430_2 }, 5568 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5570 pbn_ni8430_4 }, 5571 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5573 pbn_ni8430_4 }, 5574 5575 /* 5576 * MOXA 5577 */ 5578 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5580 pbn_moxa8250_2p }, 5581 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5583 pbn_moxa8250_2p }, 5584 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5586 pbn_moxa8250_4p }, 5587 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5589 pbn_moxa8250_4p }, 5590 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5592 pbn_moxa8250_8p }, 5593 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5595 pbn_moxa8250_8p }, 5596 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5598 pbn_moxa8250_8p }, 5599 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5601 pbn_moxa8250_8p }, 5602 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5604 pbn_moxa8250_2p }, 5605 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5607 pbn_moxa8250_4p }, 5608 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5610 pbn_moxa8250_8p }, 5611 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5613 pbn_moxa8250_8p }, 5614 5615 /* 5616 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5617 */ 5618 { PCI_VENDOR_ID_ADDIDATA, 5619 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5620 PCI_ANY_ID, 5621 PCI_ANY_ID, 5622 0, 5623 0, 5624 pbn_b0_4_115200 }, 5625 5626 { PCI_VENDOR_ID_ADDIDATA, 5627 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5628 PCI_ANY_ID, 5629 PCI_ANY_ID, 5630 0, 5631 0, 5632 pbn_b0_2_115200 }, 5633 5634 { PCI_VENDOR_ID_ADDIDATA, 5635 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5636 PCI_ANY_ID, 5637 PCI_ANY_ID, 5638 0, 5639 0, 5640 pbn_b0_1_115200 }, 5641 5642 { PCI_VENDOR_ID_AMCC, 5643 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5644 PCI_ANY_ID, 5645 PCI_ANY_ID, 5646 0, 5647 0, 5648 pbn_b1_8_115200 }, 5649 5650 { PCI_VENDOR_ID_ADDIDATA, 5651 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5652 PCI_ANY_ID, 5653 PCI_ANY_ID, 5654 0, 5655 0, 5656 pbn_b0_4_115200 }, 5657 5658 { PCI_VENDOR_ID_ADDIDATA, 5659 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5660 PCI_ANY_ID, 5661 PCI_ANY_ID, 5662 0, 5663 0, 5664 pbn_b0_2_115200 }, 5665 5666 { PCI_VENDOR_ID_ADDIDATA, 5667 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5668 PCI_ANY_ID, 5669 PCI_ANY_ID, 5670 0, 5671 0, 5672 pbn_b0_1_115200 }, 5673 5674 { PCI_VENDOR_ID_ADDIDATA, 5675 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5676 PCI_ANY_ID, 5677 PCI_ANY_ID, 5678 0, 5679 0, 5680 pbn_b0_4_115200 }, 5681 5682 { PCI_VENDOR_ID_ADDIDATA, 5683 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5684 PCI_ANY_ID, 5685 PCI_ANY_ID, 5686 0, 5687 0, 5688 pbn_b0_2_115200 }, 5689 5690 { PCI_VENDOR_ID_ADDIDATA, 5691 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5692 PCI_ANY_ID, 5693 PCI_ANY_ID, 5694 0, 5695 0, 5696 pbn_b0_1_115200 }, 5697 5698 { PCI_VENDOR_ID_ADDIDATA, 5699 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5700 PCI_ANY_ID, 5701 PCI_ANY_ID, 5702 0, 5703 0, 5704 pbn_b0_8_115200 }, 5705 5706 { PCI_VENDOR_ID_ADDIDATA, 5707 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5708 PCI_ANY_ID, 5709 PCI_ANY_ID, 5710 0, 5711 0, 5712 pbn_ADDIDATA_PCIe_4_3906250 }, 5713 5714 { PCI_VENDOR_ID_ADDIDATA, 5715 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5716 PCI_ANY_ID, 5717 PCI_ANY_ID, 5718 0, 5719 0, 5720 pbn_ADDIDATA_PCIe_2_3906250 }, 5721 5722 { PCI_VENDOR_ID_ADDIDATA, 5723 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5724 PCI_ANY_ID, 5725 PCI_ANY_ID, 5726 0, 5727 0, 5728 pbn_ADDIDATA_PCIe_1_3906250 }, 5729 5730 { PCI_VENDOR_ID_ADDIDATA, 5731 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5732 PCI_ANY_ID, 5733 PCI_ANY_ID, 5734 0, 5735 0, 5736 pbn_ADDIDATA_PCIe_8_3906250 }, 5737 5738 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5739 PCI_VENDOR_ID_IBM, 0x0299, 5740 0, 0, pbn_b0_bt_2_115200 }, 5741 5742 /* 5743 * other NetMos 9835 devices are most likely handled by the 5744 * parport_serial driver, check drivers/parport/parport_serial.c 5745 * before adding them here. 5746 */ 5747 5748 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5749 0xA000, 0x1000, 5750 0, 0, pbn_b0_1_115200 }, 5751 5752 /* the 9901 is a rebranded 9912 */ 5753 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5754 0xA000, 0x1000, 5755 0, 0, pbn_b0_1_115200 }, 5756 5757 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5758 0xA000, 0x1000, 5759 0, 0, pbn_b0_1_115200 }, 5760 5761 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5762 0xA000, 0x1000, 5763 0, 0, pbn_b0_1_115200 }, 5764 5765 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5766 0xA000, 0x1000, 5767 0, 0, pbn_b0_1_115200 }, 5768 5769 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5770 0xA000, 0x3002, 5771 0, 0, pbn_NETMOS9900_2s_115200 }, 5772 5773 /* 5774 * Best Connectivity and Rosewill PCI Multi I/O cards 5775 */ 5776 5777 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5778 0xA000, 0x1000, 5779 0, 0, pbn_b0_1_115200 }, 5780 5781 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5782 0xA000, 0x3002, 5783 0, 0, pbn_b0_bt_2_115200 }, 5784 5785 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5786 0xA000, 0x3004, 5787 0, 0, pbn_b0_bt_4_115200 }, 5788 /* Intel CE4100 */ 5789 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5791 pbn_ce4100_1_115200 }, 5792 5793 /* 5794 * Cronyx Omega PCI 5795 */ 5796 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5798 pbn_omegapci }, 5799 5800 /* 5801 * Broadcom TruManage 5802 */ 5803 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5805 pbn_brcm_trumanage }, 5806 5807 /* 5808 * AgeStar as-prs2-009 5809 */ 5810 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5811 PCI_ANY_ID, PCI_ANY_ID, 5812 0, 0, pbn_b0_bt_2_115200 }, 5813 5814 /* 5815 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5816 * so not listed here. 5817 */ 5818 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5819 PCI_ANY_ID, PCI_ANY_ID, 5820 0, 0, pbn_b0_bt_4_115200 }, 5821 5822 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5823 PCI_ANY_ID, PCI_ANY_ID, 5824 0, 0, pbn_b0_bt_2_115200 }, 5825 5826 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5827 PCI_ANY_ID, PCI_ANY_ID, 5828 0, 0, pbn_b0_bt_4_115200 }, 5829 5830 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5831 PCI_ANY_ID, PCI_ANY_ID, 5832 0, 0, pbn_wch382_2 }, 5833 5834 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5835 PCI_ANY_ID, PCI_ANY_ID, 5836 0, 0, pbn_wch384_4 }, 5837 5838 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5839 PCI_ANY_ID, PCI_ANY_ID, 5840 0, 0, pbn_wch384_8 }, 5841 /* 5842 * Realtek RealManage 5843 */ 5844 { PCI_VENDOR_ID_REALTEK, 0x816a, 5845 PCI_ANY_ID, PCI_ANY_ID, 5846 0, 0, pbn_b0_1_115200 }, 5847 5848 { PCI_VENDOR_ID_REALTEK, 0x816b, 5849 PCI_ANY_ID, PCI_ANY_ID, 5850 0, 0, pbn_b0_1_115200 }, 5851 5852 /* Fintek PCI serial cards */ 5853 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5854 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5855 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5856 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5857 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5858 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5859 5860 /* MKS Tenta SCOM-080x serial cards */ 5861 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5862 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5863 5864 /* Amazon PCI serial device */ 5865 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5866 5867 /* 5868 * These entries match devices with class COMMUNICATION_SERIAL, 5869 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5870 */ 5871 { PCI_ANY_ID, PCI_ANY_ID, 5872 PCI_ANY_ID, PCI_ANY_ID, 5873 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5874 0xffff00, pbn_default }, 5875 { PCI_ANY_ID, PCI_ANY_ID, 5876 PCI_ANY_ID, PCI_ANY_ID, 5877 PCI_CLASS_COMMUNICATION_MODEM << 8, 5878 0xffff00, pbn_default }, 5879 { PCI_ANY_ID, PCI_ANY_ID, 5880 PCI_ANY_ID, PCI_ANY_ID, 5881 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5882 0xffff00, pbn_default }, 5883 { 0, } 5884}; 5885 5886static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5887 pci_channel_state_t state) 5888{ 5889 struct serial_private *priv = pci_get_drvdata(dev); 5890 5891 if (state == pci_channel_io_perm_failure) 5892 return PCI_ERS_RESULT_DISCONNECT; 5893 5894 if (priv) 5895 pciserial_detach_ports(priv); 5896 5897 pci_disable_device(dev); 5898 5899 return PCI_ERS_RESULT_NEED_RESET; 5900} 5901 5902static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5903{ 5904 int rc; 5905 5906 rc = pci_enable_device(dev); 5907 5908 if (rc) 5909 return PCI_ERS_RESULT_DISCONNECT; 5910 5911 pci_restore_state(dev); 5912 pci_save_state(dev); 5913 5914 return PCI_ERS_RESULT_RECOVERED; 5915} 5916 5917static void serial8250_io_resume(struct pci_dev *dev) 5918{ 5919 struct serial_private *priv = pci_get_drvdata(dev); 5920 struct serial_private *new; 5921 5922 if (!priv) 5923 return; 5924 5925 new = pciserial_init_ports(dev, priv->board); 5926 if (!IS_ERR(new)) { 5927 pci_set_drvdata(dev, new); 5928 kfree(priv); 5929 } 5930} 5931 5932static const struct pci_error_handlers serial8250_err_handler = { 5933 .error_detected = serial8250_io_error_detected, 5934 .slot_reset = serial8250_io_slot_reset, 5935 .resume = serial8250_io_resume, 5936}; 5937 5938static struct pci_driver serial_pci_driver = { 5939 .name = "serial", 5940 .probe = pciserial_init_one, 5941 .remove = pciserial_remove_one, 5942 .driver = { 5943 .pm = &pciserial_pm_ops, 5944 }, 5945 .id_table = serial_pci_tbl, 5946 .err_handler = &serial8250_err_handler, 5947}; 5948 5949module_pci_driver(serial_pci_driver); 5950 5951MODULE_LICENSE("GPL"); 5952MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5953MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5954