1// SPDX-License-Identifier: GPL-2.0 2/* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11#include <linux/clk.h> 12#include <linux/device.h> 13#include <linux/io.h> 14#include <linux/module.h> 15#include <linux/serial_8250.h> 16#include <linux/serial_reg.h> 17#include <linux/tty_flip.h> 18#include <linux/platform_device.h> 19#include <linux/slab.h> 20#include <linux/of.h> 21#include <linux/of_device.h> 22#include <linux/of_gpio.h> 23#include <linux/of_irq.h> 24#include <linux/delay.h> 25#include <linux/pm_runtime.h> 26#include <linux/console.h> 27#include <linux/pm_qos.h> 28#include <linux/pm_wakeirq.h> 29#include <linux/dma-mapping.h> 30#include <linux/sys_soc.h> 31 32#include "8250.h" 33 34#define DEFAULT_CLK_SPEED 48000000 35#define OMAP_UART_REGSHIFT 2 36 37#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39#define OMAP_DMA_TX_KICK (1 << 2) 40/* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44#define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45#define UART_HAS_EFR2 BIT(4) 46#define UART_HAS_RHR_IT_DIS BIT(5) 47#define UART_RX_TIMEOUT_QUIRK BIT(6) 48 49#define OMAP_UART_FCR_RX_TRIG 6 50#define OMAP_UART_FCR_TX_TRIG 4 51 52/* SCR register bitmasks */ 53#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55#define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57#define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60/* MVR register bitmasks */ 61#define OMAP_UART_MVR_SCHEME_SHIFT 30 62#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65#define OMAP_UART_MVR_MAJ_MASK 0x700 66#define OMAP_UART_MVR_MAJ_SHIFT 8 67#define OMAP_UART_MVR_MIN_MASK 0x3f 68 69/* SYSC register bitmasks */ 70#define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72/* SYSS register bitmasks */ 73#define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75#define UART_TI752_TLR_TX 0 76#define UART_TI752_TLR_RX 4 77 78#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79#define TRIGGER_FCR_MASK(x) (x & 3) 80 81/* Enable XON/XOFF flow control on output */ 82#define OMAP_UART_SW_TX 0x08 83/* Enable XON/XOFF flow control on input */ 84#define OMAP_UART_SW_RX 0x02 85 86#define OMAP_UART_WER_MOD_WKUP 0x7f 87#define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89#define TX_TRIGGER 1 90#define RX_TRIGGER 48 91 92#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97#define OMAP_UART_REV_46 0x0406 98#define OMAP_UART_REV_52 0x0502 99#define OMAP_UART_REV_63 0x0603 100 101/* Interrupt Enable Register 2 */ 102#define UART_OMAP_IER2 0x1B 103#define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105/* Enhanced features register 2 */ 106#define UART_OMAP_EFR2 0x23 107#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 108 109/* RX FIFO occupancy indicator */ 110#define UART_OMAP_RX_LVL 0x19 111 112struct omap8250_priv { 113 void __iomem *membase; 114 int line; 115 u8 habit; 116 u8 mdr1; 117 u8 efr; 118 u8 scr; 119 u8 wer; 120 u8 xon; 121 u8 xoff; 122 u8 delayed_restore; 123 u16 quot; 124 125 u8 tx_trigger; 126 u8 rx_trigger; 127 bool is_suspending; 128 int wakeirq; 129 int wakeups_enabled; 130 u32 latency; 131 u32 calc_latency; 132 struct pm_qos_request pm_qos_request; 133 struct work_struct qos_work; 134 struct uart_8250_dma omap8250_dma; 135 spinlock_t rx_dma_lock; 136 bool rx_dma_broken; 137 bool throttled; 138}; 139 140struct omap8250_dma_params { 141 u32 rx_size; 142 u8 rx_trigger; 143 u8 tx_trigger; 144}; 145 146struct omap8250_platdata { 147 struct omap8250_dma_params *dma_params; 148 u8 habit; 149}; 150 151#ifdef CONFIG_SERIAL_8250_DMA 152static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 153#else 154static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 155#endif 156 157static u32 uart_read(struct omap8250_priv *priv, u32 reg) 158{ 159 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 160} 161 162static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 163{ 164 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 165} 166 167/* 168 * Called on runtime PM resume path from omap8250_restore_regs(), and 169 * omap8250_set_mctrl(). 170 */ 171static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 172{ 173 struct uart_8250_port *up = up_to_u8250p(port); 174 struct omap8250_priv *priv = up->port.private_data; 175 u8 lcr; 176 177 serial8250_do_set_mctrl(port, mctrl); 178 179 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 180 /* 181 * Turn off autoRTS if RTS is lowered and restore autoRTS 182 * setting if RTS is raised 183 */ 184 lcr = serial_in(up, UART_LCR); 185 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 186 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 187 priv->efr |= UART_EFR_RTS; 188 else 189 priv->efr &= ~UART_EFR_RTS; 190 serial_out(up, UART_EFR, priv->efr); 191 serial_out(up, UART_LCR, lcr); 192 } 193} 194 195static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 196{ 197 int err; 198 199 err = pm_runtime_resume_and_get(port->dev); 200 if (err) 201 return; 202 203 __omap8250_set_mctrl(port, mctrl); 204 205 pm_runtime_mark_last_busy(port->dev); 206 pm_runtime_put_autosuspend(port->dev); 207} 208 209/* 210 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 211 * The access to uart register after MDR1 Access 212 * causes UART to corrupt data. 213 * 214 * Need a delay = 215 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 216 * give 10 times as much 217 */ 218static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 219 struct omap8250_priv *priv) 220{ 221 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 222 udelay(2); 223 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 224 UART_FCR_CLEAR_RCVR); 225} 226 227static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 228 struct omap8250_priv *priv) 229{ 230 unsigned int uartclk = port->uartclk; 231 unsigned int div_13, div_16; 232 unsigned int abs_d13, abs_d16; 233 234 /* 235 * Old custom speed handling. 236 */ 237 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 238 priv->quot = port->custom_divisor & UART_DIV_MAX; 239 /* 240 * I assume that nobody is using this. But hey, if somebody 241 * would like to specify the divisor _and_ the mode then the 242 * driver is ready and waiting for it. 243 */ 244 if (port->custom_divisor & (1 << 16)) 245 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 246 else 247 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 248 return; 249 } 250 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 251 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 252 253 if (!div_13) 254 div_13 = 1; 255 if (!div_16) 256 div_16 = 1; 257 258 abs_d13 = abs(baud - uartclk / 13 / div_13); 259 abs_d16 = abs(baud - uartclk / 16 / div_16); 260 261 if (abs_d13 >= abs_d16) { 262 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 263 priv->quot = div_16; 264 } else { 265 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 266 priv->quot = div_13; 267 } 268} 269 270static void omap8250_update_scr(struct uart_8250_port *up, 271 struct omap8250_priv *priv) 272{ 273 u8 old_scr; 274 275 old_scr = serial_in(up, UART_OMAP_SCR); 276 if (old_scr == priv->scr) 277 return; 278 279 /* 280 * The manual recommends not to enable the DMA mode selector in the SCR 281 * (instead of the FCR) register _and_ selecting the DMA mode as one 282 * register write because this may lead to malfunction. 283 */ 284 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 285 serial_out(up, UART_OMAP_SCR, 286 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 287 serial_out(up, UART_OMAP_SCR, priv->scr); 288} 289 290static void omap8250_update_mdr1(struct uart_8250_port *up, 291 struct omap8250_priv *priv) 292{ 293 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 294 omap_8250_mdr1_errataset(up, priv); 295 else 296 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 297} 298 299static void omap8250_restore_regs(struct uart_8250_port *up) 300{ 301 struct omap8250_priv *priv = up->port.private_data; 302 struct uart_8250_dma *dma = up->dma; 303 u8 mcr = serial8250_in_MCR(up); 304 305 if (dma && dma->tx_running) { 306 /* 307 * TCSANOW requests the change to occur immediately however if 308 * we have a TX-DMA operation in progress then it has been 309 * observed that it might stall and never complete. Therefore we 310 * delay DMA completes to prevent this hang from happen. 311 */ 312 priv->delayed_restore = 1; 313 return; 314 } 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 serial_out(up, UART_EFR, UART_EFR_ECB); 318 319 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 320 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 321 serial_out(up, UART_FCR, up->fcr); 322 323 omap8250_update_scr(up, priv); 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 327 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 328 OMAP_UART_TCR_HALT(52)); 329 serial_out(up, UART_TI752_TLR, 330 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 331 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 332 333 serial_out(up, UART_LCR, 0); 334 335 /* drop TCR + TLR access, we setup XON/XOFF later */ 336 serial8250_out_MCR(up, mcr); 337 338 serial_out(up, UART_IER, up->ier); 339 340 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 341 serial_dl_write(up, priv->quot); 342 343 serial_out(up, UART_EFR, priv->efr); 344 345 /* Configure flow control */ 346 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 347 serial_out(up, UART_XON1, priv->xon); 348 serial_out(up, UART_XOFF1, priv->xoff); 349 350 serial_out(up, UART_LCR, up->lcr); 351 352 omap8250_update_mdr1(up, priv); 353 354 __omap8250_set_mctrl(&up->port, up->port.mctrl); 355 356 if (up->port.rs485.flags & SER_RS485_ENABLED) 357 serial8250_em485_stop_tx(up); 358} 359 360/* 361 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 362 * some differences in how we want to handle flow control. 363 */ 364static void omap_8250_set_termios(struct uart_port *port, 365 struct ktermios *termios, 366 struct ktermios *old) 367{ 368 struct uart_8250_port *up = up_to_u8250p(port); 369 struct omap8250_priv *priv = up->port.private_data; 370 unsigned char cval = 0; 371 unsigned int baud; 372 373 switch (termios->c_cflag & CSIZE) { 374 case CS5: 375 cval = UART_LCR_WLEN5; 376 break; 377 case CS6: 378 cval = UART_LCR_WLEN6; 379 break; 380 case CS7: 381 cval = UART_LCR_WLEN7; 382 break; 383 default: 384 case CS8: 385 cval = UART_LCR_WLEN8; 386 break; 387 } 388 389 if (termios->c_cflag & CSTOPB) 390 cval |= UART_LCR_STOP; 391 if (termios->c_cflag & PARENB) 392 cval |= UART_LCR_PARITY; 393 if (!(termios->c_cflag & PARODD)) 394 cval |= UART_LCR_EPAR; 395 if (termios->c_cflag & CMSPAR) 396 cval |= UART_LCR_SPAR; 397 398 /* 399 * Ask the core to calculate the divisor for us. 400 */ 401 baud = uart_get_baud_rate(port, termios, old, 402 port->uartclk / 16 / UART_DIV_MAX, 403 port->uartclk / 13); 404 omap_8250_get_divisor(port, baud, priv); 405 406 /* 407 * Ok, we're now changing the port state. Do it with 408 * interrupts disabled. 409 */ 410 pm_runtime_get_sync(port->dev); 411 spin_lock_irq(&port->lock); 412 413 /* 414 * Update the per-port timeout. 415 */ 416 uart_update_timeout(port, termios->c_cflag, baud); 417 418 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 419 if (termios->c_iflag & INPCK) 420 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 421 if (termios->c_iflag & (IGNBRK | PARMRK)) 422 up->port.read_status_mask |= UART_LSR_BI; 423 424 /* 425 * Characters to ignore 426 */ 427 up->port.ignore_status_mask = 0; 428 if (termios->c_iflag & IGNPAR) 429 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 430 if (termios->c_iflag & IGNBRK) { 431 up->port.ignore_status_mask |= UART_LSR_BI; 432 /* 433 * If we're ignoring parity and break indicators, 434 * ignore overruns too (for real raw support). 435 */ 436 if (termios->c_iflag & IGNPAR) 437 up->port.ignore_status_mask |= UART_LSR_OE; 438 } 439 440 /* 441 * ignore all characters if CREAD is not set 442 */ 443 if ((termios->c_cflag & CREAD) == 0) 444 up->port.ignore_status_mask |= UART_LSR_DR; 445 446 /* 447 * Modem status interrupts 448 */ 449 up->ier &= ~UART_IER_MSI; 450 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 451 up->ier |= UART_IER_MSI; 452 453 up->lcr = cval; 454 /* Up to here it was mostly serial8250_do_set_termios() */ 455 456 /* 457 * We enable TRIG_GRANU for RX and TX and additionally we set 458 * SCR_TX_EMPTY bit. The result is the following: 459 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 460 * - less than RX_TRIGGER number of bytes will also cause an interrupt 461 * once the UART decides that there no new bytes arriving. 462 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 463 * empty - the trigger level is ignored here. 464 * 465 * Once DMA is enabled: 466 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 467 * bytes in the TX FIFO. On each assert the DMA engine will move 468 * TX_TRIGGER bytes into the FIFO. 469 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 470 * the FIFO and move RX_TRIGGER bytes. 471 * This is because threshold and trigger values are the same. 472 */ 473 up->fcr = UART_FCR_ENABLE_FIFO; 474 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 475 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 476 477 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 478 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 479 480 if (up->dma) 481 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 482 OMAP_UART_SCR_DMAMODE_CTL; 483 484 priv->xon = termios->c_cc[VSTART]; 485 priv->xoff = termios->c_cc[VSTOP]; 486 487 priv->efr = 0; 488 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 489 490 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 491 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 492 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 493 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 494 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 495 priv->efr |= UART_EFR_CTS; 496 } else if (up->port.flags & UPF_SOFT_FLOW) { 497 /* 498 * OMAP rx s/w flow control is borked; the transmitter remains 499 * stuck off even if rx flow control is subsequently disabled 500 */ 501 502 /* 503 * IXOFF Flag: 504 * Enable XON/XOFF flow control on output. 505 * Transmit XON1, XOFF1 506 */ 507 if (termios->c_iflag & IXOFF) { 508 up->port.status |= UPSTAT_AUTOXOFF; 509 priv->efr |= OMAP_UART_SW_TX; 510 } 511 } 512 omap8250_restore_regs(up); 513 514 spin_unlock_irq(&up->port.lock); 515 pm_runtime_mark_last_busy(port->dev); 516 pm_runtime_put_autosuspend(port->dev); 517 518 /* calculate wakeup latency constraint */ 519 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 520 priv->latency = priv->calc_latency; 521 522 schedule_work(&priv->qos_work); 523 524 /* Don't rewrite B0 */ 525 if (tty_termios_baud_rate(termios)) 526 tty_termios_encode_baud_rate(termios, baud, baud); 527} 528 529/* same as 8250 except that we may have extra flow bits set in EFR */ 530static void omap_8250_pm(struct uart_port *port, unsigned int state, 531 unsigned int oldstate) 532{ 533 struct uart_8250_port *up = up_to_u8250p(port); 534 u8 efr; 535 536 pm_runtime_get_sync(port->dev); 537 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 538 efr = serial_in(up, UART_EFR); 539 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 540 serial_out(up, UART_LCR, 0); 541 542 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 543 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 544 serial_out(up, UART_EFR, efr); 545 serial_out(up, UART_LCR, 0); 546 547 pm_runtime_mark_last_busy(port->dev); 548 pm_runtime_put_autosuspend(port->dev); 549} 550 551static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 552 struct omap8250_priv *priv) 553{ 554 const struct soc_device_attribute k3_soc_devices[] = { 555 { .family = "AM65X", }, 556 { .family = "J721E", .revision = "SR1.0" }, 557 { /* sentinel */ } 558 }; 559 u32 mvr, scheme; 560 u16 revision, major, minor; 561 562 mvr = uart_read(priv, UART_OMAP_MVER); 563 564 /* Check revision register scheme */ 565 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 566 567 switch (scheme) { 568 case 0: /* Legacy Scheme: OMAP2/3 */ 569 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 570 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 571 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 572 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 573 break; 574 case 1: 575 /* New Scheme: OMAP4+ */ 576 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 577 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 578 OMAP_UART_MVR_MAJ_SHIFT; 579 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 580 break; 581 default: 582 dev_warn(up->port.dev, 583 "Unknown revision, defaulting to highest\n"); 584 /* highest possible revision */ 585 major = 0xff; 586 minor = 0xff; 587 } 588 /* normalize revision for the driver */ 589 revision = UART_BUILD_REVISION(major, minor); 590 591 switch (revision) { 592 case OMAP_UART_REV_46: 593 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 594 break; 595 case OMAP_UART_REV_52: 596 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 597 OMAP_UART_WER_HAS_TX_WAKEUP; 598 break; 599 case OMAP_UART_REV_63: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 601 OMAP_UART_WER_HAS_TX_WAKEUP; 602 break; 603 default: 604 break; 605 } 606 607 /* 608 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 609 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 610 * to enable errata workaround. 611 */ 612 if (soc_device_match(k3_soc_devices)) 613 priv->habit &= ~UART_HAS_RHR_IT_DIS; 614} 615 616static void omap8250_uart_qos_work(struct work_struct *work) 617{ 618 struct omap8250_priv *priv; 619 620 priv = container_of(work, struct omap8250_priv, qos_work); 621 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 622} 623 624#ifdef CONFIG_SERIAL_8250_DMA 625static int omap_8250_dma_handle_irq(struct uart_port *port); 626#endif 627 628static irqreturn_t omap8250_irq(int irq, void *dev_id) 629{ 630 struct uart_port *port = dev_id; 631 struct omap8250_priv *priv = port->private_data; 632 struct uart_8250_port *up = up_to_u8250p(port); 633 unsigned int iir, lsr; 634 int ret; 635 636#ifdef CONFIG_SERIAL_8250_DMA 637 if (up->dma) { 638 ret = omap_8250_dma_handle_irq(port); 639 return IRQ_RETVAL(ret); 640 } 641#endif 642 643 serial8250_rpm_get(up); 644 lsr = serial_port_in(port, UART_LSR); 645 iir = serial_port_in(port, UART_IIR); 646 ret = serial8250_handle_irq(port, iir); 647 648 /* 649 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 650 * FIFO has been drained, in which case a dummy read of RX FIFO 651 * is required to clear RX TIMEOUT condition. 652 */ 653 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 654 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 655 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 656 serial_port_in(port, UART_RX); 657 } 658 659 /* Stop processing interrupts on input overrun */ 660 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 661 unsigned long delay; 662 663 /* Synchronize UART_IER access against the console. */ 664 spin_lock(&port->lock); 665 up->ier = port->serial_in(port, UART_IER); 666 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 667 port->ops->stop_rx(port); 668 } else { 669 /* Keep restarting the timer until 670 * the input overrun subsides. 671 */ 672 cancel_delayed_work(&up->overrun_backoff); 673 } 674 spin_unlock(&port->lock); 675 676 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 677 schedule_delayed_work(&up->overrun_backoff, delay); 678 } 679 680 serial8250_rpm_put(up); 681 682 return IRQ_RETVAL(ret); 683} 684 685static int omap_8250_startup(struct uart_port *port) 686{ 687 struct uart_8250_port *up = up_to_u8250p(port); 688 struct omap8250_priv *priv = port->private_data; 689 int ret; 690 691 if (priv->wakeirq) { 692 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 693 if (ret) 694 return ret; 695 } 696 697 pm_runtime_get_sync(port->dev); 698 699 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 700 701 serial_out(up, UART_LCR, UART_LCR_WLEN8); 702 703 up->lsr_saved_flags = 0; 704 up->msr_saved_flags = 0; 705 706 /* Disable DMA for console UART */ 707 if (uart_console(port)) 708 up->dma = NULL; 709 710 if (up->dma) { 711 ret = serial8250_request_dma(up); 712 if (ret) { 713 dev_warn_ratelimited(port->dev, 714 "failed to request DMA\n"); 715 up->dma = NULL; 716 } 717 } 718 719 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 720 dev_name(port->dev), port); 721 if (ret < 0) 722 goto err; 723 724 up->ier = UART_IER_RLSI | UART_IER_RDI; 725 serial_out(up, UART_IER, up->ier); 726 727#ifdef CONFIG_PM 728 up->capabilities |= UART_CAP_RPM; 729#endif 730 731 /* Enable module level wake up */ 732 priv->wer = OMAP_UART_WER_MOD_WKUP; 733 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 734 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 735 serial_out(up, UART_OMAP_WER, priv->wer); 736 737 if (up->dma && !(priv->habit & UART_HAS_EFR2)) 738 up->dma->rx_dma(up); 739 740 pm_runtime_mark_last_busy(port->dev); 741 pm_runtime_put_autosuspend(port->dev); 742 return 0; 743err: 744 pm_runtime_mark_last_busy(port->dev); 745 pm_runtime_put_autosuspend(port->dev); 746 dev_pm_clear_wake_irq(port->dev); 747 return ret; 748} 749 750static void omap_8250_shutdown(struct uart_port *port) 751{ 752 struct uart_8250_port *up = up_to_u8250p(port); 753 struct omap8250_priv *priv = port->private_data; 754 755 flush_work(&priv->qos_work); 756 if (up->dma) 757 omap_8250_rx_dma_flush(up); 758 759 pm_runtime_get_sync(port->dev); 760 761 serial_out(up, UART_OMAP_WER, 0); 762 if (priv->habit & UART_HAS_EFR2) 763 serial_out(up, UART_OMAP_EFR2, 0x0); 764 765 up->ier = 0; 766 serial_out(up, UART_IER, 0); 767 768 if (up->dma) 769 serial8250_release_dma(up); 770 771 /* 772 * Disable break condition and FIFOs 773 */ 774 if (up->lcr & UART_LCR_SBC) 775 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 776 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 777 778 pm_runtime_mark_last_busy(port->dev); 779 pm_runtime_put_autosuspend(port->dev); 780 free_irq(port->irq, port); 781 dev_pm_clear_wake_irq(port->dev); 782} 783 784static void omap_8250_throttle(struct uart_port *port) 785{ 786 struct omap8250_priv *priv = port->private_data; 787 unsigned long flags; 788 789 pm_runtime_get_sync(port->dev); 790 791 spin_lock_irqsave(&port->lock, flags); 792 port->ops->stop_rx(port); 793 priv->throttled = true; 794 spin_unlock_irqrestore(&port->lock, flags); 795 796 pm_runtime_mark_last_busy(port->dev); 797 pm_runtime_put_autosuspend(port->dev); 798} 799 800static void omap_8250_unthrottle(struct uart_port *port) 801{ 802 struct omap8250_priv *priv = port->private_data; 803 struct uart_8250_port *up = up_to_u8250p(port); 804 unsigned long flags; 805 806 pm_runtime_get_sync(port->dev); 807 808 spin_lock_irqsave(&port->lock, flags); 809 priv->throttled = false; 810 if (up->dma) 811 up->dma->rx_dma(up); 812 up->ier |= UART_IER_RLSI | UART_IER_RDI; 813 port->read_status_mask |= UART_LSR_DR; 814 serial_out(up, UART_IER, up->ier); 815 spin_unlock_irqrestore(&port->lock, flags); 816 817 pm_runtime_mark_last_busy(port->dev); 818 pm_runtime_put_autosuspend(port->dev); 819} 820 821#ifdef CONFIG_SERIAL_8250_DMA 822static int omap_8250_rx_dma(struct uart_8250_port *p); 823 824/* Must be called while priv->rx_dma_lock is held */ 825static void __dma_rx_do_complete(struct uart_8250_port *p) 826{ 827 struct uart_8250_dma *dma = p->dma; 828 struct tty_port *tty_port = &p->port.state->port; 829 struct omap8250_priv *priv = p->port.private_data; 830 struct dma_chan *rxchan = dma->rxchan; 831 dma_cookie_t cookie; 832 struct dma_tx_state state; 833 int count; 834 int ret; 835 u32 reg; 836 837 if (!dma->rx_running) 838 goto out; 839 840 cookie = dma->rx_cookie; 841 dma->rx_running = 0; 842 843 /* Re-enable RX FIFO interrupt now that transfer is complete */ 844 if (priv->habit & UART_HAS_RHR_IT_DIS) { 845 reg = serial_in(p, UART_OMAP_IER2); 846 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 847 serial_out(p, UART_OMAP_IER2, reg); 848 } 849 850 dmaengine_tx_status(rxchan, cookie, &state); 851 852 count = dma->rx_size - state.residue + state.in_flight_bytes; 853 if (count < dma->rx_size) { 854 dmaengine_terminate_async(rxchan); 855 856 /* 857 * Poll for teardown to complete which guarantees in 858 * flight data is drained. 859 */ 860 if (state.in_flight_bytes) { 861 int poll_count = 25; 862 863 while (dmaengine_tx_status(rxchan, cookie, NULL) && 864 poll_count--) 865 cpu_relax(); 866 867 if (poll_count == -1) 868 dev_err(p->port.dev, "teardown incomplete\n"); 869 } 870 } 871 if (!count) 872 goto out; 873 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 874 875 p->port.icount.rx += ret; 876 p->port.icount.buf_overrun += count - ret; 877out: 878 879 tty_flip_buffer_push(tty_port); 880} 881 882static void __dma_rx_complete(void *param) 883{ 884 struct uart_8250_port *p = param; 885 struct omap8250_priv *priv = p->port.private_data; 886 struct uart_8250_dma *dma = p->dma; 887 struct dma_tx_state state; 888 unsigned long flags; 889 890 spin_lock_irqsave(&p->port.lock, flags); 891 892 /* 893 * If the tx status is not DMA_COMPLETE, then this is a delayed 894 * completion callback. A previous RX timeout flush would have 895 * already pushed the data, so exit. 896 */ 897 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 898 DMA_COMPLETE) { 899 spin_unlock_irqrestore(&p->port.lock, flags); 900 return; 901 } 902 __dma_rx_do_complete(p); 903 if (!priv->throttled) { 904 p->ier |= UART_IER_RLSI | UART_IER_RDI; 905 serial_out(p, UART_IER, p->ier); 906 if (!(priv->habit & UART_HAS_EFR2)) 907 omap_8250_rx_dma(p); 908 } 909 910 spin_unlock_irqrestore(&p->port.lock, flags); 911} 912 913static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 914{ 915 struct omap8250_priv *priv = p->port.private_data; 916 struct uart_8250_dma *dma = p->dma; 917 struct dma_tx_state state; 918 unsigned long flags; 919 int ret; 920 921 spin_lock_irqsave(&priv->rx_dma_lock, flags); 922 923 if (!dma->rx_running) { 924 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 925 return; 926 } 927 928 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 929 if (ret == DMA_IN_PROGRESS) { 930 ret = dmaengine_pause(dma->rxchan); 931 if (WARN_ON_ONCE(ret)) 932 priv->rx_dma_broken = true; 933 } 934 __dma_rx_do_complete(p); 935 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 936} 937 938static int omap_8250_rx_dma(struct uart_8250_port *p) 939{ 940 struct omap8250_priv *priv = p->port.private_data; 941 struct uart_8250_dma *dma = p->dma; 942 int err = 0; 943 struct dma_async_tx_descriptor *desc; 944 unsigned long flags; 945 u32 reg; 946 947 if (priv->rx_dma_broken) 948 return -EINVAL; 949 950 spin_lock_irqsave(&priv->rx_dma_lock, flags); 951 952 if (dma->rx_running) { 953 enum dma_status state; 954 955 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 956 if (state == DMA_COMPLETE) { 957 /* 958 * Disable RX interrupts to allow RX DMA completion 959 * callback to run. 960 */ 961 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 962 serial_out(p, UART_IER, p->ier); 963 } 964 goto out; 965 } 966 967 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 968 dma->rx_size, DMA_DEV_TO_MEM, 969 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 970 if (!desc) { 971 err = -EBUSY; 972 goto out; 973 } 974 975 dma->rx_running = 1; 976 desc->callback = __dma_rx_complete; 977 desc->callback_param = p; 978 979 dma->rx_cookie = dmaengine_submit(desc); 980 981 /* 982 * Disable RX FIFO interrupt while RX DMA is enabled, else 983 * spurious interrupt may be raised when data is in the RX FIFO 984 * but is yet to be drained by DMA. 985 */ 986 if (priv->habit & UART_HAS_RHR_IT_DIS) { 987 reg = serial_in(p, UART_OMAP_IER2); 988 reg |= UART_OMAP_IER2_RHR_IT_DIS; 989 serial_out(p, UART_OMAP_IER2, reg); 990 } 991 992 dma_async_issue_pending(dma->rxchan); 993out: 994 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 995 return err; 996} 997 998static int omap_8250_tx_dma(struct uart_8250_port *p); 999 1000static void omap_8250_dma_tx_complete(void *param) 1001{ 1002 struct uart_8250_port *p = param; 1003 struct uart_8250_dma *dma = p->dma; 1004 struct circ_buf *xmit = &p->port.state->xmit; 1005 unsigned long flags; 1006 bool en_thri = false; 1007 struct omap8250_priv *priv = p->port.private_data; 1008 1009 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1010 UART_XMIT_SIZE, DMA_TO_DEVICE); 1011 1012 spin_lock_irqsave(&p->port.lock, flags); 1013 1014 dma->tx_running = 0; 1015 1016 xmit->tail += dma->tx_size; 1017 xmit->tail &= UART_XMIT_SIZE - 1; 1018 p->port.icount.tx += dma->tx_size; 1019 1020 if (priv->delayed_restore) { 1021 priv->delayed_restore = 0; 1022 omap8250_restore_regs(p); 1023 } 1024 1025 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1026 uart_write_wakeup(&p->port); 1027 1028 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1029 int ret; 1030 1031 ret = omap_8250_tx_dma(p); 1032 if (ret) 1033 en_thri = true; 1034 } else if (p->capabilities & UART_CAP_RPM) { 1035 en_thri = true; 1036 } 1037 1038 if (en_thri) { 1039 dma->tx_err = 1; 1040 serial8250_set_THRI(p); 1041 } 1042 1043 spin_unlock_irqrestore(&p->port.lock, flags); 1044} 1045 1046static int omap_8250_tx_dma(struct uart_8250_port *p) 1047{ 1048 struct uart_8250_dma *dma = p->dma; 1049 struct omap8250_priv *priv = p->port.private_data; 1050 struct circ_buf *xmit = &p->port.state->xmit; 1051 struct dma_async_tx_descriptor *desc; 1052 unsigned int skip_byte = 0; 1053 int ret; 1054 1055 if (dma->tx_running) 1056 return 0; 1057 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1058 1059 /* 1060 * Even if no data, we need to return an error for the two cases 1061 * below so serial8250_tx_chars() is invoked and properly clears 1062 * THRI and/or runtime suspend. 1063 */ 1064 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1065 ret = -EBUSY; 1066 goto err; 1067 } 1068 serial8250_clear_THRI(p); 1069 return 0; 1070 } 1071 1072 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1073 if (priv->habit & OMAP_DMA_TX_KICK) { 1074 u8 tx_lvl; 1075 1076 /* 1077 * We need to put the first byte into the FIFO in order to start 1078 * the DMA transfer. For transfers smaller than four bytes we 1079 * don't bother doing DMA at all. It seem not matter if there 1080 * are still bytes in the FIFO from the last transfer (in case 1081 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1082 * leaving the FIFO seem not to trigger the DMA transfer. It is 1083 * really the byte that we put into the FIFO. 1084 * If the FIFO is already full then we most likely got here from 1085 * omap_8250_dma_tx_complete(). And this means the DMA engine 1086 * just completed its work. We don't have to wait the complete 1087 * 86us at 115200,8n1 but around 60us (not to mention lower 1088 * baudrates). So in that case we take the interrupt and try 1089 * again with an empty FIFO. 1090 */ 1091 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1092 if (tx_lvl == p->tx_loadsz) { 1093 ret = -EBUSY; 1094 goto err; 1095 } 1096 if (dma->tx_size < 4) { 1097 ret = -EINVAL; 1098 goto err; 1099 } 1100 skip_byte = 1; 1101 } 1102 1103 desc = dmaengine_prep_slave_single(dma->txchan, 1104 dma->tx_addr + xmit->tail + skip_byte, 1105 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1106 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1107 if (!desc) { 1108 ret = -EBUSY; 1109 goto err; 1110 } 1111 1112 dma->tx_running = 1; 1113 1114 desc->callback = omap_8250_dma_tx_complete; 1115 desc->callback_param = p; 1116 1117 dma->tx_cookie = dmaengine_submit(desc); 1118 1119 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1120 UART_XMIT_SIZE, DMA_TO_DEVICE); 1121 1122 dma_async_issue_pending(dma->txchan); 1123 if (dma->tx_err) 1124 dma->tx_err = 0; 1125 1126 serial8250_clear_THRI(p); 1127 if (skip_byte) 1128 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1129 return 0; 1130err: 1131 dma->tx_err = 1; 1132 return ret; 1133} 1134 1135static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1136{ 1137 switch (iir & 0x3f) { 1138 case UART_IIR_RLSI: 1139 case UART_IIR_RX_TIMEOUT: 1140 case UART_IIR_RDI: 1141 omap_8250_rx_dma_flush(up); 1142 return true; 1143 } 1144 return omap_8250_rx_dma(up); 1145} 1146 1147static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up, 1148 u8 iir, unsigned char status) 1149{ 1150 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1151 (iir & UART_IIR_RDI)) { 1152 if (handle_rx_dma(up, iir)) { 1153 status = serial8250_rx_chars(up, status); 1154 omap_8250_rx_dma(up); 1155 } 1156 } 1157 1158 return status; 1159} 1160 1161static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1162 unsigned char status) 1163{ 1164 /* 1165 * Queue a new transfer if FIFO has data. 1166 */ 1167 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1168 (up->ier & UART_IER_RDI)) { 1169 omap_8250_rx_dma(up); 1170 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1171 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1172 /* 1173 * Disable RX timeout, read IIR to clear 1174 * current timeout condition, clear EFR2 to 1175 * periodic timeouts, re-enable interrupts. 1176 */ 1177 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1178 serial_out(up, UART_IER, up->ier); 1179 omap_8250_rx_dma_flush(up); 1180 serial_in(up, UART_IIR); 1181 serial_out(up, UART_OMAP_EFR2, 0x0); 1182 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1183 serial_out(up, UART_IER, up->ier); 1184 } 1185} 1186 1187/* 1188 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1189 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1190 * use the default routine in the non-DMA case and this one for with DMA. 1191 */ 1192static int omap_8250_dma_handle_irq(struct uart_port *port) 1193{ 1194 struct uart_8250_port *up = up_to_u8250p(port); 1195 struct omap8250_priv *priv = up->port.private_data; 1196 unsigned char status; 1197 unsigned long flags; 1198 u8 iir; 1199 1200 serial8250_rpm_get(up); 1201 1202 iir = serial_port_in(port, UART_IIR); 1203 if (iir & UART_IIR_NO_INT) { 1204 serial8250_rpm_put(up); 1205 return IRQ_HANDLED; 1206 } 1207 1208 spin_lock_irqsave(&port->lock, flags); 1209 1210 status = serial_port_in(port, UART_LSR); 1211 1212 if ((iir & 0x3f) != UART_IIR_THRI) { 1213 if (priv->habit & UART_HAS_EFR2) 1214 am654_8250_handle_rx_dma(up, iir, status); 1215 else 1216 status = omap_8250_handle_rx_dma(up, iir, status); 1217 } 1218 1219 serial8250_modem_status(up); 1220 if (status & UART_LSR_THRE && up->dma->tx_err) { 1221 if (uart_tx_stopped(&up->port) || 1222 uart_circ_empty(&up->port.state->xmit)) { 1223 up->dma->tx_err = 0; 1224 serial8250_tx_chars(up); 1225 } else { 1226 /* 1227 * try again due to an earlier failer which 1228 * might have been resolved by now. 1229 */ 1230 if (omap_8250_tx_dma(up)) 1231 serial8250_tx_chars(up); 1232 } 1233 } 1234 1235 uart_unlock_and_check_sysrq(port, flags); 1236 serial8250_rpm_put(up); 1237 return 1; 1238} 1239 1240static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1241{ 1242 return false; 1243} 1244 1245#else 1246 1247static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1248{ 1249 return -EINVAL; 1250} 1251#endif 1252 1253static int omap8250_no_handle_irq(struct uart_port *port) 1254{ 1255 /* IRQ has not been requested but handling irq? */ 1256 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1257 return 0; 1258} 1259 1260static struct omap8250_dma_params am654_dma = { 1261 .rx_size = SZ_2K, 1262 .rx_trigger = 1, 1263 .tx_trigger = TX_TRIGGER, 1264}; 1265 1266static struct omap8250_dma_params am33xx_dma = { 1267 .rx_size = RX_TRIGGER, 1268 .rx_trigger = RX_TRIGGER, 1269 .tx_trigger = TX_TRIGGER, 1270}; 1271 1272static struct omap8250_platdata am654_platdata = { 1273 .dma_params = &am654_dma, 1274 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1275 UART_RX_TIMEOUT_QUIRK, 1276}; 1277 1278static struct omap8250_platdata am33xx_platdata = { 1279 .dma_params = &am33xx_dma, 1280 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1281}; 1282 1283static struct omap8250_platdata omap4_platdata = { 1284 .dma_params = &am33xx_dma, 1285 .habit = UART_ERRATA_CLOCK_DISABLE, 1286}; 1287 1288static const struct of_device_id omap8250_dt_ids[] = { 1289 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1290 { .compatible = "ti,omap2-uart" }, 1291 { .compatible = "ti,omap3-uart" }, 1292 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1293 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1294 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1295 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1296 {}, 1297}; 1298MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1299 1300static int omap8250_probe(struct platform_device *pdev) 1301{ 1302 struct device_node *np = pdev->dev.of_node; 1303 struct omap8250_priv *priv; 1304 const struct omap8250_platdata *pdata; 1305 struct uart_8250_port up; 1306 struct resource *regs; 1307 void __iomem *membase; 1308 int irq, ret; 1309 1310 irq = platform_get_irq(pdev, 0); 1311 if (irq < 0) 1312 return irq; 1313 1314 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1315 if (!regs) { 1316 dev_err(&pdev->dev, "missing registers\n"); 1317 return -EINVAL; 1318 } 1319 1320 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1321 if (!priv) 1322 return -ENOMEM; 1323 1324 membase = devm_ioremap(&pdev->dev, regs->start, 1325 resource_size(regs)); 1326 if (!membase) 1327 return -ENODEV; 1328 1329 memset(&up, 0, sizeof(up)); 1330 up.port.dev = &pdev->dev; 1331 up.port.mapbase = regs->start; 1332 up.port.membase = membase; 1333 up.port.irq = irq; 1334 /* 1335 * It claims to be 16C750 compatible however it is a little different. 1336 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1337 * have) is enabled via EFR instead of MCR. The type is set here 8250 1338 * just to get things going. UNKNOWN does not work for a few reasons and 1339 * we don't need our own type since we don't use 8250's set_termios() 1340 * or pm callback. 1341 */ 1342 up.port.type = PORT_8250; 1343 up.port.iotype = UPIO_MEM; 1344 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1345 UPF_HARD_FLOW; 1346 up.port.private_data = priv; 1347 1348 up.port.regshift = OMAP_UART_REGSHIFT; 1349 up.port.fifosize = 64; 1350 up.tx_loadsz = 64; 1351 up.capabilities = UART_CAP_FIFO; 1352#ifdef CONFIG_PM 1353 /* 1354 * Runtime PM is mostly transparent. However to do it right we need to a 1355 * TX empty interrupt before we can put the device to auto idle. So if 1356 * PM is not enabled we don't add that flag and can spare that one extra 1357 * interrupt in the TX path. 1358 */ 1359 up.capabilities |= UART_CAP_RPM; 1360#endif 1361 up.port.set_termios = omap_8250_set_termios; 1362 up.port.set_mctrl = omap8250_set_mctrl; 1363 up.port.pm = omap_8250_pm; 1364 up.port.startup = omap_8250_startup; 1365 up.port.shutdown = omap_8250_shutdown; 1366 up.port.throttle = omap_8250_throttle; 1367 up.port.unthrottle = omap_8250_unthrottle; 1368 up.port.rs485_config = serial8250_em485_config; 1369 up.rs485_start_tx = serial8250_em485_start_tx; 1370 up.rs485_stop_tx = serial8250_em485_stop_tx; 1371 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1372 1373 ret = of_alias_get_id(np, "serial"); 1374 if (ret < 0) { 1375 dev_err(&pdev->dev, "failed to get alias\n"); 1376 return ret; 1377 } 1378 up.port.line = ret; 1379 1380 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1381 struct clk *clk; 1382 1383 clk = devm_clk_get(&pdev->dev, NULL); 1384 if (IS_ERR(clk)) { 1385 if (PTR_ERR(clk) == -EPROBE_DEFER) 1386 return -EPROBE_DEFER; 1387 } else { 1388 up.port.uartclk = clk_get_rate(clk); 1389 } 1390 } 1391 1392 if (of_property_read_u32(np, "overrun-throttle-ms", 1393 &up.overrun_backoff_time_ms) != 0) 1394 up.overrun_backoff_time_ms = 0; 1395 1396 priv->wakeirq = irq_of_parse_and_map(np, 1); 1397 1398 pdata = of_device_get_match_data(&pdev->dev); 1399 if (pdata) 1400 priv->habit |= pdata->habit; 1401 1402 if (!up.port.uartclk) { 1403 up.port.uartclk = DEFAULT_CLK_SPEED; 1404 dev_warn(&pdev->dev, 1405 "No clock speed specified: using default: %d\n", 1406 DEFAULT_CLK_SPEED); 1407 } 1408 1409 priv->membase = membase; 1410 priv->line = -ENODEV; 1411 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1412 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1413 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1414 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1415 1416 spin_lock_init(&priv->rx_dma_lock); 1417 1418 platform_set_drvdata(pdev, priv); 1419 1420 device_init_wakeup(&pdev->dev, true); 1421 pm_runtime_enable(&pdev->dev); 1422 pm_runtime_use_autosuspend(&pdev->dev); 1423 1424 /* 1425 * Disable runtime PM until autosuspend delay unless specifically 1426 * enabled by the user via sysfs. This is the historic way to 1427 * prevent an unsafe default policy with lossy characters on wake-up. 1428 * For serdev devices this is not needed, the policy can be managed by 1429 * the serdev driver. 1430 */ 1431 if (!of_get_available_child_count(pdev->dev.of_node)) 1432 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1433 1434 pm_runtime_irq_safe(&pdev->dev); 1435 1436 pm_runtime_get_sync(&pdev->dev); 1437 1438 omap_serial_fill_features_erratas(&up, priv); 1439 up.port.handle_irq = omap8250_no_handle_irq; 1440 priv->rx_trigger = RX_TRIGGER; 1441 priv->tx_trigger = TX_TRIGGER; 1442#ifdef CONFIG_SERIAL_8250_DMA 1443 /* 1444 * Oh DMA support. If there are no DMA properties in the DT then 1445 * we will fall back to a generic DMA channel which does not 1446 * really work here. To ensure that we do not get a generic DMA 1447 * channel assigned, we have the the_no_dma_filter_fn() here. 1448 * To avoid "failed to request DMA" messages we check for DMA 1449 * properties in DT. 1450 */ 1451 ret = of_property_count_strings(np, "dma-names"); 1452 if (ret == 2) { 1453 struct omap8250_dma_params *dma_params = NULL; 1454 1455 up.dma = &priv->omap8250_dma; 1456 up.dma->fn = the_no_dma_filter_fn; 1457 up.dma->tx_dma = omap_8250_tx_dma; 1458 up.dma->rx_dma = omap_8250_rx_dma; 1459 if (pdata) 1460 dma_params = pdata->dma_params; 1461 1462 if (dma_params) { 1463 up.dma->rx_size = dma_params->rx_size; 1464 up.dma->rxconf.src_maxburst = dma_params->rx_trigger; 1465 up.dma->txconf.dst_maxburst = dma_params->tx_trigger; 1466 priv->rx_trigger = dma_params->rx_trigger; 1467 priv->tx_trigger = dma_params->tx_trigger; 1468 } else { 1469 up.dma->rx_size = RX_TRIGGER; 1470 up.dma->rxconf.src_maxburst = RX_TRIGGER; 1471 up.dma->txconf.dst_maxburst = TX_TRIGGER; 1472 } 1473 } 1474#endif 1475 ret = serial8250_register_8250_port(&up); 1476 if (ret < 0) { 1477 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1478 goto err; 1479 } 1480 priv->line = ret; 1481 pm_runtime_mark_last_busy(&pdev->dev); 1482 pm_runtime_put_autosuspend(&pdev->dev); 1483 return 0; 1484err: 1485 pm_runtime_dont_use_autosuspend(&pdev->dev); 1486 pm_runtime_put_sync(&pdev->dev); 1487 flush_work(&priv->qos_work); 1488 pm_runtime_disable(&pdev->dev); 1489 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1490 return ret; 1491} 1492 1493static int omap8250_remove(struct platform_device *pdev) 1494{ 1495 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1496 int err; 1497 1498 err = pm_runtime_resume_and_get(&pdev->dev); 1499 if (err) 1500 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1501 1502 serial8250_unregister_port(priv->line); 1503 priv->line = -ENODEV; 1504 pm_runtime_dont_use_autosuspend(&pdev->dev); 1505 pm_runtime_put_sync(&pdev->dev); 1506 flush_work(&priv->qos_work); 1507 pm_runtime_disable(&pdev->dev); 1508 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1509 device_init_wakeup(&pdev->dev, false); 1510 return 0; 1511} 1512 1513#ifdef CONFIG_PM_SLEEP 1514static int omap8250_prepare(struct device *dev) 1515{ 1516 struct omap8250_priv *priv = dev_get_drvdata(dev); 1517 1518 if (!priv) 1519 return 0; 1520 priv->is_suspending = true; 1521 return 0; 1522} 1523 1524static void omap8250_complete(struct device *dev) 1525{ 1526 struct omap8250_priv *priv = dev_get_drvdata(dev); 1527 1528 if (!priv) 1529 return; 1530 priv->is_suspending = false; 1531} 1532 1533static int omap8250_suspend(struct device *dev) 1534{ 1535 struct omap8250_priv *priv = dev_get_drvdata(dev); 1536 struct uart_8250_port *up = serial8250_get_port(priv->line); 1537 int err = 0; 1538 1539 serial8250_suspend_port(priv->line); 1540 1541 err = pm_runtime_resume_and_get(dev); 1542 if (err) 1543 return err; 1544 if (!device_may_wakeup(dev)) 1545 priv->wer = 0; 1546 serial_out(up, UART_OMAP_WER, priv->wer); 1547 if (uart_console(&up->port) && console_suspend_enabled) 1548 err = pm_runtime_force_suspend(dev); 1549 flush_work(&priv->qos_work); 1550 1551 return err; 1552} 1553 1554static int omap8250_resume(struct device *dev) 1555{ 1556 struct omap8250_priv *priv = dev_get_drvdata(dev); 1557 struct uart_8250_port *up = serial8250_get_port(priv->line); 1558 int err; 1559 1560 if (uart_console(&up->port) && console_suspend_enabled) { 1561 err = pm_runtime_force_resume(dev); 1562 if (err) 1563 return err; 1564 } 1565 1566 serial8250_resume_port(priv->line); 1567 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1568 pm_runtime_mark_last_busy(dev); 1569 pm_runtime_put_autosuspend(dev); 1570 1571 return 0; 1572} 1573#else 1574#define omap8250_prepare NULL 1575#define omap8250_complete NULL 1576#endif 1577 1578#ifdef CONFIG_PM 1579static int omap8250_lost_context(struct uart_8250_port *up) 1580{ 1581 u32 val; 1582 1583 val = serial_in(up, UART_OMAP_SCR); 1584 /* 1585 * If we lose context, then SCR is set to its reset value of zero. 1586 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1587 * among other bits, to never set the register back to zero again. 1588 */ 1589 if (!val) 1590 return 1; 1591 return 0; 1592} 1593 1594/* TODO: in future, this should happen via API in drivers/reset/ */ 1595static int omap8250_soft_reset(struct device *dev) 1596{ 1597 struct omap8250_priv *priv = dev_get_drvdata(dev); 1598 int timeout = 100; 1599 int sysc; 1600 int syss; 1601 1602 /* 1603 * At least on omap4, unused uarts may not idle after reset without 1604 * a basic scr dma configuration even with no dma in use. The 1605 * module clkctrl status bits will be 1 instead of 3 blocking idle 1606 * for the whole clockdomain. The softreset below will clear scr, 1607 * and we restore it on resume so this is safe to do on all SoCs 1608 * needing omap8250_soft_reset() quirk. Do it in two writes as 1609 * recommended in the comment for omap8250_update_scr(). 1610 */ 1611 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1612 uart_write(priv, UART_OMAP_SCR, 1613 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1614 1615 sysc = uart_read(priv, UART_OMAP_SYSC); 1616 1617 /* softreset the UART */ 1618 sysc |= OMAP_UART_SYSC_SOFTRESET; 1619 uart_write(priv, UART_OMAP_SYSC, sysc); 1620 1621 /* By experiments, 1us enough for reset complete on AM335x */ 1622 do { 1623 udelay(1); 1624 syss = uart_read(priv, UART_OMAP_SYSS); 1625 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1626 1627 if (!timeout) { 1628 dev_err(dev, "timed out waiting for reset done\n"); 1629 return -ETIMEDOUT; 1630 } 1631 1632 return 0; 1633} 1634 1635static int omap8250_runtime_suspend(struct device *dev) 1636{ 1637 struct omap8250_priv *priv = dev_get_drvdata(dev); 1638 struct uart_8250_port *up = NULL; 1639 1640 if (priv->line >= 0) 1641 up = serial8250_get_port(priv->line); 1642 1643 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1644 int ret; 1645 1646 ret = omap8250_soft_reset(dev); 1647 if (ret) 1648 return ret; 1649 1650 if (up) { 1651 /* Restore to UART mode after reset (for wakeup) */ 1652 omap8250_update_mdr1(up, priv); 1653 /* Restore wakeup enable register */ 1654 serial_out(up, UART_OMAP_WER, priv->wer); 1655 } 1656 } 1657 1658 if (up && up->dma && up->dma->rxchan) 1659 omap_8250_rx_dma_flush(up); 1660 1661 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1662 schedule_work(&priv->qos_work); 1663 1664 return 0; 1665} 1666 1667static int omap8250_runtime_resume(struct device *dev) 1668{ 1669 struct omap8250_priv *priv = dev_get_drvdata(dev); 1670 struct uart_8250_port *up = NULL; 1671 1672 if (priv->line >= 0) 1673 up = serial8250_get_port(priv->line); 1674 1675 if (up && omap8250_lost_context(up)) 1676 omap8250_restore_regs(up); 1677 1678 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) 1679 omap_8250_rx_dma(up); 1680 1681 priv->latency = priv->calc_latency; 1682 schedule_work(&priv->qos_work); 1683 return 0; 1684} 1685#endif 1686 1687#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1688static int __init omap8250_console_fixup(void) 1689{ 1690 char *omap_str; 1691 char *options; 1692 u8 idx; 1693 1694 if (strstr(boot_command_line, "console=ttyS")) 1695 /* user set a ttyS based name for the console */ 1696 return 0; 1697 1698 omap_str = strstr(boot_command_line, "console=ttyO"); 1699 if (!omap_str) 1700 /* user did not set ttyO based console, so we don't care */ 1701 return 0; 1702 1703 omap_str += 12; 1704 if ('0' <= *omap_str && *omap_str <= '9') 1705 idx = *omap_str - '0'; 1706 else 1707 return 0; 1708 1709 omap_str++; 1710 if (omap_str[0] == ',') { 1711 omap_str++; 1712 options = omap_str; 1713 } else { 1714 options = NULL; 1715 } 1716 1717 add_preferred_console("ttyS", idx, options); 1718 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1719 idx, idx); 1720 pr_err("This ensures that you still see kernel messages. Please\n"); 1721 pr_err("update your kernel commandline.\n"); 1722 return 0; 1723} 1724console_initcall(omap8250_console_fixup); 1725#endif 1726 1727static const struct dev_pm_ops omap8250_dev_pm_ops = { 1728 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1729 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1730 omap8250_runtime_resume, NULL) 1731 .prepare = omap8250_prepare, 1732 .complete = omap8250_complete, 1733}; 1734 1735static struct platform_driver omap8250_platform_driver = { 1736 .driver = { 1737 .name = "omap8250", 1738 .pm = &omap8250_dev_pm_ops, 1739 .of_match_table = omap8250_dt_ids, 1740 }, 1741 .probe = omap8250_probe, 1742 .remove = omap8250_remove, 1743}; 1744module_platform_driver(omap8250_platform_driver); 1745 1746MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1747MODULE_DESCRIPTION("OMAP 8250 Driver"); 1748MODULE_LICENSE("GPL v2"); 1749