1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Mediatek 8250 driver. 4 * 5 * Copyright (c) 2014 MundoReader S.L. 6 * Author: Matthias Brugger <matthias.bgg@gmail.com> 7 */ 8#include <linux/clk.h> 9#include <linux/io.h> 10#include <linux/module.h> 11#include <linux/of_irq.h> 12#include <linux/of_platform.h> 13#include <linux/pinctrl/consumer.h> 14#include <linux/platform_device.h> 15#include <linux/pm_runtime.h> 16#include <linux/serial_8250.h> 17#include <linux/serial_reg.h> 18#include <linux/console.h> 19#include <linux/dma-mapping.h> 20#include <linux/tty.h> 21#include <linux/tty_flip.h> 22 23#include "8250.h" 24 25#define MTK_UART_HIGHS 0x09 /* Highspeed register */ 26#define MTK_UART_SAMPLE_COUNT 0x0a /* Sample count register */ 27#define MTK_UART_SAMPLE_POINT 0x0b /* Sample point register */ 28#define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */ 29#define MTK_UART_ESCAPE_DAT 0x10 /* Escape Character register */ 30#define MTK_UART_ESCAPE_EN 0x11 /* Escape Enable register */ 31#define MTK_UART_DMA_EN 0x13 /* DMA Enable register */ 32#define MTK_UART_RXTRI_AD 0x14 /* RX Trigger address */ 33#define MTK_UART_FRACDIV_L 0x15 /* Fractional divider LSB address */ 34#define MTK_UART_FRACDIV_M 0x16 /* Fractional divider MSB address */ 35#define MTK_UART_DEBUG0 0x18 36#define MTK_UART_IER_XOFFI 0x20 /* Enable XOFF character interrupt */ 37#define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */ 38#define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */ 39 40#define MTK_UART_EFR 38 /* I/O: Extended Features Register */ 41#define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */ 42#define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */ 43#define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */ 44#define MTK_UART_EFR_NO_SW_FC 0x0 /* no sw flow control */ 45#define MTK_UART_EFR_XON1_XOFF1 0xa /* XON1/XOFF1 as sw flow control */ 46#define MTK_UART_EFR_XON2_XOFF2 0x5 /* XON2/XOFF2 as sw flow control */ 47#define MTK_UART_EFR_SW_FC_MASK 0xf /* Enable CTS Modem status interrupt */ 48#define MTK_UART_EFR_HW_FC (MTK_UART_EFR_RTS | MTK_UART_EFR_CTS) 49#define MTK_UART_DMA_EN_TX 0x2 50#define MTK_UART_DMA_EN_RX 0x5 51 52#define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */ 53#define MTK_UART_RX_SIZE 0x8000 54#define MTK_UART_TX_TRIGGER 1 55#define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE 56 57#define MTK_UART_XON1 40 /* I/O: Xon character 1 */ 58#define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */ 59 60#ifdef CONFIG_SERIAL_8250_DMA 61enum dma_rx_status { 62 DMA_RX_START = 0, 63 DMA_RX_RUNNING = 1, 64 DMA_RX_SHUTDOWN = 2, 65}; 66#endif 67 68struct mtk8250_data { 69 int line; 70 unsigned int rx_pos; 71 unsigned int clk_count; 72 struct clk *uart_clk; 73 struct clk *bus_clk; 74 struct uart_8250_dma *dma; 75#ifdef CONFIG_SERIAL_8250_DMA 76 enum dma_rx_status rx_status; 77#endif 78 int rx_wakeup_irq; 79}; 80 81/* flow control mode */ 82enum { 83 MTK_UART_FC_NONE, 84 MTK_UART_FC_SW, 85 MTK_UART_FC_HW, 86}; 87 88#ifdef CONFIG_SERIAL_8250_DMA 89static void mtk8250_rx_dma(struct uart_8250_port *up); 90 91static void mtk8250_dma_rx_complete(void *param) 92{ 93 struct uart_8250_port *up = param; 94 struct uart_8250_dma *dma = up->dma; 95 struct mtk8250_data *data = up->port.private_data; 96 struct tty_port *tty_port = &up->port.state->port; 97 struct dma_tx_state state; 98 int copied, total, cnt; 99 unsigned char *ptr; 100 unsigned long flags; 101 102 if (data->rx_status == DMA_RX_SHUTDOWN) 103 return; 104 105 spin_lock_irqsave(&up->port.lock, flags); 106 107 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 108 total = dma->rx_size - state.residue; 109 cnt = total; 110 111 if ((data->rx_pos + cnt) > dma->rx_size) 112 cnt = dma->rx_size - data->rx_pos; 113 114 ptr = (unsigned char *)(data->rx_pos + dma->rx_buf); 115 copied = tty_insert_flip_string(tty_port, ptr, cnt); 116 data->rx_pos += cnt; 117 118 if (total > cnt) { 119 ptr = (unsigned char *)(dma->rx_buf); 120 cnt = total - cnt; 121 copied += tty_insert_flip_string(tty_port, ptr, cnt); 122 data->rx_pos = cnt; 123 } 124 125 up->port.icount.rx += copied; 126 127 tty_flip_buffer_push(tty_port); 128 129 mtk8250_rx_dma(up); 130 131 spin_unlock_irqrestore(&up->port.lock, flags); 132} 133 134static void mtk8250_rx_dma(struct uart_8250_port *up) 135{ 136 struct uart_8250_dma *dma = up->dma; 137 struct dma_async_tx_descriptor *desc; 138 139 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 140 dma->rx_size, DMA_DEV_TO_MEM, 141 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 142 if (!desc) { 143 pr_err("failed to prepare rx slave single\n"); 144 return; 145 } 146 147 desc->callback = mtk8250_dma_rx_complete; 148 desc->callback_param = up; 149 150 dma->rx_cookie = dmaengine_submit(desc); 151 152 dma_async_issue_pending(dma->rxchan); 153} 154 155static void mtk8250_dma_enable(struct uart_8250_port *up) 156{ 157 struct uart_8250_dma *dma = up->dma; 158 struct mtk8250_data *data = up->port.private_data; 159 int lcr = serial_in(up, UART_LCR); 160 161 if (data->rx_status != DMA_RX_START) 162 return; 163 164 dma->rxconf.src_port_window_size = dma->rx_size; 165 dma->rxconf.src_addr = dma->rx_addr; 166 167 dma->txconf.dst_port_window_size = UART_XMIT_SIZE; 168 dma->txconf.dst_addr = dma->tx_addr; 169 170 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 171 UART_FCR_CLEAR_XMIT); 172 serial_out(up, MTK_UART_DMA_EN, 173 MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX); 174 175 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 176 serial_out(up, MTK_UART_EFR, UART_EFR_ECB); 177 serial_out(up, UART_LCR, lcr); 178 179 if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0) 180 pr_err("failed to configure rx dma channel\n"); 181 if (dmaengine_slave_config(dma->txchan, &dma->txconf) != 0) 182 pr_err("failed to configure tx dma channel\n"); 183 184 data->rx_status = DMA_RX_RUNNING; 185 data->rx_pos = 0; 186 mtk8250_rx_dma(up); 187} 188#endif 189 190static int mtk8250_startup(struct uart_port *port) 191{ 192#ifdef CONFIG_SERIAL_8250_DMA 193 struct uart_8250_port *up = up_to_u8250p(port); 194 struct mtk8250_data *data = port->private_data; 195 196 /* disable DMA for console */ 197 if (uart_console(port)) 198 up->dma = NULL; 199 200 if (up->dma) { 201 data->rx_status = DMA_RX_START; 202 uart_circ_clear(&port->state->xmit); 203 } 204#endif 205 memset(&port->icount, 0, sizeof(port->icount)); 206 207 return serial8250_do_startup(port); 208} 209 210static void mtk8250_shutdown(struct uart_port *port) 211{ 212#ifdef CONFIG_SERIAL_8250_DMA 213 struct uart_8250_port *up = up_to_u8250p(port); 214 struct mtk8250_data *data = port->private_data; 215 216 if (up->dma) 217 data->rx_status = DMA_RX_SHUTDOWN; 218#endif 219 220 return serial8250_do_shutdown(port); 221} 222 223static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask) 224{ 225 serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask)); 226} 227 228static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask) 229{ 230 serial_out(up, UART_IER, serial_in(up, UART_IER) | mask); 231} 232 233static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) 234{ 235 struct uart_port *port = &up->port; 236 int lcr = serial_in(up, UART_LCR); 237 238 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 239 serial_out(up, MTK_UART_EFR, UART_EFR_ECB); 240 serial_out(up, UART_LCR, lcr); 241 lcr = serial_in(up, UART_LCR); 242 243 switch (mode) { 244 case MTK_UART_FC_NONE: 245 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 246 serial_out(up, MTK_UART_ESCAPE_EN, 0x00); 247 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 248 serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) & 249 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))); 250 serial_out(up, UART_LCR, lcr); 251 mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI | 252 MTK_UART_IER_RTSI | MTK_UART_IER_CTSI); 253 break; 254 255 case MTK_UART_FC_HW: 256 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 257 serial_out(up, MTK_UART_ESCAPE_EN, 0x00); 258 serial_out(up, UART_MCR, UART_MCR_RTS); 259 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 260 261 /*enable hw flow control*/ 262 serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC | 263 (serial_in(up, MTK_UART_EFR) & 264 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); 265 266 serial_out(up, UART_LCR, lcr); 267 mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI); 268 mtk8250_enable_intrs(up, MTK_UART_IER_CTSI | MTK_UART_IER_RTSI); 269 break; 270 271 case MTK_UART_FC_SW: /*MTK software flow control */ 272 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 273 serial_out(up, MTK_UART_ESCAPE_EN, 0x01); 274 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 275 276 /*enable sw flow control */ 277 serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 | 278 (serial_in(up, MTK_UART_EFR) & 279 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); 280 281 serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty)); 282 serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty)); 283 serial_out(up, UART_LCR, lcr); 284 mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI); 285 mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI); 286 break; 287 default: 288 break; 289 } 290} 291 292static void 293mtk8250_set_termios(struct uart_port *port, struct ktermios *termios, 294 struct ktermios *old) 295{ 296 unsigned short fraction_L_mapping[] = { 297 0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF 298 }; 299 unsigned short fraction_M_mapping[] = { 300 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3 301 }; 302 struct uart_8250_port *up = up_to_u8250p(port); 303 unsigned int baud, quot, fraction; 304 unsigned long flags; 305 int mode; 306 307#ifdef CONFIG_SERIAL_8250_DMA 308 if (up->dma) { 309 if (uart_console(port)) { 310 devm_kfree(up->port.dev, up->dma); 311 up->dma = NULL; 312 } else { 313 mtk8250_dma_enable(up); 314 } 315 } 316#endif 317 318 /* 319 * Store the requested baud rate before calling the generic 8250 320 * set_termios method. Standard 8250 port expects bauds to be 321 * no higher than (uartclk / 16) so the baud will be clamped if it 322 * gets out of that bound. Mediatek 8250 port supports speed 323 * higher than that, therefore we'll get original baud rate back 324 * after calling the generic set_termios method and recalculate 325 * the speed later in this method. 326 */ 327 baud = tty_termios_baud_rate(termios); 328 329 serial8250_do_set_termios(port, termios, NULL); 330 331 tty_termios_encode_baud_rate(termios, baud, baud); 332 333 /* 334 * Mediatek UARTs use an extra highspeed register (MTK_UART_HIGHS) 335 * 336 * We need to recalcualte the quot register, as the claculation depends 337 * on the vaule in the highspeed register. 338 * 339 * Some baudrates are not supported by the chip, so we use the next 340 * lower rate supported and update termios c_flag. 341 * 342 * If highspeed register is set to 3, we need to specify sample count 343 * and sample point to increase accuracy. If not, we reset the 344 * registers to their default values. 345 */ 346 baud = uart_get_baud_rate(port, termios, old, 347 port->uartclk / 16 / UART_DIV_MAX, 348 port->uartclk); 349 350 if (baud < 115200) { 351 serial_port_out(port, MTK_UART_HIGHS, 0x0); 352 quot = uart_get_divisor(port, baud); 353 } else { 354 serial_port_out(port, MTK_UART_HIGHS, 0x3); 355 quot = DIV_ROUND_UP(port->uartclk, 256 * baud); 356 } 357 358 /* 359 * Ok, we're now changing the port state. Do it with 360 * interrupts disabled. 361 */ 362 spin_lock_irqsave(&port->lock, flags); 363 364 /* 365 * Update the per-port timeout. 366 */ 367 uart_update_timeout(port, termios->c_cflag, baud); 368 369 /* set DLAB we have cval saved in up->lcr from the call to the core */ 370 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 371 serial_dl_write(up, quot); 372 373 /* reset DLAB */ 374 serial_port_out(port, UART_LCR, up->lcr); 375 376 if (baud >= 115200) { 377 unsigned int tmp; 378 379 tmp = (port->uartclk / (baud * quot)) - 1; 380 serial_port_out(port, MTK_UART_SAMPLE_COUNT, tmp); 381 serial_port_out(port, MTK_UART_SAMPLE_POINT, 382 (tmp >> 1) - 1); 383 384 /*count fraction to set fractoin register */ 385 fraction = ((port->uartclk * 100) / baud / quot) % 100; 386 fraction = DIV_ROUND_CLOSEST(fraction, 10); 387 serial_port_out(port, MTK_UART_FRACDIV_L, 388 fraction_L_mapping[fraction]); 389 serial_port_out(port, MTK_UART_FRACDIV_M, 390 fraction_M_mapping[fraction]); 391 } else { 392 serial_port_out(port, MTK_UART_SAMPLE_COUNT, 0x00); 393 serial_port_out(port, MTK_UART_SAMPLE_POINT, 0xff); 394 serial_port_out(port, MTK_UART_FRACDIV_L, 0x00); 395 serial_port_out(port, MTK_UART_FRACDIV_M, 0x00); 396 } 397 398 if ((termios->c_cflag & CRTSCTS) && (!(termios->c_iflag & CRTSCTS))) 399 mode = MTK_UART_FC_HW; 400 else if (termios->c_iflag & CRTSCTS) 401 mode = MTK_UART_FC_SW; 402 else 403 mode = MTK_UART_FC_NONE; 404 405 mtk8250_set_flow_ctrl(up, mode); 406 407 if (uart_console(port)) 408 up->port.cons->cflag = termios->c_cflag; 409 410 spin_unlock_irqrestore(&port->lock, flags); 411 /* Don't rewrite B0 */ 412 if (tty_termios_baud_rate(termios)) 413 tty_termios_encode_baud_rate(termios, baud, baud); 414} 415 416static int __maybe_unused mtk8250_runtime_suspend(struct device *dev) 417{ 418 struct mtk8250_data *data = dev_get_drvdata(dev); 419 struct uart_8250_port *up = serial8250_get_port(data->line); 420 421 /* wait until UART in idle status */ 422 while 423 (serial_in(up, MTK_UART_DEBUG0)); 424 425 if (data->clk_count == 0U) { 426 dev_dbg(dev, "%s clock count is 0\n", __func__); 427 } else { 428 clk_disable_unprepare(data->bus_clk); 429 data->clk_count--; 430 } 431 432 return 0; 433} 434 435static int __maybe_unused mtk8250_runtime_resume(struct device *dev) 436{ 437 struct mtk8250_data *data = dev_get_drvdata(dev); 438 int err; 439 440 if (data->clk_count > 0U) { 441 dev_dbg(dev, "%s clock count is %d\n", __func__, 442 data->clk_count); 443 } else { 444 err = clk_prepare_enable(data->bus_clk); 445 if (err) { 446 dev_warn(dev, "Can't enable bus clock\n"); 447 return err; 448 } 449 data->clk_count++; 450 } 451 452 return 0; 453} 454 455static void 456mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 457{ 458 if (!state) 459 if (!mtk8250_runtime_resume(port->dev)) 460 pm_runtime_get_sync(port->dev); 461 462 serial8250_do_pm(port, state, old); 463 464 if (state) 465 if (!pm_runtime_put_sync_suspend(port->dev)) 466 mtk8250_runtime_suspend(port->dev); 467} 468 469#ifdef CONFIG_SERIAL_8250_DMA 470static bool mtk8250_dma_filter(struct dma_chan *chan, void *param) 471{ 472 return false; 473} 474#endif 475 476static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p, 477 struct mtk8250_data *data) 478{ 479#ifdef CONFIG_SERIAL_8250_DMA 480 int dmacnt; 481#endif 482 483 data->uart_clk = devm_clk_get(&pdev->dev, "baud"); 484 if (IS_ERR(data->uart_clk)) { 485 /* 486 * For compatibility with older device trees try unnamed 487 * clk when no baud clk can be found. 488 */ 489 data->uart_clk = devm_clk_get(&pdev->dev, NULL); 490 if (IS_ERR(data->uart_clk)) { 491 dev_warn(&pdev->dev, "Can't get uart clock\n"); 492 return PTR_ERR(data->uart_clk); 493 } 494 495 return 0; 496 } 497 498 data->bus_clk = devm_clk_get(&pdev->dev, "bus"); 499 if (IS_ERR(data->bus_clk)) 500 return PTR_ERR(data->bus_clk); 501 502 data->dma = NULL; 503#ifdef CONFIG_SERIAL_8250_DMA 504 dmacnt = of_property_count_strings(pdev->dev.of_node, "dma-names"); 505 if (dmacnt == 2) { 506 data->dma = devm_kzalloc(&pdev->dev, sizeof(*data->dma), 507 GFP_KERNEL); 508 if (!data->dma) 509 return -ENOMEM; 510 511 data->dma->fn = mtk8250_dma_filter; 512 data->dma->rx_size = MTK_UART_RX_SIZE; 513 data->dma->rxconf.src_maxburst = MTK_UART_RX_TRIGGER; 514 data->dma->txconf.dst_maxburst = MTK_UART_TX_TRIGGER; 515 } 516#endif 517 518 return 0; 519} 520 521static int mtk8250_probe(struct platform_device *pdev) 522{ 523 struct uart_8250_port uart = {}; 524 struct mtk8250_data *data; 525 struct resource *regs; 526 int irq, err; 527 528 irq = platform_get_irq(pdev, 0); 529 if (irq < 0) 530 return irq; 531 532 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 533 if (!regs) { 534 dev_err(&pdev->dev, "no registers defined\n"); 535 return -EINVAL; 536 } 537 538 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 539 resource_size(regs)); 540 if (!uart.port.membase) 541 return -ENOMEM; 542 543 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 544 if (!data) 545 return -ENOMEM; 546 547 data->clk_count = 0; 548 549 if (pdev->dev.of_node) { 550 err = mtk8250_probe_of(pdev, &uart.port, data); 551 if (err) 552 return err; 553 } else 554 return -ENODEV; 555 556 spin_lock_init(&uart.port.lock); 557 uart.port.mapbase = regs->start; 558 uart.port.irq = irq; 559 uart.port.pm = mtk8250_do_pm; 560 uart.port.type = PORT_16550; 561 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 562 uart.port.dev = &pdev->dev; 563 uart.port.iotype = UPIO_MEM32; 564 uart.port.regshift = 2; 565 uart.port.private_data = data; 566 uart.port.shutdown = mtk8250_shutdown; 567 uart.port.startup = mtk8250_startup; 568 uart.port.set_termios = mtk8250_set_termios; 569 uart.port.uartclk = clk_get_rate(data->uart_clk); 570#ifdef CONFIG_SERIAL_8250_DMA 571 if (data->dma) 572 uart.dma = data->dma; 573#endif 574 575 /* Disable Rate Fix function */ 576 writel(0x0, uart.port.membase + 577 (MTK_UART_RATE_FIX << uart.port.regshift)); 578 579 platform_set_drvdata(pdev, data); 580 581 pm_runtime_enable(&pdev->dev); 582 err = mtk8250_runtime_resume(&pdev->dev); 583 if (err) 584 goto err_pm_disable; 585 586 data->line = serial8250_register_8250_port(&uart); 587 if (data->line < 0) { 588 err = data->line; 589 goto err_pm_disable; 590 } 591 592 data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1); 593 594 return 0; 595 596err_pm_disable: 597 pm_runtime_disable(&pdev->dev); 598 599 return err; 600} 601 602static int mtk8250_remove(struct platform_device *pdev) 603{ 604 struct mtk8250_data *data = platform_get_drvdata(pdev); 605 606 pm_runtime_get_sync(&pdev->dev); 607 608 serial8250_unregister_port(data->line); 609 610 pm_runtime_disable(&pdev->dev); 611 pm_runtime_put_noidle(&pdev->dev); 612 613 if (!pm_runtime_status_suspended(&pdev->dev)) 614 mtk8250_runtime_suspend(&pdev->dev); 615 616 return 0; 617} 618 619static int __maybe_unused mtk8250_suspend(struct device *dev) 620{ 621 struct mtk8250_data *data = dev_get_drvdata(dev); 622 int irq = data->rx_wakeup_irq; 623 int err; 624 625 serial8250_suspend_port(data->line); 626 627 pinctrl_pm_select_sleep_state(dev); 628 if (irq >= 0) { 629 err = enable_irq_wake(irq); 630 if (err) { 631 dev_err(dev, 632 "failed to enable irq wake on IRQ %d: %d\n", 633 irq, err); 634 pinctrl_pm_select_default_state(dev); 635 serial8250_resume_port(data->line); 636 return err; 637 } 638 } 639 640 return 0; 641} 642 643static int __maybe_unused mtk8250_resume(struct device *dev) 644{ 645 struct mtk8250_data *data = dev_get_drvdata(dev); 646 int irq = data->rx_wakeup_irq; 647 648 if (irq >= 0) 649 disable_irq_wake(irq); 650 pinctrl_pm_select_default_state(dev); 651 652 serial8250_resume_port(data->line); 653 654 return 0; 655} 656 657static const struct dev_pm_ops mtk8250_pm_ops = { 658 SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume) 659 SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume, 660 NULL) 661}; 662 663static const struct of_device_id mtk8250_of_match[] = { 664 { .compatible = "mediatek,mt6577-uart" }, 665 { /* Sentinel */ } 666}; 667MODULE_DEVICE_TABLE(of, mtk8250_of_match); 668 669static struct platform_driver mtk8250_platform_driver = { 670 .driver = { 671 .name = "mt6577-uart", 672 .pm = &mtk8250_pm_ops, 673 .of_match_table = mtk8250_of_match, 674 }, 675 .probe = mtk8250_probe, 676 .remove = mtk8250_remove, 677}; 678module_platform_driver(mtk8250_platform_driver); 679 680#ifdef CONFIG_SERIAL_8250_CONSOLE 681static int __init early_mtk8250_setup(struct earlycon_device *device, 682 const char *options) 683{ 684 if (!device->port.membase) 685 return -ENODEV; 686 687 device->port.iotype = UPIO_MEM32; 688 device->port.regshift = 2; 689 690 return early_serial8250_setup(device, NULL); 691} 692 693OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup); 694#endif 695 696MODULE_AUTHOR("Matthias Brugger"); 697MODULE_LICENSE("GPL"); 698MODULE_DESCRIPTION("Mediatek 8250 serial port driver"); 699